KR860002098A - 쇄어드 센스 엠프(Shared sense amplifier) 회로의 구동방법 - Google Patents
쇄어드 센스 엠프(Shared sense amplifier) 회로의 구동방법 Download PDFInfo
- Publication number
- KR860002098A KR860002098A KR1019850003292A KR850003292A KR860002098A KR 860002098 A KR860002098 A KR 860002098A KR 1019850003292 A KR1019850003292 A KR 1019850003292A KR 850003292 A KR850003292 A KR 850003292A KR 860002098 A KR860002098 A KR 860002098A
- Authority
- KR
- South Korea
- Prior art keywords
- bit line
- sense amplifier
- electrical
- bit
- pair
- Prior art date
Links
- 238000000034 method Methods 0.000 claims 5
- 230000008878 coupling Effects 0.000 claims 4
- 238000010168 coupling process Methods 0.000 claims 4
- 238000005859 coupling reaction Methods 0.000 claims 4
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (4)
- 센스 엠프화, 제1의 비트선과 제2의 비트선으로 행성된 제1비트라인 쌍과 전기 제1비트선을 전기 센스엠프에 결합시키기 위한 제1트랜스퍼 트랜지스터와, 전기 제2비트선을 전기 센스엠프에 결합시키기 위한 제2트랜스퍼 트랜지스터와, 제3비트선과 제4비트선으로 행성된 제2비트라인 쌍과, 전기 제3비트선을 전기 센스엠프에 결합시키기 위한 제3트랜스퍼 트랜지스터어와, 전기 제4비트신을 전기 센스엠프에 결합시키기 위한 제4트랜스퍼 트랜지스터와를 구비한 쇄어드 센스 엠프회로를 구동하는 방법으로써, 전기 제1비트 라인 쌍이 선택된 경우에는 전기 제3 및 제4트랜스퍼 트랜지스터의 게이트 전위를 전기 제2의 비트라인 쌍의 프리 차아지 전위와 동등하게 하므로서 제2비트라인 쌍을 전기 센스엠프에서 일시적으로 단절시킴과 동시에 센스 엠프의 증폭 동작에 의하여 자동적으로 재접속하고, 전기 제2의 비트라인 조가 선택된 경우에는, 전기 제1 및 제2트랜스퍼 트랜지스터의 게이트 전위를 전기 제1의 비트라인 조의 프리 챠아저 전위와 동등하게 하므로서, 전기 제1비트라인 조를 전기 센스 엠프에서 일시적으로 단절함과 동시에 센스 엠프의 증폭 동작에 의하여 자동전으로 재접속하는 것을 특징으로 한 쇄어드 센스 엠프 회로의 구동방법.
- 제1항에 있어서, 판독동작 이전에는 전기 제1,제2 및 제3,제4의 트랜스퍼 트랜지스터의 게이트 전위를 각기 제1 및 제2의 비트라인 조의 프리 챠야지 전위와 그들의 트랜지스터의 최저치값 전압의 합산치보다도 높게하는 것을 특징으로 하는 셔어드 센스 엠프 회로의 구동방법.
- 제1항 또는 제2항에 있어서, 전기 제1 및 제2의 비트라인 쌍은 각기 절환행 비트랑니으로 행성되는 셔어드 센스 엠프 회로의 구동방법.
- 제1항 또는 제2항에 있어서, 전기 제1 및 제2의 비트라인 쌍은 같기 오픈행 비트라인으로 행성되는 셔어드 센서 엠프 회로의 구동방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59172005A JPS6150284A (ja) | 1984-08-17 | 1984-08-17 | シエアドセンスアンプ回路の駆動方法 |
JP59-172005 | 1984-08-17 | ||
JP172005 | 1984-08-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860002098A true KR860002098A (ko) | 1986-03-26 |
KR900008613B1 KR900008613B1 (ko) | 1990-11-26 |
Family
ID=15933751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850003292A KR900008613B1 (ko) | 1984-08-17 | 1985-05-14 | 쇄어드 센스앰프(Shared sense amplifier)회로의 구동방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4710901A (ko) |
JP (1) | JPS6150284A (ko) |
KR (1) | KR900008613B1 (ko) |
DE (1) | DE3529476A1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6280897A (ja) * | 1985-10-04 | 1987-04-14 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5058073A (en) * | 1988-03-10 | 1991-10-15 | Oki Electric Industry Co., Ltd. | CMOS RAM having a complementary channel sense amplifier |
US5148399A (en) * | 1988-06-28 | 1992-09-15 | Oki Electric Industry Co., Ltd. | Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory |
US4969125A (en) * | 1989-06-23 | 1990-11-06 | International Business Machines Corporation | Asynchronous segmented precharge architecture |
US5270591A (en) * | 1992-02-28 | 1993-12-14 | Xerox Corporation | Content addressable memory architecture and circuits |
US5721875A (en) * | 1993-11-12 | 1998-02-24 | Intel Corporation | I/O transceiver having a pulsed latch receiver circuit |
JPH08171796A (ja) * | 1994-12-16 | 1996-07-02 | Toshiba Corp | 半導体記憶装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4061999A (en) * | 1975-12-29 | 1977-12-06 | Mostek Corporation | Dynamic random access memory system |
US4053873A (en) * | 1976-06-30 | 1977-10-11 | International Business Machines Corporation | Self-isolating cross-coupled sense amplifier latch circuit |
JPS5457921A (en) * | 1977-10-18 | 1979-05-10 | Fujitsu Ltd | Sense amplifier circuit |
US4233675A (en) * | 1979-06-08 | 1980-11-11 | National Semiconductor Corporation | X Sense AMP memory |
JPS5693178A (en) * | 1979-12-26 | 1981-07-28 | Toshiba Corp | Semiconductor memory device |
US4287576A (en) * | 1980-03-26 | 1981-09-01 | International Business Machines Corporation | Sense amplifying system for memories with small cells |
JPS6045499B2 (ja) * | 1980-04-15 | 1985-10-09 | 富士通株式会社 | 半導体記憶装置 |
US4363111A (en) * | 1980-10-06 | 1982-12-07 | Heightley John D | Dummy cell arrangement for an MOS memory |
US4351034A (en) * | 1980-10-10 | 1982-09-21 | Inmos Corporation | Folded bit line-shared sense amplifiers |
JPS5873095A (ja) * | 1981-10-23 | 1983-05-02 | Toshiba Corp | ダイナミツク型メモリ装置 |
JPS5995728A (ja) * | 1982-11-24 | 1984-06-01 | Sanyo Electric Co Ltd | Most出力回路 |
-
1984
- 1984-08-17 JP JP59172005A patent/JPS6150284A/ja active Pending
-
1985
- 1985-05-14 KR KR1019850003292A patent/KR900008613B1/ko not_active IP Right Cessation
- 1985-08-16 DE DE19853529476 patent/DE3529476A1/de active Granted
- 1985-08-19 US US06/767,193 patent/US4710901A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3529476C2 (ko) | 1990-06-13 |
JPS6150284A (ja) | 1986-03-12 |
DE3529476A1 (de) | 1986-02-27 |
US4710901A (en) | 1987-12-01 |
KR900008613B1 (ko) | 1990-11-26 |
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