KR20210087101A - Methods of patterning metal layers - Google Patents

Abstract

The present disclosure provides methods for patterning a metal layer of a device (eg, a semiconductor device) to form features in the interconnect layer as part of a process for manufacturing an interconnect structure of the device. The disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides methods for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.

Description

Methods of patterning metal layers

[0001] Embodiments of the present disclosure relate to methods for forming semiconductor device structures. More specifically, embodiments of the present disclosure relate to methods of patterning metal layers on a substrate.

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. Evolution in chip design has resulted in greater circuit density, improving the process capability and speed of chips. Demands for faster processing capability with greater circuit densities place corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to a scale of less than 10 nm, low dielectric constant insulating materials as well as low resistivity conductive materials are used to obtain adequate electrical performance from such components.

[0003] Interconnects provide electrical connections between the various electronic components of an integrated circuit, and external contact elements (eg, pins) of a device and these components for connecting the integrated circuit to other circuits. form connections between them. Traditionally, copper has been the material of choice for interconnect layers. However, at scales below 10 nm, conventional copper interconnects exhibit reduced conductivity, making copper an undesirable material for advanced nodes. Recently, alternative materials have been sought to overcome the defects of copper as an interconnect material. One such material is molybdenum. Molybdenum interconnects exhibit desirable electrical properties even at the sub-10 nm scale. However, because molybdenum is a high hardness metal, molybdenum interconnect layers are still difficult to pattern during semiconductor device fabrication.

[0004] Accordingly, there is a need in the art for improved methods for patterning molybdenum layers.

[0005] In one embodiment, a method of patterning a molybdenum interconnect layer is provided. The method includes forming a molybdenum layer on a substrate. A masking layer is then formed over the molybdenum layer and patterned to expose regions of the molybdenum layer to the periphery. Exposed regions of molybdenum are modified with oxygen to form molybdenum oxide portions of the molybdenum interconnect layer. After modification, the molybdenum oxide portions of the molybdenum interconnect layer are removed from the substrate through an etching process.

[0006] In one embodiment, a method of forming a metal interconnect layer on a patterned substrate is provided. The method includes forming a molybdenum layer on the patterned substrate. A masking layer is formed on the molybdenum layer, and the masking layer is patterned to expose undesired regions of the molybdenum layer to the periphery. The patterned substrate is then exposed to a neutral particle beam to remove unwanted regions of the molybdenum layer.

[0007] In one embodiment, a method of patterning a metal interconnect layer on a substrate is provided. The method includes forming a molybdenum interconnect layer on a substrate. A mask is formed on the molybdenum layer and patterned to expose regions of the molybdenum interconnect layer. The substrate is then placed into a substrate processing region of the substrate processing chamber, and a partial pressure in the range of about 20 bar to about 55 bar and a partial pressure in the range of about 250°C to about 550°C to remove the exposed regions of the molybdenum interconnect layer. It is exposed to _{gaseous H 2} O at temperatures within the range.

[0008] In such a way that the above-listed features of the present disclosure may be understood in detail, a more specific description of the present disclosure, briefly summarized above, may be made with reference to embodiments, some of which are appended It is illustrated in the drawings. It should be noted, however, that the appended drawings illustrate only exemplary embodiments and are not to be considered limiting of the scope of the present disclosure, but may admit to other equally effective embodiments.
1 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to an embodiment of the present disclosure;
2A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on a substrate are removed, in accordance with an embodiment of the present disclosure;
2B illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on a substrate have been modified, in accordance with an embodiment of the present disclosure.
2C illustrates a schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after portions of one or more layers on a substrate have been modified, in accordance with an embodiment of the present disclosure.
2D illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been removed, in accordance with an embodiment of the present disclosure;
3 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to an embodiment of the present disclosure;
4A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on a substrate are removed, in accordance with an embodiment of the present disclosure;
4B illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been removed, in accordance with an embodiment of the present disclosure.
4C illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after additional portions of one or more layers on the substrate have been removed, in accordance with an embodiment of the present disclosure.
5 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to an embodiment of the present disclosure;
To facilitate understanding, identical reference numbers have been used where possible to designate identical elements that are common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0020] The present disclosure provides methods for patterning a metal layer of a device (eg, a semiconductor device) to form features in the interconnect layer as part of a process for manufacturing an interconnect structure of the device. The disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides methods for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.

[0021] 1 is a flow diagram of a method 100 for patterning a molybdenum layer of a device, such as a semiconductor device, according to one embodiment. In some embodiments, a molybdenum layer may be disposed directly over the substrate surface. In some embodiments, the molybdenum layer may be disposed on another metal layer, such as a barrier metal layer. In other embodiments, a molybdenum layer may be disposed on a dielectric layer, such as a silicon dioxide layer. The patterning of the molybdenum layer can be used to fabricate the interconnect structure of the device. The patterning method 100 may be performed in a process chamber, such as a plasma process chamber or other suitable process chamber. The following describes the method 100 of FIG. 1 in conjunction with the figures shown in FIGS. 2A-2C , which show a device comprising a molybdenum layer at different stages of the method 100 . Moreover, although method 100 is described below with reference to a molybdenum layer utilized to form an interconnect structure, method 100 may also be advantageously used for other metal-containing layers and in other semiconductor device manufacturing applications. can

[0022] In operation 102 , a semiconductor device 200 (see FIG. 2A ) comprising a molybdenum layer 202 is positioned in a plasma process chamber, such as an etch process chamber (not shown). The semiconductor device 200 may include one or more semiconductor devices that are in a manufacturing process or at various stages of fabrication. 2A is a schematic cross-sectional view of a portion of a semiconductor device 200 including a molybdenum layer 202 before portions of one or more layers disposed on a substrate 201 are removed, according to one embodiment. The diagram of FIG. 2A shows the semiconductor device 200 before an initial patterning process (eg, an oxidation process) is performed to modify portions of the molybdenum layer 202 .

[0023] The semiconductor device 200 includes a substrate 201 . Substrate 201 may be formed of any suitable material, such as silicon, crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, silicon on insulator (SOI), among other materials. , carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. In some embodiments, the substrate 201 is a 200 mm, 300 mm, 450 mm, or other diameter circular substrate. In other embodiments, the substrate 201 is a rectangular substrate or a square substrate. In embodiments where SOI is used for the substrate 201 , the substrate 201 may further include a buried dielectric layer disposed on a silicon crystalline substrate.

[0024] A molybdenum layer 202 is disposed on the substrate 201 . In one embodiment, the molybdenum layer 202 is disposed directly over and in contact with the substrate 201 . In other embodiments, the molybdenum layer 202 may be disposed on an intermediate layer (not shown), such as a dielectric layer. In these embodiments, the intermediate layer is disposed directly over and in contact with the substrate 201 , and the molybdenum layer 202 is disposed on the intermediate layer. The molybdenum layer 202 is used as an interconnect layer to connect multiple elements or devices of an integrated circuit.

The semiconductor device 200 further includes a masking layer 203 during one or more fabrication stages. The masking layer 203 may be formed directly over the molybdenum layer 202 , or on an intermediate layer (not shown), such as a dielectric layer. In some embodiments, the masking layer is formed of a material that does not react to wet etching solutions. In some embodiments, the masking layer is formed of a low hardness material. In other embodiments, the masking layer 203 is a hard mask, such as a carbon hard mask. In addition to or alternatively to the carbon hard mask, the masking layer 203 may be formed of other high hardness materials. Examples of high hardness materials are tungsten carbide (WC), tungsten boron carbide (WBC), tungsten nitride (WN), silicon boride (SiB _x ), boron carbide (BC), amorphous carbon, boron nitride (BN), boron carbon nitride (BCN), or other similar materials, including but not limited to. The masking layer 203 materials described above may include compounds (eg, chemical compounds of equal parts tungsten and carbon, stoichiometric compounds, etc.) or doped materials (eg, a tungsten layer containing a small percentage of carbon). ) may be included. In some embodiments that may be combined with other embodiments described herein, the masking layer 203 is formed of photosensitive materials, such as naphthoquinone diazide (NQD) or other suitable photoreactive materials. is the resist

[0026] In some embodiments, the substrate 201 is a thermally oxidized substrate. In embodiments involving a thermally oxidized substrate, the molybdenum layer 202 may be formed directly over the substrate 201 . The thermally oxidized substrate includes oxygen at its surface in contact with the molybdenum layer 202 . As described below, when portions of the molybdenum layer 202 are removed to expose the thermally oxidized substrate, oxygen from the thermally oxidized substrate is transferred to a passivation layer on the exposed surface of the semiconductor device 200 . used to form (not shown). The passivation layer stops or substantially reduces further etching when the etching process breaks through the molybdenum layer 202 . For example, oxygen from a thermally oxidized substrate is used to etch the molybdenum layer 202 to form a passivation layer of silicon oxide on exposed portions of the semiconductor device 200 to stop the etching process. It can be combined with silicon atoms from a silicon-containing gas. Although the passivation layer is described herein as being formed in part by oxygen from a thermally oxidized substrate, the oxygen may come from a layer comprising oxygen, immediately beneath the molybdenum layer 202 .

[0027] In some embodiments, semiconductor device 200 may further include a barrier layer (not shown) and a low-k insulating dielectric layer (not shown). A low-k insulating dielectric layer is disposed over the substrate 201 between the molybdenum layer 202 and the substrate 201 . A barrier layer may be disposed over the low-k insulating dielectric layer between the molybdenum layer 202 and the low-k insulating dielectric layer. The barrier layer includes tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), silicon nitride (SiN), silicon oxynitride (SiON), silicon It may be made of carbide (SiC), (silicon isocyanide) SiNC, silicon oxycarbide (SiOC), or other suitable materials. In addition, the low-k insulating dielectric layer may be formed of SiO containing materials, SiN containing materials, SiOC containing materials, SiC containing materials, carbon based materials, or other suitable materials.

[0028] In operation 104 , portions of the masking layer 203 are removed to form exposed portions 222 of the molybdenum layer 202 , as shown in FIG. 2B . 2B is a schematic cross-sectional view of a portion of a semiconductor device 200 including a molybdenum layer 202 after portions of a masking layer 203 disposed on the molybdenum layer 202 have been removed, according to one embodiment. . Removal of these portions of the masking layer 203 forms in the masking layer 203 voids 205 , shown as trenches in FIG. 2B , the bottom of which is the exposed portion of the molybdenum layer 202 . formed by portions 222 (ie, bounded or partially defined). Accordingly, removal of portions of masking layer 203 exposes portions of molybdenum layer 202 .

[0029] The use of the materials described above for the masking layer 203 (i.e., high hardness materials, such as WC) may improve the process of selectively etching features over the molybdenum layer 202, but in turn the masking layer ( Portions or all of 203 are removed to form features, such as transistor structures, on the device.

[0030] In operation 106 , the exposed portions 222 of the molybdenum layer 202 are modified. In one embodiment, the exposed portions 222 are oxidized to form molybdenum oxide portions 223 . 2C is a schematic cross-sectional view of a portion of the semiconductor device 200 including the molybdenum layer 202 after the exposed portions 222 of the molybdenum layer 202 have been oxidized, according to one embodiment.

The exposed portions 222 may be oxidized by various methods including, but not limited to, direct oxygen ion implantation or oxygen plasma doping. For example, implanted oxygen ions may be bombarded in a substantially perpendicular path to the exposed portions 222 of the molybdenum layer 202 to penetrate the exposed portions 222 . The implanted ions may penetrate the exposed portions 222 at various depths depending on the power and bias utilized to energize the oxygen ions. For example, the exposed portions 222 may have an accelerating voltage of from about 5 KeV to about 30 KeV, such as from about 10 KeV to about 20 KeV, and from about 0.5E16 ion/cm ² to about 5E17 ion/cm ² , such as, Energized oxygen ions may be implanted at a dose ranging from about 1E16 ion/cm ² to about 1E17 ion/cm ^{2 .} For example, the exposed portions 222 may be implanted with oxygen ions ^{energized at 10 KeV and dosed at 1E17 ion/cm 2 .}

[0032] Ion implantation may be performed by beamline or plasma implantation tools. Suitable processing platform, available commercially that can be used to advantage according to embodiments described herein is available commercially available VIISTA ^® PLAD ™ platform from California, Santa Clara, Applied Materials, Inc.. It is contemplated that other suitably configured implantation technology platforms from other manufacturers may also be used in accordance with embodiments herein.

[0033] In some embodiments, after oxygen ion implantation of exposed portions 222 , semiconductor device 200 is annealed to form a polycrystalline structure of molybdenum oxide portions 223 . The semiconductor device 200 is annealed by various methods, such as furnace annealing or rapid thermal annealing, such as lamp-based or laser annealing. In one embodiment, the device structure 200 is annealed at a temperature of about 200° C. to about 600° C., a water vapor pressure of about 0.5 bar to about 75 bar, and a duration of about 15 minutes to about 2 hours. In some examples, device structure 200 is annealed to a temperature of about 250°C to about 550°C, such as about 300°C to about 500°C, such as about 350°C to about 450°C. In some examples, device structure 200 is annealed at a pressure of about 25 bar to about 55 bar, such as about 30 bar to about 50 bar, such as about 35 bar to about 45 bar. In some examples, device structure 200 is annealed for a duration of between about 30 minutes and about 1.5 hours, such as between 45 minutes and 75 minutes. In one example, device structure 200 is annealed at conditions of 325° C. and 55 bar for about 60 minutes.

[0034] In some embodiments, the thermal annealing is performed at high pressure and in the presence of a processing gas such as hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases for high pressure gas annealing. Annealing the semiconductor device 200 at high pressure levels makes it possible to form a polycrystalline structure of the molybdenum oxide portions 223 even at low temperatures, such as below 350°C.

In operation 108 , molybdenum oxide portions 223 are removed from semiconductor device 200 to form patterned molybdenum layer 204 . 2D is a schematic cross-sectional view of the portion of the substrate 201 including the patterned molybdenum layer 204 after the molybdenum oxide portions 223 have been removed. Removal of molybdenum oxide portions 223 is shown as trenches in FIG. 2D . Gaps 205 are formed in the patterned molybdenum layer 204 , the bottom of which is formed by the top surface 207 of the substrate 201 .

[0036] Molybdenum oxide portions 223 may be removed from substrate 201 by any suitable etching process selective for molybdenum oxide, including wet etching or dry etching processes. For example, molybdenum oxide portions 223 are removed from the substrate 201 by wet etching using an ammonia solution. The ammonia solution is selective for the oxidized portions 223 . Thus, the oxidized portions 223 are removed, while the unoxidized patterned molybdenum layer 204 is not removed by the ammonia solution. The ammonia solution may comprise ammonia hydroxide at a concentration of about 26% w/w to about 30% w/w, such as about 28% w/w. The semiconductor device 200 may be exposed to an ammonia solution to etch a desired depth of the molybdenum oxide portions 223 , such as for a duration of about 2 minutes to about 10 minutes.

[0037] In another example that may be combined with the examples and embodiments described herein, molybdenum oxide portions 223 are removed from semiconductor device 200 by wet etching using a pH 10 buffer solution. A pH 10 buffered solution contains a sodium compound, such as sodium tetraborate or sodium hydroxide. The semiconductor device 200 may be exposed to a pH 10 buffer solution to etch a desired depth of the molybdenum oxide portions 223 , such as for a duration of about 2 minutes to about 10 minutes. The use of an ammonia solution or a pH 10 buffer solution to selectively etch the molybdenum oxide portions 223 does not damage the unoxidized patterned molybdenum layer 204 or other material layers and device structures of the semiconductor device 200 . The molybdenum oxide portions 223 are etched without

[0038] 3 is a flow diagram of a method 300 for patterning a molybdenum layer of a device, such as a semiconductor device, by neutral atom beam etching, according to one embodiment. Similar to the embodiment shown in FIGS. 1 and 2 , the molybdenum layer 202 may be disposed directly over the substrate 201 , or on another layer, such as a metal layer or a dielectric layer. The patterning of the molybdenum layer 202 according to this embodiment can be used to fabricate the interconnect structure of the semiconductor device 200 . The patterning method 300 is performed in a process chamber, such as a plasma process chamber or a neutral atom beam etching apparatus. Next, the method 300 of FIG. 3 is illustrated in FIGS. 4A-4C , which show the semiconductor device 200 of FIG. 2 including a molybdenum layer 202 at different stages of the method 300 . explain with Moreover, although method 300 is described below with reference to a molybdenum layer 202 utilized to form an interconnect structure, method 300 also applies to materials other than molybdenum, and other semiconductor device manufacturing applications. can be advantageously used in

[0039] In operation 302 , a semiconductor device 200 (see FIG. 4A ) comprising a molybdenum layer 202 is positioned in a plasma process chamber, such as an etch process chamber (not shown). The semiconductor device 200 may include one or more semiconductor devices that are in a manufacturing process or at various stages of fabrication. 4A is a schematic cross-sectional view of a portion of a semiconductor device 200 including a molybdenum layer 202 before portions of one or more layers disposed on a substrate 201 are removed, according to one embodiment. The diagram of FIG. 4A shows the semiconductor device 200 before a patterning process (eg, neutral beam etching) is performed to modify portions of the molybdenum layer 202 .

[0040] In operation 304 , portions of the masking layer 203 are removed to form exposed portions 222 of the molybdenum layer 202 , as shown in FIG. 4B . 4B is a schematic cross-sectional view of a portion of a semiconductor device 200 including a molybdenum layer 202 after portions of a masking layer 203 disposed on the molybdenum layer 202 have been removed, according to one embodiment. . Removal of these portions of the masking layer 203 forms in the masking layer 203 voids 205 , shown as trenches in FIG. 4B , the bottom of which is the exposed portion of the molybdenum layer 202 . formed by portions 222 (ie, bounded or partially defined). Accordingly, removal of portions of masking layer 203 exposes portions of molybdenum layer 202 .

[0041] In operation 306 , exposed portions of molybdenum layer 202 are removed from semiconductor device 200 to form patterned molybdenum layer 204 . 4C is a schematic cross-sectional view of a portion of semiconductor device 200 including patterned molybdenum layer 204 after exposed portions 222 of molybdenum layer 202 have been removed. Removal of the exposed portions 222 forms in the patterned molybdenum layer 204 voids 205 , shown as trenches in FIG. 4C , the bottom of which is the top surface of the substrate 201 . is formed by

[0042] 3 and 4 , the exposed portions 222 of the molybdenum layer 202 may be removed from the semiconductor device 200 by an accelerated atomic beam process. A suitable commercially available processing platform that may be advantageously utilized in accordance with the embodiments described herein is the NanoAccel™ platform available from Exogenesis Corp. of Billerica, Massachusetts. It is contemplated that other suitably configured accelerated atomic beam platforms from other manufacturers may also be used in accordance with embodiments herein.

In one example, the exposed portions 222 of the molybdenum layer 202 may be removed by a gas cluster ion beam (GCIB) etch. During the GCIB etching of the molybdenum layer 202 , a pressurized inert gas flows, expands, and accelerates toward the exposed portions 222 of the molybdenum layer 202 within the processing chamber so that the exposed portions 222 are etched. It can transfer energy to the outermost atoms and cause the removal of the outermost atoms. In one embodiment, the gas cluster ion beam is formed of argon gas. In other embodiments, _{additional gases including oxygen (O 2} ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ) may be combined with an inert gas to form a gas cluster ion beam. can

[0044] A gas cluster ion beam may be directed in a substantially vertical path through the pores 205 in the masking layer 203 to penetrate desired portions of the molybdenum layer 202 to form a patterned molybdenum layer 204 . have. Accordingly, other device structures or material layers on the semiconductor device 200 are left intact during gas cluster ion beam etching. The gas cluster ion beam may be accelerated to an accelerating voltage between 10 KeV and 40 KeV, such as between 15 KeV and 35 KeV. For example, a gas cluster ion beam is accelerated with an accelerating voltage of 25 KeV. The semiconductor device 200 may be exposed to the gas cluster ion beam for any suitable dose time, such as from about 0 seconds to about 30 seconds, including 2-20 seconds. For example, the semiconductor device 200 may be exposed to the gas cluster ion beam for a dose time of 6, 8, 10, 14, or 18 seconds.

[0045] In another example that may be combined with the embodiments and examples described herein, an accelerated neutral atom beam (ANAB) etch is performed to remove the exposed portions 222 of the molybdenum layer 202 from the semiconductor device 200 . this is used Similar to GCIB etching, accelerated neutral atom beam etching utilizes an accelerated beam of gas cluster ions, but the gas cluster dissociates and the charge is removed before impacting the surface of the exposed portions 222 . The accelerated neutral atom beam is directed in a substantially vertical path through the pores 205 in the masking layer 203 to penetrate desired portions of the molybdenum layer 202 . Also, each atom inside the neutral atom beam has a relatively low energy, causing limited surface modification of only a few atomic layers, thus significantly reducing etch damage to other materials and layers or semiconductor device 200 . reduce or eliminate

[0046] The accelerated neutral atom beam is accelerated with an acceleration voltage of 10 KeV to 40 KeV, such as 15 KeV to 35 KeV. For example, an accelerated neutral atom beam is accelerated to an accelerating voltage of 25 KeV. The semiconductor device 200 is exposed to the accelerated neutral atom beam for any suitable dose time, such as from about 0 seconds to about 30 seconds, including 2-20 seconds. For example, the semiconductor device 200 may be exposed to the accelerated neutral atom beam for a dose time of 6, 8, 10, 14, or 18 seconds. Inert gases, such as argon, may be used to form the accelerated neutral atom beam. In some embodiments, _{additional gases including oxygen (O 2} ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ) may be combined with the inert gas. The ANAB etch may be performed at any suitable etch conditions.

[0047] 5 is a flow diagram of a method 500 for patterning a molybdenum layer of a device, such as a semiconductor device, by high pressure water anneal, according to one embodiment. Similar to the embodiments shown in FIGS. 1-4 , a molybdenum layer may be disposed directly over the substrate surface or on another layer, such as a metal layer or a dielectric layer. The patterning of a molybdenum layer according to this embodiment, which can be combined with other embodiments and examples described herein, can be used to fabricate an interconnect structure of a device. The patterning method 500 is performed in a plasma process chamber, such as an etch process chamber or other suitable process apparatus. Although method 500 is described below with reference to a molybdenum layer utilized to form an interconnect structure, method 500 may also be advantageously used with materials other than molybdenum, and in other semiconductor device manufacturing applications. have.

[0048] At operation 502 , a semiconductor device comprising a molybdenum layer is positioned in a plasma process chamber, such as an etch process chamber (not shown). A semiconductor device may include one or more semiconductor devices that are in a manufacturing process. The semiconductor device further comprises a substrate, a molybdenum layer disposed over the substrate, and a masking layer, eg, similar to the substrate 201 , the molybdenum layer 202 , and the masking layer 203 described in connection with FIGS. 2 and 4 . include The semiconductor device may also include other material layers disposed on the substrate, such as a barrier layer or a low-k insulating layer.

[0049] At operation 504 , portions of the masking layer are removed to form exposed portions of the molybdenum layer. Removal of these portions of the masking layer forms pores 205 in the masking layer, the bottom of which is formed by the exposed portions of the molybdenum layer. Removal of portions of the masking layer exposes portions of the molybdenum layer.

[0050] At operation 506 , the semiconductor device is exposed to a high pressure water anneal (HPWA) process to remove the exposed portions of the molybdenum layer from the semiconductor device. Although method 500 describes high pressure water annealing that utilizes water vapor to anneal the semiconductor device, it is contemplated that other gases may be used to anneal the semiconductor device under high pressure. For example, the semiconductor device may be annealed at high pressure using hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases. In another example, the semiconductor device may be annealed using a combination of gases including hydrogen, deuterium, fluorine, chlorine, ammonium, and other suitable gases.

[0051] In operation 506, the processing chamber is pressurized by supplying water vapor from the pressure chamber to the processing chamber, followed by thermal annealing of the device and depressurization of the processing chamber by evacuation of the water vapor. Thermal annealing is performed at a temperature of from about 250°C to about 450°C, such as from about 300°C to about 400°C. For example, thermal annealing is performed at a temperature of about 325°C to about 375°C. Further, the processing chamber is pressurized to a pressure of from about 10 bar to about 75 bar, such as from about 20 bar to about 60 bar. For example, the processing chamber is pressurized to a pressure of about 30 bar to about 50 bar. Exposure of the device to high pressure steam anneal removes the exposed portions of the molybdenum layer to form a patterned molybdenum layer without damaging other device structures or material layers.

[0052] Embodiments of the present disclosure include methods for patterning a metal layer of a device to form features in the interconnect layer as part of a process for manufacturing an interconnect structure of the device. Specifically, the disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. The increased selectivity in patterning molybdenum layers can be applied to other metal layers without the disadvantages associated with patterning high hardness materials, including large undercuts and damage to other layers and structures deposited within the semiconductor device. as well as enabling the formation of interconnect structures. Thus, the methods provided herein make molybdenum, as well as other hard metals, more desirable and viable materials for device structures such as interconnect structures.

[0053] Although the foregoing relates to implementations of the present disclosure, other and additional implementations of the disclosure may be devised without departing from the basic scope of the disclosure, the scope of the disclosure being defined by the following claims. it is decided

Claims (15)

A method of forming a metal interconnect layer comprising:
forming a molybdenum layer on the substrate;
forming a masking layer over the molybdenum layer;
patterning the masking layer to expose portions of the molybdenum layer;
modifying the exposed portions of the molybdenum layer with oxygen to form molybdenum oxide portions of the molybdenum layer; and
removing the molybdenum oxide portions from the substrate;
A method of forming a metal interconnect layer. According to claim 1,
exposed portions of the molybdenum layer are modified by oxygen plasma doping,
A method of forming a metal interconnect layer. According to claim 1,
exposed portions of the molybdenum layer are modified by direct oxygen implantation;
A method of forming a metal interconnect layer. According to claim 1,
molybdenum oxide portions of the molybdenum layer are removed by a dry etching process;
A method of forming a metal interconnect layer. According to claim 1,
wherein the molybdenum oxide portions of the molybdenum layer are removed by a wet etching process.
A method of forming a metal interconnect layer. 6. The method of claim 5,
molybdenum oxide portions of the molybdenum layer are wet etched with a pH 10 buffer solution;
A method of forming a metal interconnect layer. 6. The method of claim 5,
molybdenum oxide portions of the molybdenum layer are wet etched with an ammonia solution;
A method of forming a metal interconnect layer. According to claim 1,
annealing the substrate prior to etching away molybdenum oxide portions of the molybdenum layer;
A method of forming a metal interconnect layer. 9. The method of claim 8,
wherein the annealing is performed at a temperature of about 250° C. to about 550° C. and a pressure of about 25 bar to about 55 bar;
A method of forming a metal interconnect layer. A method of forming a metal interconnect layer on a patterned substrate, comprising:
forming a molybdenum layer on the patterned substrate;
forming a masking layer on the molybdenum layer, the masking layer patterned to expose portions of the molybdenum layer; and
exposing the patterned substrate to an accelerated atomic beam to remove exposed regions of the molybdenum layer;
A method of forming a metal interconnect layer on a patterned substrate. 11. The method of claim 10,
wherein the accelerated atomic beam is a gas cluster ion beam formed by ionizing and accelerating gas clusters comprising argon.
A method of forming a metal interconnect layer on a patterned substrate. 12. The method of claim 11,
wherein the gas cluster is accelerated at a voltage potential of about 20 KeV to 30 KeV;
A method of forming a metal interconnect layer on a patterned substrate. 12. The method of claim 11,
wherein the gas cluster ion beam further comprises one or more additional gases selected from the group consisting of oxygen, nitrogen, sulfur hexafluoride, and methane.
A method of forming a metal interconnect layer on a patterned substrate. 11. The method of claim 10,
wherein the accelerated atomic beam is an accelerated neutral atomic beam;
A method of forming a metal interconnect layer on a patterned substrate. A method of patterning a metal interconnect layer on a substrate, comprising:
forming a molybdenum interconnect layer on the substrate;
forming a masking layer on the molybdenum interconnect layer;
patterning the masking layer to expose portions of the molybdenum interconnect layer; and
_{exposing the substrate to gaseous H 2} O at a partial pressure of about 20 bar to about 55 bar and a temperature of about 250° C. to about 550° C. to remove the exposed portions of the molybdenum interconnect layer;
A method of patterning a metal interconnect layer on a substrate.

Images