JP2022509816A - How to pattern a metal layer - Google Patents

Abstract

The present disclosure provides a method for patterning a metal layer of a device (eg, a semiconductor device) to form features in the interconnect layer as part of a process for manufacturing the interconnect structure of the device. The methods of the present disclosure describe a process for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides a method for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.
[Selection diagram] Fig. 1

Description

Embodiments of the present disclosure relate to methods of forming semiconductor device structures. More specifically, embodiments of the present disclosure relate to a method of patterning a metal layer on a substrate.

Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. Evolutions in chip design have resulted in higher circuit densities, improving chip processing power and speed. The demand for faster processing power with higher circuit densities also imposes corresponding demands on the materials used to make such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to scales of less than 10 nm, low resistivity conductive materials, as well as low dielectric constant insulating materials, are used to obtain adequate electrical performance from such components. Has been done.

Interconnects provide electrical connections between the various electronic components of an integrated circuit, and the connections between these elements and the external contact elements (eg, pins) of the device for connecting the integrated circuit to other circuits. To form. Traditionally, copper has been the best material for interconnect layers. However, at scales below 10 nm, conventional copper interconnects show reduced conductivity, making copper an undesired material for advanced nodes. Recently, alternative materials have been sought to overcome the shortcomings of copper as an interconnect material. One such material is molybdenum. Molybdenum interconnects exhibit desirable electrical properties even on a scale of less than 10 nm. However, since molybdenum is a high-hardness metal, the molybdenum interconnect layer is still difficult to pattern during the manufacture of semiconductor devices.

Therefore, an improved method for patterning a molybdenum layer is needed in the art.

In one embodiment, a method of patterning a molybdenum interconnect layer is provided. The method comprises forming a molybdenum layer on the substrate. Next, a masking layer is formed on top of the molybdenum layer and patterned to expose the area of the molybdenum layer to the periphery. The exposed area of molybdenum is modified with oxygen to form the molybdenum oxide moiety of the molybdenum interconnect layer. After modification, the molybdenum oxide portion of the molybdenum interconnection layer is removed from the substrate by an etching process.

In one embodiment, a method of forming a metal interconnect layer on a patterned substrate is provided. The method comprises forming a molybdenum layer on a patterned substrate. A masking layer is formed on the molybdenum layer, and the masking layer is patterned so as to expose undesired areas of the molybdenum layer to the periphery. The patterned substrate is then exposed to a neutral beam to remove unwanted regions of the molybdenum layer.

In one embodiment, a method of patterning a metal interconnect layer on a substrate is provided. The method comprises forming a molybdenum interconnect layer on the substrate. A mask is formed on the molybdenum layer and patterned to expose the area of the molybdenum interconnect layer. The substrate is then placed in the substrate processing area of the substrate processing chamber and exposed to gas phase _H2O at a partial pressure in the range of about 20 bar to about 55 bar and a temperature in the range of about 250 ° C to about 550 ° C. And later remove the exposed area of the molybdenum interconnect.

To help you understand the above features of the present disclosure in detail, a more detailed description of the present disclosure briefly summarized above is provided by reference to embodiments, some of which are shown in the accompanying drawings. Obtainable. However, it should be noted that the accompanying drawings show only exemplary embodiments and therefore should not be considered limiting their scope and other equally valid embodiments may be acceptable.

A flow diagram of a method for patterning a molybdenum interconnection layer of a device such as a semiconductor device according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer prior to removal of a portion of one or more layers on the substrate according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after a portion of one or more layers on a substrate has been modified according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after a portion of one or more layers on a substrate has been modified according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after a portion of one or more layers on a substrate has been removed according to an embodiment of the present disclosure. A flow diagram of a method for patterning a molybdenum interconnection layer of a device such as a semiconductor device according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer prior to removal of a portion of one or more layers on the substrate according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after a portion of one or more layers on a substrate has been removed according to an embodiment of the present disclosure. Schematic cross-sectional view of a portion of a semiconductor device comprising a molybdenum layer after removal of additional portions of one or more layers on the substrate according to an embodiment of the present disclosure. A flow diagram of a method for patterning a molybdenum interconnection layer of a device such as a semiconductor device according to an embodiment of the present disclosure.

For ease of understanding, where possible, the same reference numbers are used to indicate the same elements that are common to the drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further description.

The present disclosure provides a method for patterning a metal layer of a device (eg, a semiconductor device) to form features in the interconnect layer as part of a process for manufacturing the interconnect structure of the device. The methods of the present disclosure describe a process for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides a method for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.

FIG. 1 is a flow chart of a method 100 for patterning a molybdenum layer of a device such as a semiconductor device according to one embodiment. In some embodiments, the molybdenum layer can be placed directly on the substrate surface. In some embodiments, the molybdenum layer can be placed on another metal layer, such as a barrier metal layer. In another embodiment, the molybdenum layer can be placed on a dielectric layer such as a silicon dioxide layer. Molybdenum layer patterning can be used to make interconnected structures for devices. The patterning method 100 can be performed in a processing chamber such as a plasma processing chamber or other suitable processing chamber. Hereinafter, the method 100 of FIG. 1 will be described together with the figures shown in FIGS. 2A to 2C showing devices containing a molybdenum layer at various stages of the method 100. Further, Method 100 is described below with respect to the molybdenum layer utilized to form the interconnect structure, which method 100, along with other metal-containing layers, is also advantageous in other semiconductor device manufacturing applications. It can also be used.

In operation 102, the semiconductor device 200 (see FIG. 2A) containing the molybdenum layer 202 is positioned in a plasma processing chamber (not shown), such as an etching processing chamber. The semiconductor device 200 can include one or more semiconductor devices that are in the manufacturing process or at various stages of manufacturing. FIG. 2A is a schematic cross-sectional view of a portion of the semiconductor device 200 comprising the molybdenum layer 202 before the portion of the one or more layers disposed on the substrate 201 is removed according to one embodiment. The figure of FIG. 2A shows a semiconductor device 200 before an initial patterning process (eg, an oxidation process) is performed to modify a portion of the molybdenum layer 202.

The semiconductor device 200 includes a substrate 201. The substrate 201 is, among other things, silicon, crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, silicon on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped. It can be formed from suitable materials such as silicon, germanium, gallium arsenide, glass, or sapphire. In some embodiments, the substrate 201 is a circular substrate of 200 mm, 300 mm, 450 mm, or other diameter. In another embodiment, the substrate 201 is a rectangular substrate or a square substrate. In embodiments where SOI is used for substrate 201, the substrate 201 may further include an embedded dielectric layer disposed on a silicon crystal substrate.

The molybdenum layer 202 is arranged on the substrate 201. In one embodiment, the molybdenum layer 202 is arranged directly on the substrate 201 and in contact with the substrate 201. In another embodiment, the molybdenum layer 202 can be placed on an intermediate layer (not shown) such as a dielectric layer. In these embodiments, the intermediate layer is arranged directly on the substrate 201 and in contact with the substrate 201, and the molybdenum layer 202 is arranged on the intermediate layer. The molybdenum layer 202 is used as an interconnect layer for connecting a plurality of elements or devices of an integrated circuit.

The semiconductor device 200 further includes a masking layer 203 during one or more stages of manufacture. The masking layer 203 can be formed directly on the molybdenum layer 202 or on an intermediate layer (not shown) such as a dielectric layer. In some embodiments, the masking layer is formed of a material that does not react with the wet etching solution. In some embodiments, the masking layer is made of a low hardness material. In another embodiment, the masking layer 203 is a hard mask such as a carbon hard mask. As an alternative to the carbon hard mask, or in addition to the carbon hard mask, the masking layer 203 can be formed of other high hardness materials. Examples of high hardness materials include Tungsten Carbide (WC), tungsten boron carbide (WBC), Tungsten Nitride (WN), Silicon Boron (SiB _x ), Boron Carbide (BC), Amorphous Carbon, Includes, but is not limited to, boron nitride (BN), boron carbide (BCN), or other similar materials. The material of the masking layer 203 described above may include a compound (eg, an equal amount compound of tungsten and carbon, a stoichiometric compound, etc.) or a doped material (eg, a tungsten layer containing a small amount of carbon). .. In some embodiments that can be combined with other embodiments described herein, the masking layer 203 is made of a photosensitive material such as naphthoquinone diazide (NQD) or other suitable photoreactive material. It is a photoresist. In other embodiments,

In some embodiments, the substrate 201 is a thermally oxidized substrate. In embodiments that include a thermally oxidized substrate, the molybdenum layer 202 can be formed directly on the substrate 201. The thermally oxidized substrate contains oxygen on the surface in contact with the molybdenum layer 202. When a portion of the molybdenum layer 202 is removed to expose the thermally oxidized substrate as described below, oxygen from the thermally oxidized substrate is used to provide a passivation layer on the exposed surface of the semiconductor device 200. (Not shown) is formed. The passivation layer either stops or substantially reduces further etching as the etching process breaks through the molybdenum layer 202. For example, oxygen from the thermally oxidized substrate combines with silicon atoms from the silicon-containing gas used to etch the molybdenum layer 202 to form a silicon oxide passivation layer on the exposed portion of the semiconductor device 200. It can be formed and the etching process can be stopped. The passivation layer is described herein in part by oxygen from a thermally oxidized substrate, but the oxygen is in the oxygen-containing layer directly beneath the molybdenum layer 202. It may be derived.

In some embodiments, the semiconductor device 200 may further include a barrier layer (not shown) and a low dielectric constant insulating dielectric layer (not shown). The low dielectric constant insulating dielectric layer is arranged on the substrate 201 between the molybdenum layer 202 and the substrate 201. The barrier layer can be placed on top of the low dielectric constant insulating dielectric layer between the molybdenum layer 202 and the low dielectric constant insulating dielectric layer. The barrier layer includes tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AIN), tantalum nitride silicon (TaSiN), silicon nitride (TiSiN), silicon nitride (SiN), silicon oxynitride (SiON), and carbonic acid. It can be made from silicon (SiC), (silicon isocyanide) SiNC, silicon oxycarbide (SiOC), or other suitable material. Further, the low dielectric constant insulating dielectric layer can be formed from a SiO-containing material, a SiN-containing material, a SiOC-containing material, a SiC-containing material, a carbon-based material, or another suitable material.

In operation 104, part of the masking layer 203 is removed to form the exposed portion 222 of the molybdenum layer 202, as shown in FIG. 2B. FIG. 2B is a schematic cross-sectional view of a part of the semiconductor device 200 after the part of the masking layer 203 arranged on the molybdenum layer 202 is removed according to the embodiment. Removal of these portions of the masking layer 203 forms a void 205 in the masking layer 203, shown as a trench in FIG. 2B, the bottom of the void 205 formed by the exposed portion 222 of the molybdenum layer 202 (ie, the boundary, Or it is partially defined). Therefore, by removing a part of the masking layer 203, a part of the molybdenum layer 202 is exposed.

By using the above materials (ie, high hardness materials such as WC) for the masking layer 203, the process of selectively etching the features on the molybdenum layer 202 can be improved, but ultimately, Part or all of the masking layer 203 is removed to form features on the device, such as transistor structures.

In operation 106, the exposed portion 222 of the molybdenum layer 202 is modified. In one embodiment, the exposed portion 222 is oxidized to form the molybdenum oxide portion 223. FIG. 2C is a schematic cross-sectional view of a portion of the semiconductor device 200 comprising the molybdenum layer 202 after the exposed portion 222 of the molybdenum layer 202 has been oxidized according to one embodiment.

The exposed portion 222 can be oxidized by a variety of methods including, but not limited to, direct oxygen ion implantation or oxygen plasma doping. For example, the injected oxygen ions are impacted by a path substantially perpendicular to the exposed portion 222 of the molybdenum layer 202 and can penetrate the exposed portion 222. The injected ions can penetrate the exposed portion 222 at various depths, depending on the power and bias used to energize the oxygen ions. For example, the exposed portion 222 may have an acceleration voltage of about 5 KeV to about 30 KeV, such as about 10 KeV to about 20 KeV, from about 0.5E16 ions / cm2 to about 5E17 ions / cm2, such as about 1E16 ions / cm2 to about 1E17. It can be infused with energized oxygen ions at doses in the range of ions / cm2. For example, the exposed portion 222 can be injected with oxygen ions energized at doses of 10 KeV and 1E17 ions / cm2.

Ion implantation can be performed by a beamline or plasma implantation tool. Suitable commercially available processing platforms that can be advantageously used in accordance with the embodiments described herein are Applied Materials, Inc., located in Santa Clara, Calif., USA. VIISTA® PLAD ™ platform available from the company. It is envisioned that other well-configured injection technology platforms by other manufacturers can also be used in accordance with embodiments herein.

In some embodiments, after oxygen ion implantation of the exposed moiety 222, the semiconductor device 200 is annealed to form the polycrystalline structure of the molybdenum oxide moiety 223. The semiconductor device 200 is annealed by various methods such as furnace annealing or rapid thermal annealing, for example lamp annealing or laser annealing. In one embodiment, the device structure 200 has a temperature between about 200 ° C. and about 600 ° C., a water vapor pressure between about 0.5 bar and about 75 bar, and a duration between about 15 minutes and about 2 hours. Annealed. In some examples, the device structure 200 is annealed at a temperature between about 250 ° C and about 550 ° C, such as between about 300 ° C and about 500 ° C, for example between about 350 ° C and about 450 ° C. In some examples, the device structure 200 is annealed at a pressure between about 25 bar and about 55 bar, such as between about 30 bar and about 50 bar, for example between about 35 bar and about 45 bar. In some examples, the device structure 200 is annealed for a duration of about 30 minutes to about 1.5 hours, eg, 45 minutes to 75 minutes. In one example, the device structure 200 is annealed at 325 ° C. and 55 bar for about 60 minutes.

In some embodiments, thermal annealing is performed at high pressure and in the presence of a processing gas such as hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gas for high pressure gas annealing. Annealing the semiconductor device 200 at a high pressure level facilitates the formation of the polycrystalline structure of the molybdenum oxide moiety 223 even at a low temperature of, for example, less than 350 ° C.

In operation 108, the molybdenum oxide moiety 223 is removed from the semiconductor device 200 to form the patterned molybdenum layer 204. FIG. 2D is a schematic cross-sectional view of a portion of the substrate 201 containing the patterned molybdenum layer 204 after the molybdenum oxide moiety 223 has been removed. By removing the molybdenum oxide portion 223, a void 205 shown as a trench in FIG. 2D is formed on the patterned molybdenum layer 204, and the bottom portion of the void 205 is formed by the upper surface 207 of the substrate 201.

The molybdenum oxide moiety 223 can be removed from the substrate 201 by any suitable etching process selective for molybdenum oxide, including wet or dry etching processes. For example, the molybdenum oxide moiety 223 is removed from the substrate 201 by wet etching with an ammonia solution. The ammonia solution is selective for the oxidized moiety 223. Therefore, the oxidized portion 223 is removed, while the unoxidized patterned molybdenum layer 204 is not removed by the ammonia solution. Ammonia solution may contain ammonium hydroxide at a concentration of about 26% w / w to about 30% w / w, for example about 28% w / w. The semiconductor device 200 may be exposed to an ammonia solution for a duration of, for example, between about 2 minutes and about 10 minutes in order to etch the desired depth of the molybdenum oxide moiety 223.

In another example that can be combined with the examples and embodiments described herein, the molybdenum oxide moiety 223 is removed from the semiconductor device 200 by wet etching with a pH 10 buffer. The pH 10 buffer contains a sodium compound such as sodium tetraborate or sodium hydroxide. The semiconductor device 200 may be exposed to pH 10 buffer for a duration of, for example, between about 2 minutes and about 10 minutes in order to etch the desired depth of the molybdenum oxide moiety 223. The use of either an ammonia solution or a pH 10 buffer to selectively etch the molybdenum oxide moiety 223 impairs the unoxidized patterned molybdenum layer 204 or other material layer and device structure of the semiconductor device 200. Instead, the molybdenum oxide portion 223 is etched.

FIG. 3 is a flow chart of a method 300 for patterning a molybdenum layer of a device such as a semiconductor device by neutral atom beam etching according to one embodiment. Similar to the embodiments shown in FIGS. 1 and 2, the molybdenum layer 202 can be placed directly on the substrate 201 or on another layer such as a metal layer or a dielectric layer. The patterning of the molybdenum layer 202 according to the present embodiment can be used to manufacture the interconnection structure of the semiconductor device 200. The patterning method 300 is performed in a processing chamber such as a plasma processing chamber or in a neutral atom beam etching apparatus. The following describes the method 300 of FIG. 3 together with the diagrams shown in FIGS. 4A-4C showing the semiconductor device 200 of FIG. 2 comprising the molybdenum layer 202 at various stages of the method 300. Further, the method 300 is described below with respect to the molybdenum layer 202 used to form the interconnect structure, which method 300, along with materials other than molybdenum, is also advantageous in other semiconductor device manufacturing applications. Can be used.

In operation 302, the semiconductor device 200 (see FIG. 4A) containing the molybdenum layer 202 is positioned within a plasma processing chamber (not shown), such as an etching processing chamber. The semiconductor device 200 can include one or more semiconductor devices that are in the manufacturing process or at various stages of manufacturing. FIG. 4A is a schematic cross-sectional view of a portion of the semiconductor device 200 comprising the molybdenum layer 202 before the portion of the one or more layers disposed on the substrate 201 is removed according to one embodiment. The figure of FIG. 4A shows the semiconductor device 200 before the patterning process (eg, neutral beam etching) is performed to modify a part of the molybdenum layer 202.

In operation 304, part of the masking layer 203 is removed to form the exposed portion 222 of the molybdenum layer 202, as shown in FIG. 4B. FIG. 4B is a schematic cross-sectional view of a part of the semiconductor device 200 after the part of the masking layer 203 arranged on the molybdenum layer 202 is removed according to the embodiment. Removal of these portions of the masking layer 203 forms voids 205 in the masking layer 203, shown as trenches in FIG. 4B, the bottom of the voids 205 formed by exposed portions 222 of the molybdenum layer 202 (ie, boundaries). , Or partially defined). Therefore, by removing a part of the masking layer 203, a part of the molybdenum layer 202 is exposed.

In operation 306, the exposed portion of the molybdenum layer 202 is removed from the semiconductor device 200 to form the patterned molybdenum layer 204. FIG. 4C is a schematic cross-sectional view of a portion of the semiconductor device 200 comprising the patterned molybdenum layer 204 after the exposed portion 222 of the molybdenum layer 202 has been removed. Removal of the exposed portion 222 forms a void 205, shown as a trench in FIG. 4C, on the patterned molybdenum layer 204, the bottom of which is formed by the top surface of the substrate 201.

In the embodiments shown by FIGS. 3 and 4, the exposed portion 222 of the molybdenum layer 202 can be removed from the semiconductor device 200 by an accelerated atomic beam process. Suitable commercial processing platforms that can be advantageously used in accordance with the embodiments described herein are Exogenesis Corp., located in Billerica, Massachusetts, USA. NanoAccel ™ platform available from the company. It is envisioned that other well-configured accelerated atomic beam platforms by other manufacturers can also be used in accordance with embodiments herein.

In one example, the exposed portion 222 of the molybdenum layer 202 can be removed by gas cluster ion beam (GCIB) etching. During the GCIB etching of the molybdenum layer 202, the pressurized inert gas flows towards the exposed portion 222 of the molybdenum layer 202 in the processing chamber, expands and accelerates, and the exposed portion 222. Energy can be transferred to the outermost atom of the molybdenum to remove the atom. In one embodiment, the gas cluster ion beam is formed from argon gas. In other embodiments, additional gases, including oxygen (O ₂ ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ), are combined with an inert gas to form gas cluster ions. A beam can be formed.

The gas cluster ion beam can be guided through the void 205 of the masking layer 203 into a substantially vertical path so as to penetrate the desired portion of the molybdenum layer 202 to form the patterned molybdenum layer 204. Therefore, other device structures or material layers on the semiconductor device 200 are left undamaged during gas cluster ion beam etching. The gas cluster ion beam can be accelerated from 10 KeV to 40 KeV, for example from 15 KeV to 35 KeV. For example, a gas cluster ion beam can be accelerated to an acceleration voltage of 25 KeV. The semiconductor device 200 can be exposed to a gas cluster ion beam for any suitable dose time, for example between about 0 and about 30 seconds, including between 2 and 20 seconds. For example, the semiconductor device 200 may be exposed to a gas cluster ion beam for a dose time of 6, 8, 10, 14, or 18 seconds.

In another example that can be combined with the embodiments and examples described herein, accelerated neutral atomic beam (ANAB) etching is used to remove the exposed portion 222 of the molybdenum layer 202 from the semiconductor device 200. do. Similar to GCIB etching, accelerated neutral atom beam etching utilizes a beam of accelerated gas cluster ions, but the gas clusters are dissociated and the charge is removed before colliding with the surface of the exposed portion 222. .. The accelerated neutral atom beam can be guided in a substantially vertical path through the void 205 of the masking layer 203 so as to penetrate the desired portion of the molybdenum layer 202. Furthermore, each atom in the neutral atom beam has a relatively low energy, resulting in limited surface modification of only a few atomic layers and thus etching damage to other materials and layers or semiconductor devices 200. Is significantly reduced or eliminated.

The accelerated neutral atom beam is accelerated from 10 KeV to 40 KeV, for example from 15 KeV to 35 KeV. For example, the accelerated neutral atom beam is accelerated to an acceleration voltage of 25 KeV. The semiconductor device 200 is exposed to an accelerated neutral atomic beam for any suitable dose time, for example between about 0 and about 30 seconds, including between 2 and 20 seconds. For example, the semiconductor device 200 may be exposed to an accelerated neutral atomic beam for a dose time of 6, 8, 10, 14, or 18 seconds. An inert gas such as argon can be used to form an accelerated neutral atom beam. In some embodiments, additional gases, including (O ₂ ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ), can be combined with the inert gas. ANAB etching can be performed under any suitable etching conditions.

FIG. 5 is a flow chart of a method 500 for patterning a molybdenum layer of a device such as a semiconductor device by high-pressure water annealing according to one embodiment. Similar to the embodiments shown in FIGS. 1 to 4, the molybdenum layer can be arranged directly on the surface of the substrate or on another layer such as a metal layer or a dielectric layer. The patterning of molybdenum layers according to this embodiment, which can be combined with other embodiments and examples described herein, can be used to make interconnected structures for devices. The patterning method 500 is performed in a plasma processing chamber such as an etching processing chamber or in other suitable processing equipment. Method 500 is described below with respect to the molybdenum layer utilized to form the interconnect structure, which method 500 may also be advantageously used in other semiconductor device manufacturing applications with materials other than molybdenum. can.

In operation 302, the semiconductor device containing the molybdenum layer is positioned in a plasma processing chamber (not shown), such as an etching processing chamber. The semiconductor device can include one or more semiconductor devices in the manufacturing process. The semiconductor device further includes, for example, a substrate, a molybdenum layer arranged on the substrate, and a masking layer, similar to the substrate 201, the molybdenum layer 202, and the masking layer 203 described with respect to FIGS. 2 and 4. The semiconductor device can also include other material layers disposed on the substrate, such as a barrier layer or a low dielectric constant insulating layer.

In operation 504, part of the masking layer is removed to form an exposed portion of the molybdenum layer. Removal of these portions of the masking layer forms voids 205 in the masking layer, the bottom of the void 205 being formed by exposed portions of the molybdenum layer. Removal of part of the masking layer exposes part of the molybdenum layer.

In operation 506, the semiconductor device is exposed to a high pressure water annealing (HPWA) process and the exposed portion of the molybdenum layer is removed from the semiconductor device. Method 500 describes high pressure water annealing that uses steam to anneal a semiconductor device, but it is envisioned that other gases can be used to anneal the semiconductor device under high pressure. For example, semiconductor devices can be annealed at high pressure using hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gas. In another example, the semiconductor device can be annealed using a combination of gases including hydrogen, deuterium, fluorine, chlorine, ammonium, and other suitable gases.

In operation 506, the processing chamber is pressurized by supplying water vapor from the pressure chamber to the processing chamber, followed by thermal annealing of the device and depressurization of the processing chamber by discharging the water vapor. Thermal annealing is performed at a temperature between about 250 ° C and about 450 ° C, for example between about 300 ° C and about 400 ° C. For example, thermal annealing is performed at a temperature between about 325 ° C and about 375 ° C. Further, the processing chamber is pressurized to a pressure between about 10 bar and about 75 bar, for example between about 20 bar and about 60 bar. For example, the processing chamber is pressurized to a pressure between about 30 bar and about 50 bar. Exposure of the device to high pressure steam annealing removes the exposed portion of the molybdenum layer, thus forming a patterned molybdenum layer without damaging other device structures or material layers.

Embodiments of the present disclosure include a method of patterning a metal layer of a device to form features in the interconnect layer as part of a process for manufacturing the interconnect structure of the device. In particular, the methods of the present disclosure describe a process for patterning a molybdenum layer with improved selectivity. Due to the increased selectivity in patterning of molybdenum layers, interconnect structures and interconnect structures and without the drawbacks associated with patterning high hardness materials, including large undercuts and damage to other layers and structures laminated within semiconductor devices. It allows the formation of other metal layers. Therefore, the methods provided herein make molybdenum and other high hardness metals more desirable and practical materials for device structures such as interconnect structures.

Although the above is intended for embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, the scope of which is as follows: Determined by the scope of claims.

Claims (15)

A method of forming a metal interconnect layer,
Forming a molybdenum layer on the substrate;
Forming a masking layer on the molybdenum layer;
Patterning the masking layer to expose part of the molybdenum layer;
A method comprising modifying an exposed portion of the molybdenum layer with oxygen to form a molybdenum oxide moiety of the molybdenum layer; and removing the molybdenum oxide moiety from the substrate. The method of claim 1, wherein the exposed portion of the molybdenum layer is modified by oxygen plasma doping. The method of claim 1, wherein the exposed portion of the molybdenum layer is modified by direct oxygen injection. The method according to claim 1, wherein the molybdenum oxide portion of the molybdenum layer is removed by a dry etching process. The method according to claim 1, wherein the molybdenum oxide portion of the molybdenum layer is removed by a wet etching treatment. The method according to claim 5, wherein the molybdenum oxide portion of the molybdenum layer is wet-etched with a buffer solution having a pH of 10. The method according to claim 5, wherein the molybdenum oxide portion of the molybdenum layer is wet-etched with an ammonia solution. The method of claim 1, further comprising annealing the substrate before removing the molybdenum oxide portion of the molybdenum layer by etching. 8. The method of claim 8, wherein the annealing is performed at a temperature between about 250 ° C. and about 550 ° C. and a pressure between about 25 bar and about 55 bar. A method of forming a metal interconnect layer on a patterned substrate.
Forming a molybdenum layer on the patterned substrate;
By forming a masking layer on the molybdenum layer, the masking layer is patterned to expose a part of the molybdenum layer to form a masking layer; and the patterned substrate is used as an accelerating atomic beam. A method comprising exposing to remove an exposed area of the molybdenum layer. 10. The method of claim 10, wherein the accelerated atomic beam is a gas cluster ion beam formed by ionizing and accelerating a gas cluster containing argon. 11. The method of claim 11, wherein the gas cluster is accelerated at a potential of about 20 KeV to 30 KeV. 11. The method of claim 11, wherein the gas cluster ion beam further comprises one or more additional gases selected from the group consisting of oxygen, nitrogen, sulfur hexafluoride, and methane. 10. The method of claim 10, wherein the accelerated atomic beam is an accelerated neutral atomic beam. A method of patterning a metal interconnect layer on a substrate.
Forming a molybdenum interconnect layer on the substrate;
Forming a masking layer on the molybdenum interconnect layer;
Patterning the masking layer to expose a portion of the molybdenum interconnect layer; and airing the substrate at a partial pressure between about 20 bar and about 55 bar and a temperature between about 250 ° C and about 550 ° C. A method comprising exposing the exposed portion of the molybdenum interconnect layer to phase _H2O .

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