KR102779927B1 - Methods for patterning metal layers - Google Patents

Abstract

The present disclosure provides methods for patterning a metal layer of a device (e.g., a semiconductor device) to form features in the interconnection layer as part of a process for fabricating an interconnection structure of the device. The disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides methods for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.

Description

Methods for patterning metal layers

[0001] Embodiments of the present disclosure relate to methods for forming semiconductor device structures. More specifically, embodiments of the present disclosure relate to methods for patterning metal layers on a substrate.

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. The evolution of chip design has led to greater circuit densities, which have improved the processing capabilities and speeds of the chips. The demands for faster processing capabilities due to greater circuit densities have placed corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components have shrunk to scales below 10 nm, low-k insulating materials as well as low-resistivity conductive materials are used to obtain adequate electrical performance from such components.

[0003] Interconnects provide electrical connections between the various electronic components of an integrated circuit and form connections between these components and external contact elements (e.g., pins) of the device for connecting the integrated circuit to other circuits. Traditionally, copper has been the material of choice for interconnect layers. However, at scales below 10 nm, conventional copper interconnects exhibit reduced conductivity, making copper an undesirable material for advanced nodes. Recently, alternative materials have been sought to overcome the deficiencies of copper as an interconnect material. One such material is molybdenum. Molybdenum interconnects exhibit desirable electrical properties even at scales below 10 nm. However, because molybdenum is a hard metal, molybdenum interconnect layers remain difficult to pattern during semiconductor device fabrication.

[0004] Therefore, there is a need in the art for improved methods for patterning molybdenum layers.

[0005] In one embodiment, a method of patterning a molybdenum interconnect layer is provided. The method comprises forming a molybdenum layer on a substrate. A masking layer is then formed over the molybdenum layer and patterned to expose regions of the molybdenum layer to the surroundings. The exposed regions of the molybdenum are modified with oxygen to form molybdenum oxide portions of the molybdenum interconnect layer. After the modification, the molybdenum oxide portions of the molybdenum interconnect layer are removed from the substrate through an etching process.

[0006] In one embodiment, a method of forming a metal interconnect layer on a patterned substrate is provided. The method comprises forming a molybdenum layer on the patterned substrate. A masking layer is formed on the molybdenum layer, and the masking layer is patterned to expose unwanted regions of the molybdenum layer to its surroundings. The patterned substrate is then exposed to a neutral particle beam to remove the unwanted regions of the molybdenum layer.

[0007] In one embodiment, a method of patterning a metal interconnect layer on a substrate is provided. The method comprises forming a molybdenum interconnect layer on the substrate. A mask is formed over the molybdenum layer and patterned to expose regions of the molybdenum interconnect layer. The substrate is then placed into a substrate processing region of a substrate processing chamber and exposed to gaseous H ₂ O at a partial pressure in the range of about 20 bar to about 55 bar and a temperature in the range of about 250° C. to about 550° C. to remove the exposed regions of the molybdenum interconnect layer.

[0008] So that the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. It should be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting the scope of the present disclosure, for the disclosure may admit to other equally effective embodiments.
[0009] FIG. 1 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
[0010] FIG. 2A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on a substrate are removed, according to one embodiment of the present disclosure.
[0011] FIG. 2b illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on a substrate have been modified, according to one embodiment of the present disclosure.
[0012] FIG. 2c illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on a substrate have been modified, according to one embodiment of the present disclosure.
[0013] FIG. 2d illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on a substrate have been removed, according to one embodiment of the present disclosure.
[0014] FIG. 3 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
[0015] FIG. 4A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on a substrate are removed, according to one embodiment of the present disclosure.
[0016] FIG. 4b illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on a substrate have been removed, according to one embodiment of the present disclosure.
[0017] FIG. 4c illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after additional portions of one or more layers on a substrate are removed, according to one embodiment of the present disclosure.
[0018] FIG. 5 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0020] The present disclosure provides methods for patterning a metal layer of a device (e.g., a semiconductor device) to form features in the interconnect layer as part of a process for fabricating an interconnect structure of the device. The disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. For example, the present disclosure provides methods for modifying and removing regions of a molybdenum layer by annealing or etching without damaging other device structures or materials.

[0021] FIG. 1 is a flow diagram of a method (100) for patterning a molybdenum layer of a device, such as a semiconductor device, according to one embodiment. In some embodiments, the molybdenum layer may be disposed directly on a substrate surface. In some embodiments, the molybdenum layer may be disposed on another metal layer, such as a barrier metal layer. In other embodiments, the molybdenum layer may be disposed on a dielectric layer, such as a silicon dioxide layer. Patterning the molybdenum layer may be used to fabricate interconnect structures of the device. The patterning method (100) may be performed in a process chamber, such as a plasma process chamber or other suitable process chamber. The method (100) of FIG. 1 is described below in conjunction with the drawings shown in FIGS. 2A-2C which illustrate devices including a molybdenum layer at different stages of the method (100). Additionally, although the method (100) is described below with reference to a molybdenum layer utilized to form an interconnect structure, the method (100) may also be advantageously used with other metal-containing layers and in other semiconductor device manufacturing applications.

[0022] In operation (102), a semiconductor device (200) including a molybdenum layer (202) (see FIG. 2A) is positioned in a plasma process chamber, such as an etching process chamber (not shown). The semiconductor device (200) may include one or more semiconductor devices that are in a manufacturing process or are in various stages of fabrication. FIG. 2A is a schematic cross-sectional view of a portion of a semiconductor device (200) including a molybdenum layer (202) before portions of one or more layers disposed on a substrate (201) are removed, according to one embodiment. The drawing of FIG. 2A illustrates the semiconductor device (200) before an initial patterning process (e.g., an oxidation process) is performed to modify portions of the molybdenum layer (202).

[0023] The semiconductor device (200) includes a substrate (201). The substrate (201) may be formed of any suitable material, such as silicon, crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire, among other materials. In some embodiments, the substrate (201) is a circular substrate having a diameter of 200 mm, 300 mm, 450 mm, or other similar dimensions. In other embodiments, the substrate (201) is a rectangular substrate or a square substrate. In embodiments where SOI is used for the substrate (201), the substrate (201) may further include a buried dielectric layer disposed on the crystalline silicon substrate.

[0024] The molybdenum layer (202) is disposed on the substrate (201). In one embodiment, the molybdenum layer (202) is disposed directly over and in contact with the substrate (201). In other embodiments, the molybdenum layer (202) may be disposed on an intermediate layer (not shown), such as a dielectric layer. In such embodiments, the intermediate layer is disposed directly over and in contact with the substrate (201), and the molybdenum layer (202) is disposed on the intermediate layer. The molybdenum layer (202) is used as an interconnect layer for connecting multiple elements or devices of an integrated circuit.

[0025] The semiconductor device (200) further includes a masking layer (203) during one or more of the fabrication stages. The masking layer (203) may be formed directly over the molybdenum layer (202), or over an intermediate layer (not shown), such as a dielectric layer. In some embodiments, the masking layer is formed of a material that is non-reactive to wet etching solutions. In some embodiments, the masking layer is formed of a low-hardness material. In other embodiments, the masking layer (203) is a hard mask, such as a carbon hard mask. In addition to or alternatively to a carbon hard mask, the masking layer (203) may be formed of other high-hardness materials. Examples of high hardness materials include (but are not limited to) tungsten carbide (WC), tungsten boron carbide (WBC), tungsten nitride (WN), silicon boride (SiB _x ), boron carbide (BC), amorphous carbon, boron nitride (BN), boron carbon nitride (BCN), or other similar materials. The masking layer (203) materials described above may include compounds (e.g., chemical compounds of equal parts tungsten and carbon, stoichiometric compounds, etc.) or doped materials (e.g., a tungsten layer containing a small percentage of carbon). In some embodiments that may be combined with other embodiments described herein, the masking layer (203) is a photoresist formed of photosensitive materials, such as naphthoquinone diazide (NQD) or other suitable photoreactive materials.

[0026] In some embodiments, the substrate (201) is a thermally oxidized substrate. In embodiments including a thermally oxidized substrate, a molybdenum layer (202) may be formed directly over the substrate (201). The thermally oxidized substrate includes oxygen at a surface that contacts the molybdenum layer (202). As described below, when portions of the molybdenum layer (202) are removed to expose the thermally oxidized substrate, the oxygen from the thermally oxidized substrate is used to form a passivation layer (not shown) on the exposed surfaces of the semiconductor device (200). The passivation layer stops or substantially reduces further etching when the etching process penetrates the molybdenum layer (202). For example, oxygen from the thermally oxidized substrate may combine with silicon atoms from the silicon-containing gas used to etch the molybdenum layer (202) to form a passivation layer of silicon oxide over the exposed portions of the semiconductor device (200) to stop the etching process. Although the passivation layer is described herein as being formed in part by oxygen from the thermally oxidized substrate, the oxygen may come from a layer comprising oxygen directly beneath the molybdenum layer (202).

[0027] In some embodiments, the semiconductor device (200) may further include a barrier layer (not shown) and a low-k insulating dielectric layer (not shown). The low-k insulating dielectric layer is disposed over the substrate (201) and between the molybdenum layer (202) and the substrate (201). The barrier layer may be disposed over the low-k insulating dielectric layer and between the molybdenum layer (202) and the low-k insulating dielectric layer. The barrier layer may be fabricated from tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), (silicon isocyanide) SiNC, silicon oxycarbide (SiOC), or other suitable materials. Additionally, the low-k insulating dielectric layer can be formed of SiO containing materials, SiN containing materials, SiOC containing materials, SiC containing materials, carbon-based materials, or other suitable materials.

[0028] In operation (104), portions of the masking layer (203) are removed to form exposed portions (222) of the molybdenum layer (202), as illustrated in FIG. 2B. FIG. 2B is a schematic cross-sectional view of a portion of a semiconductor device (200) including the molybdenum layer (202) after portions of the masking layer (203) disposed on the molybdenum layer (202) are removed, according to one embodiment. Removal of these portions of the masking layer (203) forms voids (205), illustrated as trenches in FIG. 2B, in the masking layer (203), with lowermost portions of the voids (205) being formed (i.e., bounded or partially defined) by the exposed portions (222) of the molybdenum layer (202). Therefore, removal of portions of the masking layer (203) exposes portions of the molybdenum layer (202).

[0029] The use of materials described above for the masking layer (203) (i.e., high hardness materials, such as WC) may improve the process of selectively etching features over the molybdenum layer (202), but may ultimately result in portions or all of the masking layer (203) being removed to form features, such as transistor structures, on the device.

[0030] In operation (106), exposed portions (222) of the molybdenum layer (202) are modified. In one embodiment, the exposed portions (222) are oxidized to form molybdenum oxide portions (223). FIG. 2C is a schematic cross-sectional view of a portion of a semiconductor device (200) including a molybdenum layer (202) after the exposed portions (222) of the molybdenum layer (202) are oxidized, according to one embodiment.

[0031] The exposed portions (222) may be oxidized by a variety of methods, including but not limited to direct oxygen ion implantation or oxygen plasma doping. For example, the implanted oxygen ions may be bombarded in a substantially vertical path to the exposed portions (222) of the molybdenum layer (202) so as to penetrate the exposed portions (222). The implanted ions may penetrate the exposed portions (222) to various depths depending on the power and bias utilized to energize the oxygen ions. For example, the exposed portions (222) can be implanted with oxygen ions energized at an acceleration voltage of about 5 KeV to about 30 KeV, such as about 10 KeV to about 20 KeV, and a dose in a range of about 0.5E16 ion/cm ² to about 5E17 ion/cm ² , such as about 1E16 ion/cm ² to about 1E17 ion/cm ² . For example, the exposed portions (222) can be implanted with oxygen ions energized at 10 KeV and dosed at 1E17 ion/cm ² .

[0032] Ion implantation can be performed by beamline or plasma implantation tools. A suitable commercially available processing platform that may be advantageously utilized in accordance with the embodiments described herein is the VIISTA® PLAD™ platform available from Applied Materials, Inc. of Santa Clara ^, California. It is contemplated that other suitably configured implantation technology platforms from other manufacturers may also be utilized in accordance with the embodiments herein.

[0033] In some embodiments, after the oxygen ion implantation of the exposed portions (222), the semiconductor device (200) is annealed to form a polycrystalline structure of molybdenum oxide portions (223). The semiconductor device (200) is annealed by various methods, such as furnace annealing or rapid thermal annealing, such as lamp-based or laser annealing. In one embodiment, the device structure (200) is annealed at a temperature of about 200° C. to about 600° C., a vapor pressure of about 0.5 bar to about 75 bar, and a duration of about 15 minutes to about 2 hours. In some examples, the device structure (200) is annealed at a temperature of about 250° C. to about 550° C., such as about 300° C. to about 500° C., such as about 350° C. to about 450° C. In some examples, the device structure (200) is annealed at a pressure of about 25 bar to about 55 bar, such as about 30 bar to about 50 bar, such as about 35 bar to about 45 bar. In some examples, the device structure (200) is annealed for a duration of about 30 minutes to about 1.5 hours, such as about 45 minutes to 75 minutes. In one example, the device structure (200) is annealed at conditions of 325° C. and 55 bar for about 60 minutes.

[0034] In some embodiments, the thermal annealing is performed at high pressure and in the presence of a processing gas, such as hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases for high pressure gas annealing. Annealing the semiconductor device (200) at high pressure levels enables formation of a polycrystalline structure of the molybdenum oxide portions (223) even at low temperatures, such as below 350° C.

[0035] In operation (108), molybdenum oxide portions (223) are removed from the semiconductor device (200) to form a patterned molybdenum layer (204). FIG. 2d is a schematic cross-sectional view of a portion of the substrate (201) including the patterned molybdenum layer (204) after the molybdenum oxide portions (223) are removed. The removal of the molybdenum oxide portions (223) is illustrated as trenches in FIG. 2d. Gaps (205) are formed in the patterned molybdenum layer (204), and the lowermost portion of the gaps (205) is formed by the uppermost surface (207) of the substrate (201).

[0036] The molybdenum oxide portions (223) can be removed from the substrate (201) by any suitable etching process that is selective for molybdenum oxide, including wet etching or dry etching processes. For example, the molybdenum oxide portions (223) are removed from the substrate (201) by wet etching using an ammonia solution. The ammonia solution is selective for the oxidized portions (223). Thus, the oxidized portions (223) are removed, while the unoxidized patterned molybdenum layer (204) is not removed by the ammonia solution. The ammonia solution can include ammonia hydroxide at a concentration of about 26% w/w to about 30% w/w, such as about 28% w/w. The semiconductor device (200) may be exposed to the ammonia solution to etch the molybdenum oxide portions (223) to a desired depth for a duration of, for example, about 2 minutes to about 10 minutes.

[0037] In another example that may be combined with the examples and embodiments described herein, the molybdenum oxide portions (223) are removed from the semiconductor device (200) by wet etching using a pH 10 buffer solution. The pH 10 buffer solution includes a sodium compound, such as sodium tetraborate or sodium hydroxide. The semiconductor device (200) can be exposed to the pH 10 buffer solution to etch the molybdenum oxide portions (223) to a desired depth, such as for a duration of about 2 minutes to about 10 minutes. The use of an ammonia solution or a pH 10 buffer solution to selectively etch molybdenum oxide portions (223) etches the molybdenum oxide portions (223) without damaging the unoxidized patterned molybdenum layer (204) or other material layers and device structures of the semiconductor device (200).

[0038] FIG. 3 is a flow diagram of a method (300) for patterning a molybdenum layer of a device, such as a semiconductor device, by neutral atom beam etching, according to one embodiment. Similar to the embodiments illustrated in FIGS. 1 and 2 , the molybdenum layer (202) can be disposed directly on a substrate (201), or on another layer, such as a metal layer or a dielectric layer. Patterning the molybdenum layer (202) according to the present embodiment can be used to fabricate an interconnect structure of the semiconductor device (200). The patterning method (300) is performed in a process chamber, such as a plasma process chamber or a neutral atom beam etching apparatus. The method (300) of FIG. 3 is described below in conjunction with the drawings illustrated in FIGS. 4A-4C , which illustrate the semiconductor device (200) of FIG. 2 including the molybdenum layer (202) at different stages of the method (300). Additionally, although the method (300) is described below with reference to a molybdenum layer (202) utilized to form an interconnect structure, the method (300) may also be advantageously used with materials other than molybdenum and in other semiconductor device manufacturing applications.

[0039] In operation (302), a semiconductor device (200) including a molybdenum layer (202) (see FIG. 4A) is positioned in a plasma process chamber, such as an etching process chamber (not shown). The semiconductor device (200) may include one or more semiconductor devices that are in a manufacturing process or are in various fabrication stages. FIG. 4A is a schematic cross-sectional view of a portion of a semiconductor device (200) including a molybdenum layer (202) before portions of one or more layers disposed on a substrate (201) are removed, according to one embodiment. The drawing of FIG. 4A illustrates the semiconductor device (200) before a patterning process (e.g., neutral beam etching) is performed to modify portions of the molybdenum layer (202).

[0040] In operation (304), portions of the masking layer (203) are removed to form exposed portions (222) of the molybdenum layer (202), as illustrated in FIG. 4B. FIG. 4B is a schematic cross-sectional view of a portion of a semiconductor device (200) including the molybdenum layer (202) after portions of the masking layer (203) disposed on the molybdenum layer (202) are removed, according to one embodiment. Removal of these portions of the masking layer (203) forms voids (205), illustrated as trenches in FIG. 4B, in the masking layer (203), with lowermost portions of the voids (205) being formed by the exposed portions (222) of the molybdenum layer (202) (i.e., bounded or partially defined). Therefore, removal of portions of the masking layer (203) exposes portions of the molybdenum layer (202).

[0041] In operation (306), exposed portions of the molybdenum layer (202) are removed from the semiconductor device (200) to form a patterned molybdenum layer (204). FIG. 4C is a schematic cross-sectional view of a portion of the semiconductor device (200) including the patterned molybdenum layer (204) after the exposed portions (222) of the molybdenum layer (202) are removed. The removal of the exposed portions (222) forms voids (205), illustrated as trenches in FIG. 4C, in the patterned molybdenum layer (204), with lowermost portions of the voids (205) being formed by the uppermost surface of the substrate (201).

[0042] In the embodiment illustrated by FIGS. 3 and 4, the exposed portions (222) of the molybdenum layer (202) can be removed from the semiconductor device (200) by an accelerated atomic beam process. A suitable commercially available processing platform that may be advantageously utilized in accordance with the embodiments described herein is the NanoAccel™ platform available from Exogenesis Corp. of Billerica, Mass. It is contemplated that other suitably configured accelerated atomic beam platforms from other manufacturers may also be utilized in accordance with the embodiments herein.

[0043] In one example, the exposed portions (222) of the molybdenum layer (202) can be removed by a gas cluster ion beam (GCIB) etching. During the GCIB etching of the molybdenum layer (202), a pressurized inert gas can flow, expand, and accelerate within the processing chamber toward the exposed portions (222) of the molybdenum layer (202) to transfer energy to the outermost atoms of the exposed portions (222) and cause removal of the outermost atoms. In one embodiment, the gas cluster ion beam is formed of argon gas. In other embodiments, additional gases including oxygen (O ₂ ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ) can be combined with the inert gas to form the gas cluster ion beam.

[0044] The gas cluster ion beam can be directed in a substantially vertical path through the pores (205) in the masking layer (203) to penetrate desired portions of the molybdenum layer (202) to form a patterned molybdenum layer (204). Thus, other device structures or material layers on the semiconductor device (200) remain undamaged during the gas cluster ion beam etching. The gas cluster ion beam can be accelerated with an acceleration voltage of 10 KeV to 40 KeV, such as 15 KeV to 35 KeV. For example, the gas cluster ion beam is accelerated with an acceleration voltage of 25 KeV. The semiconductor device (200) can be exposed to the gas cluster ion beam for any suitable dose time, such as from about 0 seconds to about 30 seconds, including from 2-20 seconds. For example, the semiconductor device (200) can be exposed to the gas cluster ion beam for a dose time of 6, 8, 10, 14, or 18 seconds.

[0045] In another example that may be combined with the embodiments and examples described herein, an accelerated neutral atom beam (ANAB) etch is used to remove exposed portions (222) of a molybdenum layer (202) from a semiconductor device (200). Similar to the GCIB etch, the accelerated neutral atom beam etch utilizes a beam of accelerated gas cluster ions, but the gas clusters are dissociated and the charge is removed prior to impinging on the surface of the exposed portions (222). The accelerated neutral atom beam is directed in a substantially vertical path through pores (205) within the masking layer (203) to penetrate desired portions of the molybdenum layer (202). Additionally, each atom within the neutral atom beam has relatively low energy, resulting in limited surface modification of only a few atomic layers, thereby significantly reducing or eliminating etch damage to other materials and layers or to the semiconductor device (200).

[0046] The accelerated neutral atom beam is accelerated with an acceleration voltage of 10 KeV to 40 KeV, for example, 15 KeV to 35 KeV. For example, the accelerated neutral atom beam is accelerated with an acceleration voltage of 25 KeV. The semiconductor device (200) is exposed to the accelerated neutral atom beam for any suitable dose time, for example, from about 0 seconds to about 30 seconds, including 2-20 seconds. For example, the semiconductor device (200) can be exposed to the accelerated neutral atom beam for a dose time of 6, 8, 10, 14, or 18 seconds. Inert gases, such as argon, can be used to form the accelerated neutral atom beam. In some embodiments, additional gases including oxygen (O ₂ ), nitrogen (N ₂ ), methane (CH ₄ ), and sulfur hexafluoride (SF ₆ ) can be combined with the inert gas. ANAB etching can be performed under any suitable etching conditions.

[0047] FIG. 5 is a flow diagram of a method (500) for patterning a molybdenum layer of a device, such as a semiconductor device, by high pressure water anneal, according to one embodiment. Similar to the embodiments illustrated in FIGS. 1-4, the molybdenum layer may be disposed directly on a substrate surface, or on another layer, such as a metal layer or a dielectric layer. Patterning of the molybdenum layer according to this embodiment, which may be combined with other embodiments and examples described herein, may be used to fabricate interconnect structures of the device. The patterning method (500) is performed in a plasma process chamber, such as an etch process chamber, or other suitable process apparatus. Although the method (500) is described below with reference to a molybdenum layer utilized to form an interconnect structure, the method (500) may also be advantageously used with materials other than molybdenum and in other semiconductor device fabrication applications.

[0048] In operation (502), a semiconductor device including a molybdenum layer is positioned in a plasma process chamber, such as an etching process chamber (not shown). The semiconductor device may include one or more semiconductor devices in a manufacturing process. The semiconductor device further includes a substrate, a molybdenum layer disposed over the substrate, and a masking layer, similar to the substrate (201), the molybdenum layer (202), and the masking layer (203) described with respect to FIGS. 2 and 4 . The semiconductor device may also include other material layers disposed over the substrate, such as a barrier layer or a low-k insulating layer.

[0049] In operation (504), portions of the masking layer are removed to form exposed portions of the molybdenum layer. The removal of these portions of the masking layer forms voids (205) in the masking layer, with lowermost portions of the voids (205) being formed by the exposed portions of the molybdenum layer. The removal of the portions of the masking layer exposes portions of the molybdenum layer.

[0050] In operation (506), the semiconductor device is exposed to a high pressure water anneal (HPWA) process to remove exposed portions of the molybdenum layer from the semiconductor device. Although the method (500) describes a high pressure water anneal utilizing water vapor to anneal the semiconductor device, it is contemplated that other gases may be used to anneal the semiconductor device under high pressure. For example, the semiconductor device may be anneal at high pressure using hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases. In another example, the semiconductor device may be anneal using a combination of gases including hydrogen, deuterium, fluorine, chlorine, ammonium, and other suitable gases.

[0051] In operation (506), the processing chamber is pressurized by supplying water vapor from the pressure chamber to the processing chamber, followed by thermal annealing of the device and depressurization of the processing chamber by evacuation of the water vapor. The thermal annealing is performed at a temperature of about 250° C. to about 450° C., for example, about 300° C. to about 400° C. For example, the thermal annealing is performed at a temperature of about 325° C. to about 375° C. Additionally, the processing chamber is pressurized to a pressure of about 10 bar to about 75 bar, for example, about 20 bar to about 60 bar. For example, the processing chamber is pressurized to a pressure of about 30 bar to about 50 bar. Exposure of the device to high pressure steam annealing removes exposed portions of the molybdenum layer, forming a patterned molybdenum layer without damaging other device structures or material layers.

[0052] Embodiments of the present disclosure include methods for patterning a metal layer of a device to form features in the interconnection layer as part of a process for fabricating an interconnection structure of the device. Specifically, the disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. The increased selectivity in patterning the molybdenum layers enables the formation of interconnection structures as well as other metal layers without the disadvantages associated with patterning high hardness materials, including large undercuts and damage to other layers and structures stacked within a semiconductor device. Thus, the methods provided herein make molybdenum, as well as other high hardness metals, more desirable and viable materials for device structures, such as interconnection structures.

[0053] While the foregoing is directed to implementations of the present disclosure, other and additional implementations of the present disclosure may be devised without departing from the basic scope of the present disclosure, which scope is determined by the following claims.

Claims (20)

A method for forming a metal interconnection layer,
A step of forming a molybdenum layer on a substrate;
A step of forming a masking layer on the above molybdenum layer;
A step of patterning the masking layer to expose portions of the molybdenum layer;
A step of modifying exposed portions of the molybdenum layer with oxygen to form molybdenum oxide portions of the molybdenum layer;
A step of annealing the substrate at a temperature of 250° C. to 550° C. and a pressure of 25 bar to 55 bar to form a polycrystalline structure of the molybdenum oxide portions; and
After the step of annealing the substrate, a step of removing the molybdenum oxide portions from the substrate is included.
A method for forming a metal interconnect layer. In the first paragraph,
The exposed portions of the above molybdenum layer are modified by oxygen plasma doping.
A method for forming a metal interconnect layer. In the first paragraph,
The exposed portions of the above molybdenum layer are modified by direct oxygen implantation.
A method for forming a metal interconnect layer. In the first paragraph,
The molybdenum oxide portions of the above molybdenum layer are removed by a dry etching process.
A method for forming a metal interconnect layer. In the first paragraph,
The molybdenum oxide portions of the above molybdenum layer are removed by a wet etching process.
A method for forming a metal interconnect layer. In clause 5,
The molybdenum oxide portions of the above molybdenum layer are wet-etched with a pH 10 buffer solution.
A method for forming a metal interconnect layer. In clause 5,
The molybdenum oxide portions of the above molybdenum layer are wet-etched with an ammonia solution.
A method for forming a metal interconnect layer. In the third paragraph,
The above direct oxygen injection is performed at a voltage potential of 5 KeV to 30 KeV.
A method for forming a metal interconnect layer. In clause 5,
The above wet etching is performed for a duration of 2 to 10 minutes.
A method for forming a metal interconnect layer. In Article 6,
The above buffer solution comprises sodium tetraborate and sodium hydroxide.
A method for forming a metal interconnect layer. In Article 7,
The above ammonia solution contains ammonia hydroxide at a concentration of 28% w/w to 30% w/w.
A method for forming a metal interconnect layer. delete delete delete delete delete delete delete delete delete