KR20100128275A - 열 기계 플립 칩 다이 본딩 - Google Patents
열 기계 플립 칩 다이 본딩 Download PDFInfo
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- KR20100128275A KR20100128275A KR1020107016008A KR20107016008A KR20100128275A KR 20100128275 A KR20100128275 A KR 20100128275A KR 1020107016008 A KR1020107016008 A KR 1020107016008A KR 20107016008 A KR20107016008 A KR 20107016008A KR 20100128275 A KR20100128275 A KR 20100128275A
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Abstract
Description
도 2는 웨이퍼의 일례의 단면도이며;
도 3은 구리 기둥 범프가 부착된 도 2의 웨이터의 단면도이며;
도 4는 도금된 기판의 일례의 단면도이며;
도 5는 본 발명의 형태에 의한 도 4의 도금된 기판에 접합된 다이의 단면도이고;
도 6은 오버몰딩 및 언더필링된 도 5의 기판의 단면도이다.
Claims (19)
- 대응하는 하나 이상의 패드를 갖는 기판에 구리 부분과 본딩 캡을 구비한 하나 이상의 구리 기둥 범프를 포함하는 다이를 본딩하는 방법으로서:
상기 하나 이상의 구리 기둥 범프의 본딩 캡이 상기 하나 이상의 패드와 접촉하도록 상기 기판상에 상기 다이를 위치 결정하는 스텝; 및
상기 기판에 상기 다이를 본딩하기 위해 상기 하나 이상의 구리 기둥 범프에 열 기계 에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 1 항에 있어서,
상기 다이를 위치 결정하는 스텝 및 열 기계 에너지를 적용하는 스텝은 실질적으로 동시에 수행되는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 1 항에 있어서,
상기 본딩 캡은 솔더 캡을 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 3 항에 있어서,
상기 열 기계 에너지를 적용하는 스텝은 상기 솔더 캡을 적어도 부분적으로 용융시켜서 상기 기판에 상기 다이를 본딩하기 위해 충분한 열 기계 에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 1 항에 있어서,
상기 열 기계 에너지를 적용하는 스텝은 상기 기판에 상기 다이를 가압하기 위해 기계적 압력을 적용하면서 상기 하나 이상의 구리 기둥 범프에 초음파 에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 5 항에 있어서,
상기 초음파 에너지와 기계적 압력을 적용하기 전에 상기 다이를 예열하는 스텝을 더 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 제 5 항에 있어서,
상기 초음파 에너지와 기계적 압력을 적용하기 전에 상기 기판을 예열하는 스텝을 더 포함하는 것을 특징으로 하는 다이를 본딩하는 방법. - 각기 구리 부분과 본딩 캡을 포함하는 복수의 구리 기둥 범프를 웨이퍼상에 형성하는 스텝;
상기 복수의 구리 기둥 범프 중 하나 이상의 구리 기둥 범프를 각각 포함하는 복수의 다이로 상기 웨이퍼를 분리하는 스텝;
기판상에 상기 복수의 다이를 위치 결정하는 스텝; 및
상기 기판에 상기 복수의 다이를 서모소닉 본딩하는 스텝을 포함하는 것을 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 8 항에 있어서,
상기 기판은 복수의 도전성 패드를 포함하고, 상기 기판상에 상기 복수의 다이를 위치 결정하는 스텝은 복수의 구리 기둥 범프 각각의 본딩 캡이 상기 복수의 도전성 패드 각각에 접촉하도록 상기 복수의 다이를 위치 결정하는 스텝을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 9 항에 있어서,
상기 각 구리 기둥 범프의 본딩 캡은 솔더 캡을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 10 항에 있어서,
상기 기판에 상기 복수의 다이를 서모소닉 본딩하는 스텝은 상기 솔더 캡을 적어도 부분적으로 용용시키기 위해 상기 복수의 구리 기둥 범프에 열에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 9 항에 있어서,
상기 기판에 상기 복수의 다이를 서모소닉 본딩하는 스텝은 상기 복수의 구리 기둥 범프에 초음파 에너지를 적용하는 스텝, 및 상기 기판에 상기 복수의 다이를 가압하기 위해 기계적 압력을 적용하는 스텝을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 9 항에 있어서,
상기 기판에 상기 복수의 다이를 서모소닉 본딩하는 스텝은 상기 복수의 다이를 예열한 후에 상기 기판에 상기 복수의 다이를 본딩하기 위해 초음파 에너지와 기계적 압력을 적용하는 스텝을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 제 8 항에 있어서,
상기 복수의 다이를 오버몰딩 화합물로 적어도 부분적으로 커버링하는 스텝을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법. - 다이에 부착된 구리 부분과 상기 구리 부분에 부착된 본딩 캡을 각기 포함하는 복수의 구리 기둥 범프를 포함하는 플립 칩 다이를 기판에 본딩하는 방법으로서:
복수의 구리 기둥 범프 각각의 본딩 캡이 상기 기판상의 복수의 본딩 패드 중 대응하는 각 본딩 패드에 접촉하도록 상기 기판상에 상기 다이를 위치 결정하는 스텝; 및
상기 기판에 상기 다이를 서모소닉 본딩하는 스텝을 포함하는 것을 특징으로 하는 플립 칩 다이를 기판에 본딩하는 방법. - 제 15 항에 있어서,
상기 본딩 캡은 솔더 캡을 포함하는 것을 특징으로 하는 플립 칩 다이를 기판에 본딩하는 방법. - 제 16 항에 있어서,
상기 기판에 상기 다이를 서모소닉 본딩하는 스텝은 상기 솔더 캡을 적어도 부분적으로 용융시켜서 상기 복수의 구리 기둥 범프와 상기 기판상의 대응하는 복수의 본딩 패드 사이에 본딩을 형성하기 위해 상기 다이에 열 기계 에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 플립 칩 다이를 기판에 본딩하는 방법. - 제 17 항에 있어서,
상기 열 기계 에너지를 적용하는 스텝은 초음파 에너지와 기계적 압력을 적용하는 스텝을 포함하는 것을 특징으로 하는 플립 칩 다이를 기판에 본딩하는 방법. - 제 15 항에 있어서,
상기 기판에 상기 다이를 서모소닉 본딩하는 스텝은 상기 다이 및 상기 기판 중 하나 이상을 예열한 후에 상기 기판에 상기 다이를 가압하기 위해 기계적 압력을 적용하면서 상기 복수의 구리 기둥 범프에 초음파 에너지를 적용하는 스텝을 포함하는 것을 특징으로 하는 플립 칩 다이를 기판에 본딩하는 방법.
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US11/957,730 US7642135B2 (en) | 2007-12-17 | 2007-12-17 | Thermal mechanical flip chip die bonding |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170121743A (ko) * | 2015-02-25 | 2017-11-02 | 인텔 코포레이션 | 마이크로전자 구조체 내의 상호연결 패드를 위한 표면 마감부 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007028288B4 (de) * | 2007-06-20 | 2013-06-06 | Epcos Ag | Mit akustischen Wellen arbeitendes MEMS Bauelement und Verfahren zur Herstellung |
DE102008063401A1 (de) * | 2008-12-31 | 2010-07-08 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einem kosteneffizienten Chipgehäuse, das auf der Grundlage von Metallsäuren angeschlossen ist |
TWI445147B (zh) * | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | 半導體元件 |
TW201113962A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Chip having metal pillar structure |
US8546254B2 (en) * | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
TW201214584A (en) * | 2010-09-23 | 2012-04-01 | Walton Advanced Eng Inc | Flip-chip bonding method to reduce voids in underfill material |
TWI478303B (zh) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構 |
TWI451546B (zh) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | 堆疊式封裝結構、其封裝結構及封裝結構之製造方法 |
EP2671251A2 (de) | 2011-02-02 | 2013-12-11 | Pac Tech - Packaging Technologies GmbH | Verfahren und vorrichtung zur elektrischen kontaktierung von anschlussflächen zweier substrate |
US8939346B2 (en) | 2011-02-15 | 2015-01-27 | International Business Machines Corporation | Methods and systems involving soldering |
US8604597B2 (en) * | 2011-04-28 | 2013-12-10 | Monolithic Power Systems, Inc. | Multi-die packages incorporating flip chip dies and associated packaging methods |
US8513795B2 (en) | 2011-12-27 | 2013-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D IC configuration with contactless communication |
US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
US10192804B2 (en) * | 2012-07-09 | 2019-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace packaging structure and method for forming the same |
JP5967678B2 (ja) * | 2012-09-24 | 2016-08-10 | 国立研究開発法人産業技術総合研究所 | 半導体装置の製造方法、及び半導体製造装置 |
US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
CN102931108B (zh) * | 2012-10-10 | 2014-04-30 | 矽力杰半导体技术(杭州)有限公司 | 一种倒装芯片封装方法 |
US8932909B2 (en) | 2012-11-14 | 2015-01-13 | International Business Machines Corporation | Thermocompression for semiconductor chip assembly |
JP6161380B2 (ja) * | 2013-04-17 | 2017-07-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6147689B2 (ja) * | 2014-03-05 | 2017-06-14 | 株式会社東芝 | Mems装置 |
US10032699B1 (en) * | 2014-04-28 | 2018-07-24 | Amkor Technology, Inc. | Flip chip self-alignment features for substrate and leadframe applications |
DE102015116081A1 (de) * | 2015-09-23 | 2017-03-23 | Infineon Technologies Ag | Elektronisches Sensorbauelement mit einem Flip-Chip-montierten Halbleiterchip und einem Substrat mit einer Öffnung |
US9875986B2 (en) | 2015-10-09 | 2018-01-23 | International Business Machines Corporation | Micro-scrub process for fluxless micro-bump bonding |
US9806043B2 (en) | 2016-03-03 | 2017-10-31 | Infineon Technologies Ag | Method of manufacturing molded semiconductor packages having an optical inspection feature |
WO2018117361A1 (ko) * | 2016-12-23 | 2018-06-28 | 주식회사 루멘스 | 마이크로 엘이디 모듈 및 그 제조방법 |
JP6534700B2 (ja) * | 2017-04-28 | 2019-06-26 | アオイ電子株式会社 | 半導体装置の製造方法 |
TWI647769B (zh) * | 2018-02-14 | 2019-01-11 | 矽品精密工業股份有限公司 | 電子封裝件之製法 |
CN109065509A (zh) * | 2018-08-10 | 2018-12-21 | 付伟 | 带有单围堰及外移通孔的芯片封装结构及其制作方法 |
CN110233110B (zh) * | 2019-05-30 | 2021-04-27 | 同辉电子科技股份有限公司 | 一种GaN倒装芯片的焊接方法 |
US11316550B2 (en) | 2020-01-15 | 2022-04-26 | Skyworks Solutions, Inc. | Biasing of cascode power amplifiers for multiple power supply domains |
US12334885B2 (en) | 2021-07-09 | 2025-06-17 | Skyworks Solutions, Inc. | Biasing of cascode power amplifiers for multiple operating modes |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3470611A (en) * | 1967-04-11 | 1969-10-07 | Corning Glass Works | Semiconductor device assembly method |
JPH07115109A (ja) * | 1993-10-15 | 1995-05-02 | Nec Corp | フリップチップボンディング方法及び装置 |
JP2000174059A (ja) * | 1998-12-09 | 2000-06-23 | Matsushita Electric Ind Co Ltd | 電子部品の実装方法 |
JP4120133B2 (ja) * | 2000-04-28 | 2008-07-16 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2002158257A (ja) * | 2000-11-16 | 2002-05-31 | Mitsubishi Electric Corp | フリップチップボンディング方法 |
US7087458B2 (en) * | 2002-10-30 | 2006-08-08 | Advanpack Solutions Pte. Ltd. | Method for fabricating a flip chip package with pillar bump and no flow underfill |
FR2857153B1 (fr) * | 2003-07-01 | 2005-08-26 | Commissariat Energie Atomique | Micro-commutateur bistable a faible consommation. |
KR100604334B1 (ko) * | 2003-11-25 | 2006-08-08 | (주)케이나인 | 플립칩 패키징 공정에서 접합력이 향상된 플립칩 접합 방법 |
US7279359B2 (en) * | 2004-09-23 | 2007-10-09 | Intel Corporation | High performance amine based no-flow underfill materials for flip chip applications |
US7223695B2 (en) * | 2004-09-30 | 2007-05-29 | Intel Corporation | Methods to deposit metal alloy barrier layers |
US7505284B2 (en) * | 2005-05-12 | 2009-03-17 | International Business Machines Corporation | System for assembling electronic components of an electronic system |
TW200731430A (en) * | 2006-02-08 | 2007-08-16 | Jung-Tang Huang | Controllable method for manufacturing uniform planarity of plating-based solder bumps on multi-layer flip chip used in the three-dimensional packaging |
-
2007
- 2007-12-17 US US11/957,730 patent/US7642135B2/en active Active
-
2008
- 2008-11-10 KR KR1020107016008A patent/KR101592044B1/ko active Active
- 2008-11-10 CN CN2008801263666A patent/CN101939832A/zh active Pending
- 2008-11-10 EP EP08860881A patent/EP2232543A4/en not_active Withdrawn
- 2008-11-10 WO PCT/US2008/082972 patent/WO2009079114A2/en active Application Filing
- 2008-11-17 TW TW097144348A patent/TWI428967B/zh active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170121743A (ko) * | 2015-02-25 | 2017-11-02 | 인텔 코포레이션 | 마이크로전자 구조체 내의 상호연결 패드를 위한 표면 마감부 |
KR20220054886A (ko) * | 2015-02-25 | 2022-05-03 | 인텔 코포레이션 | 마이크로전자 구조체 내의 상호연결 패드를 위한 표면 마감부 |
KR20230071195A (ko) * | 2015-02-25 | 2023-05-23 | 인텔 코포레이션 | 마이크로전자 구조체, 그 제조 방법 및 그를 포함하는 전자 시스템 |
Also Published As
Publication number | Publication date |
---|---|
KR101592044B1 (ko) | 2016-02-05 |
EP2232543A2 (en) | 2010-09-29 |
EP2232543A4 (en) | 2012-05-16 |
US20090155955A1 (en) | 2009-06-18 |
US7642135B2 (en) | 2010-01-05 |
CN101939832A (zh) | 2011-01-05 |
WO2009079114A3 (en) | 2009-08-13 |
TWI428967B (zh) | 2014-03-01 |
WO2009079114A2 (en) | 2009-06-25 |
TW200941564A (en) | 2009-10-01 |
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