KR20020003001A - Method for forming epitaxial titanium silicide - Google Patents
Method for forming epitaxial titanium silicide Download PDFInfo
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- KR20020003001A KR20020003001A KR1020000037382A KR20000037382A KR20020003001A KR 20020003001 A KR20020003001 A KR 20020003001A KR 1020000037382 A KR1020000037382 A KR 1020000037382A KR 20000037382 A KR20000037382 A KR 20000037382A KR 20020003001 A KR20020003001 A KR 20020003001A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 229910021341 titanium silicide Inorganic materials 0.000 title claims abstract description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 34
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000010936 titanium Substances 0.000 claims abstract description 28
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 14
- 230000002776 aggregation Effects 0.000 abstract description 7
- 230000009466 transformation Effects 0.000 abstract description 5
- 238000005054 agglomeration Methods 0.000 abstract description 4
- 229910008484 TiSi Inorganic materials 0.000 description 63
- 239000000758 substrate Substances 0.000 description 21
- 238000009832 plasma treatment Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000006911 nucleation Effects 0.000 description 7
- 238000010899 nucleation Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 238000004220 aggregation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Chemical Kinetics & Catalysis (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 후속 열공정시 상변태 및 응집이 발생되는 것을 방지하는데 적합한 티타늄실리사이드막의 형성 방법에 관한 것으로, 이를 위한 본 발명은 실리콘층 표면에 질소플라즈마를 처리하여 상기 실리콘층 표면내에 질소트랩층을 형성하는 제 1 단계; 상기 질소트랩층을 포함한 실리콘층상에 티타늄막을 증착하고, 상기 티타늄막 증착시 상기 질소트랩층과 증착되는 티타늄막이 반응하여 티타늄나이트라이드막을 형성하는 제 2 단계; 및 상기 제 2 단계의 결과물에 열처리를 실시하여 상기 실리콘층 표면에 에피택셜 티타늄실리사이드막을 형성하는 제 3 단계를 포함하며, 상기 티타늄나이트라이드막은 상기 티타늄막과 실리콘층의 실리사이드반응을 억제시킨다.The present invention relates to a method of forming a titanium silicide film suitable for preventing phase transformation and agglomeration from occurring during a subsequent thermal process. The present invention provides a method for forming a nitrogen trap layer in the surface of the silicon layer by treating nitrogen plasma on the surface of the silicon layer. First step; Depositing a titanium film on the silicon layer including the nitrogen trap layer, and forming a titanium nitride film by reacting the nitrogen trap layer with the deposited titanium film when the titanium film is deposited; And a third step of forming an epitaxial titanium silicide film on the surface of the silicon layer by performing heat treatment on the resultant of the second step, wherein the titanium nitride film inhibits the silicide reaction between the titanium film and the silicon layer.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 실리콘기판과 금속의 접합부위에 적용하는 티타늄실리사이드(TiSi2)의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and to a method for forming titanium silicide (TiSi 2 ) applied to a junction portion of a silicon substrate and a metal.
일반적으로, 반도체소자의 성능 향상을 위해 비트라인(Bitline)이나 캐패시터전극(Capacitor electrode)으로 금속(Metal)을 사용하는데, 이 때 실리콘기판과 금속의 접합부분(Contact)에 티타늄실리사이드(이하 TiSi2라 약칭함)를 형성한다. 상기와 같은 초기 공정에 적용되는 TiSi2는 다결정(Polycrystalline)구조를 가지며, BPSG(Boro-Phospho-Silicate-Glass) 플로우(Flow)나 캐패시터 공정과 같은 후속 고온 공정을 거치게 되는데 종래의 방법으로 형성된 TiSi2는 응집(Agglomeration)현상이 발생하여 소자의 특성을 나쁘게 한다.In general, metal is used as a bit line or a capacitor electrode to improve the performance of a semiconductor device. In this case, a titanium silicide (hereinafter referred to as TiSi 2 ) at a contact portion of a silicon substrate and a metal is used. Abbreviated d). TiSi 2 applied to the initial process as described above has a polycrystalline structure and is subjected to a subsequent high temperature process such as BPSG (Boro-Phospho-Silicate-Glass) flow or capacitor process. 2 causes agglomeration to deteriorate device characteristics.
도 1은 종래기술에 따른 TiSi2의 형성 방법을 도시한 도면으로서, 실리콘기판(11)상에 티타늄을 증착한후, 질소(N2)분위기에서 급속열처리(Rapid Thermal Process; RTP)를 실시하여 TiSi2(12)를 형성한다.FIG. 1 is a view illustrating a method of forming TiSi 2 according to the prior art. After depositing titanium on a silicon substrate 11, a rapid thermal process (RTP) is performed in a nitrogen (N 2 ) atmosphere. To form TiSi 2 (12).
이 때, 상기 급속열처리는 1단계 또는 2단계로 진행하는데, 비트라인이나 캐패시터와의 접합부분은 후속 고온열공정을 받게 되므로 후속 열공정시 상변태에 의한 응집을 방지하기 위하여 2단계 열처리를 통해 안정상인 C54-TiSi2를 완전변태시킨다. 한편, 금속배선과의 접합부분은 후속 고온열공정이 없으므로 한 번의 열처리를 통해 C49-TiSi2를 형성한다.At this time, the rapid heat treatment proceeds in one or two stages, and the junction part with the bit line or the capacitor is subjected to a subsequent high temperature heat process, so that it is stable through a two-stage heat treatment to prevent agglomeration due to phase transformation during the subsequent heat process. Completely transforms C54-TiSi 2 . On the other hand, the junction part with the metal wiring does not have a subsequent high temperature heat process to form C49-TiSi 2 through one heat treatment.
그러나, 비트라인이나 캐패시터전극과의 접합부분에 적용되는 TiSi2를 C54-TiSi2로 완전변태시켜 안정상으로 형성하여도 후속 열공정, 예컨대, BPSG플로우, 캐패시터 열처리시에 C54-TiSi2의 새로운 핵생성과 입계성장(Grain growth)에 의해 TiSi2의 응집이 일어나고 실리콘기판(11)과 TiSi2(12)의 계면 거칠기(Roughness) 증가에 의해 저항이나 누설전류를 증가시킨다.However, even when TiSi 2 applied to the bit line or the junction with the capacitor electrode is completely transformed into C54-TiSi 2 to form a stable phase, the new C54-TiSi 2 is newly formed during subsequent thermal processes such as BPSG flow and capacitor heat treatment. Aggregation of TiSi 2 occurs by nucleation and grain growth, and resistance or leakage current is increased by increasing the interface roughness between the silicon substrate 11 and TiSi 2 (12).
또한, C54-TiSi2의 핵생성과 성장은, 2단계 급속열처리후에 남아있는 잔류 C49-TiSi2의 변태 또는 미반응 티타늄이 실리콘기판과 반응하면서 나타나는 현상으로 입계(Grain boundary)에서 시작된다. 이 때, 상기 입계(Grain boundary)는 격자변형에너지에 의해 에너지가 높은 지역으로, 새로운 상의 핵생성이 쉽게 일어나는 지역이다. 따라서 다결정 TiSi2의 경우, 잔류 C49-TiSi2이나, 미반응 티타늄을 제거하지 않으면 필연적으로 C54-TiSi2의 핵생성 및 성장에 의한 응집이 발생한다.In addition, nucleation and growth of C54-TiSi 2 begins at the grain boundary due to the transformation of residual C49-TiSi 2 remaining after the two-step rapid thermal treatment or unreacted titanium with the silicon substrate. At this time, the grain boundary is a region of high energy due to lattice strain energy, and is a region where nucleation of a new phase occurs easily. Accordingly, in the case of polycrystalline TiSi 2 , the remaining C49-TiSi 2 or unreacted titanium is inevitably caused by nucleation and growth of C54-TiSi 2 .
그리고, 이미 형성된 C54-TiSi2는 열역학적 에너지를 낮추기 위하여 결정입계 면적이 감소하는 그루빙(Grooving)현상이 발생하며, 이 과정에서 C54-TiSi2의 두께가 더욱 불균일해져 거칠기가 증가한다.And, in order to lower the thermodynamic energy of the already formed C54-TiSi 2 , a grooving phenomenon occurs in which the grain boundary area decreases, and in this process, the thickness of C54-TiSi 2 is more uneven and the roughness increases.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 실리사이드막의 응집현상을 방지하여 소자의 콘택저항 및 누설전류를 감소시키는데 적합한 티타늄실리사이드막의 형성 방법에 관한 것이다.The present invention has been made to solve the problems of the prior art, and relates to a method of forming a titanium silicide film suitable for preventing the aggregation phenomenon of the silicide film to reduce the contact resistance and leakage current of the device.
도 1은 종래기술에 따른 티타늄실리사이드막의 형성 방법을 개략적으로 도시한 도면,1 is a view schematically showing a method of forming a titanium silicide film according to the prior art;
도 2a 내지 도 2c는 본 발명의 실시예에 따른 에피택셜 C49-TiSi2의 형성ㅊ 방법을 도시한 도면,2A to 2C illustrate a method of forming epitaxial C49-TiSi 2 according to an embodiment of the present invention;
도 3a 및 도 3b는 질소플라즈마처리에 따른 TiSi2상의 구조변화를 도시한 그래프,3a and 3b are graphs showing the structural change of the TiSi 2 phase by nitrogen plasma treatment,
도 4a 및 도 4b는 질소플라즈마처리의 유무에 따른 TiSi2의 미세구조변화를 도시한 그래프,4a and 4b are graphs showing the microstructure change of TiSi 2 with or without nitrogen plasma treatment;
도 5a는 질소플라즈마처리를 실시하지 않은 C54-TiSi2의 단면을 도시한 도면,5A is a cross-sectional view of C54-TiSi 2 not subjected to nitrogen plasma treatment;
도 5b는 질소플라즈마를 처리하여 형성한 C49-TiSi2의 단면을 도시한 도면.5B is a view showing a cross section of C49-TiSi 2 formed by treating nitrogen plasma.
도 6은 후속 급속열처리온도에 다른 TiSi2의 구조변화를 도시한 그래프.FIG. 6 is a graph showing the structure change of TiSi 2 at different rapid heat treatment temperatures. FIG.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 실리콘기판 22 : 질소트랩층21 silicon substrate 22 nitrogen trap layer
23 : 티타늄막 24 : 티탄늄나이트라이드막23 titanium film 24 titanium nitride film
25 : C49-TiSi2 25: C49-TiSi 2
상기의 목적을 달성하기 위한 본 발명은 실리콘층 표면에 질소플라즈마를 처리하여 상기 실리콘층 표면내에 질소트랩층을 형성하는 제 1 단계; 상기 질소트랩층을 포함한 실리콘층상에 티타늄막을 증착하고, 상기 티타늄막 증착시 상기 질소트랩층과 증착되는 티타늄막이 반응하여 티타늄나이트라이드막을 형성하는 제 2 단계; 및 상기 제 2 단계의 결과물에 열처리를 실시하여 상기 실리콘층 표면에 에피택셜 티타늄실리사이드막을 형성하는 제 3 단계를 포함하며, 상기 티타늄나이트라이드막은 상기 티타늄막과 실리콘층의 실리사이드반응을 억제시키는 것을 특징으로 한다.The present invention for achieving the above object is a first step of forming a nitrogen trap layer in the surface of the silicon layer by treating nitrogen plasma on the surface of the silicon layer; Depositing a titanium film on the silicon layer including the nitrogen trap layer, and forming a titanium nitride film by reacting the nitrogen trap layer with the deposited titanium film when the titanium film is deposited; And a third step of forming an epitaxial titanium silicide film on the surface of the silicon layer by performing heat treatment on the resultant of the second step, wherein the titanium nitride film inhibits silicide reaction between the titanium film and the silicon layer. It is done.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 에피택셜 C49-TiSi2의 형성 방법을 도시한 도면이다.2A to 2C illustrate a method of forming epitaxial C49-TiSi 2 according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 티타늄(Ti)을 증착하기 전에 실리콘기판(21)에 400℃∼450℃온도와 3torr∼5torr의 압력하에서 N2또는 NH3플라즈마를 400W의 파워로 30초동안 처리하여 상기 실리콘기판(21)의 표면에 질소트랩층(22)을 형성한다. 이 때, 상기 질소트랩층(22)은 질소이온들이 실리콘(Si)의 빈격자(Vacancy site)에 침입하여 트랩되므로써 형성되는데, 상기 실리콘은 다이아몬드 큐빅(Diamond cubic)구조로 0, 3/4, 1/4 지점에 빈격자가 존재한다. 상기 질소트랩층(22)은 후속 티타늄 증착시 티타늄원자와 결합하여 티타늄나이트라이드(TiN)를 형성한다.As shown in FIG. 2A, the N 2 or NH 3 plasma is treated with a power of 400 W for 30 seconds on the silicon substrate 21 at a temperature of 400 ° C. to 450 ° C. and a pressure of 3 tor to 5 tor before depositing titanium (Ti). The nitrogen trap layer 22 is formed on the surface of the silicon substrate 21. At this time, the nitrogen trap layer 22 is formed by trapping nitrogen ions invading the vacancy site of silicon (Si), wherein the silicon has a diamond cubic structure of 0, 3/4, There is an empty lattice at quarter. The nitrogen trap layer 22 combines with titanium atoms to form titanium nitride (TiN) during subsequent titanium deposition.
도 2b에 도시된 바와 같이, 상기 질소트랩층(22)을 포함한 실리콘기판(21)상에 IMP(Ion Metal Plasma)법을 이용하여 티타늄(23)을 50Å∼300Å의 두께로 증착한다.As shown in FIG. 2B, titanium 23 is deposited to a thickness of 50 kPa to 300 kPa on the silicon substrate 21 including the nitrogen trap layer 22 by using IMP (Ion Metal Plasma) method.
도 2c에 도시된 바와 같이, 상기 티타늄(23) 증착후, 실리사이드반응을 위한 2단계 급속열처리를 실시한다. 이 때, 상기 급속열처리의 1단계는 670℃∼850℃에서 20초∼30초동안 질소분위기로 실시하며, 2단계는 850℃∼900℃에서 20초∼30초동안 질소분위기에서 실시한다.As shown in FIG. 2C, after the titanium 23 is deposited, a two-step rapid heat treatment for silicide reaction is performed. At this time, the first step of the rapid heat treatment is carried out in a nitrogen atmosphere for 20 seconds to 30 seconds at 670 ℃ to 850 ℃, the second step is carried out in a nitrogen atmosphere for 20 seconds to 30 seconds at 850 ℃ to 900 ℃.
상기와 같이 질소트랩층(22)이 형성된 상태에서 급속열처리를 실시하면 증착되는 티타늄(23) 원자와 질소트랩층(22)이 반응하여 티타늄나이트라이드(TiN)(24)를 형성하게 되고, 상기 티타늄나이트라이드(TiN)(24)는 실리콘과 티타늄의 확산을 방지하여 실리사이드의 형성 속도를 늦추게 된다.When the rapid heat treatment is performed in the state where the nitrogen trap layer 22 is formed as described above, the deposited titanium 23 atoms and the nitrogen trap layer 22 react to form titanium nitride (TiN) 24. Titanium nitride (TiN) 24 prevents the diffusion of silicon and titanium to slow down the formation of silicide.
즉, 후속 급속열처리공정에서 순수한 티타늄보다 티타늄과 실리콘의 반응이 억제되기 때문에, 티타늄나이트라이드막(24)의 형성이 먼저 일어나게 된다. 이러한 티타늄나이트라이드막은 실리콘과 티타늄의 확산을 방해하여 실리사이드반응이 느리게 진행되도록 하고, 따라서 에너지가 가장 안정한 에피택셜 C49-TiSi2(25)를 형성한다.That is, since the reaction between titanium and silicon is suppressed than pure titanium in the subsequent rapid heat treatment process, the formation of the titanium nitride film 24 occurs first. This titanium nitride film prevents the diffusion of silicon and titanium to allow the silicide reaction to proceed slowly, thus forming the most stable epitaxial C49-TiSi 2 (25).
이 때, 상기 C49-TiSi2(25)는 실리콘기판(21)과 (060)TiSi2//(200)Si, [001]TiSi2//[011]Si의 방위관계를 갖는 에피택셜층이며, 입계가 존재하지 않으므로 C54-TiSi2의 핵생성이 어렵고 입계면적 감소에 의한 그루빙현상이 발생하지 않는다.At this time, the C49-TiSi 2 (25) is an epitaxial layer having an orientation relationship between the silicon substrate 21 and (060) TiSi 2 // (200) Si, [001] TiSi 2 // [011] Si. Because of the absence of grain boundaries, nucleation of C54-TiSi 2 is difficult and no grooving occurs due to the reduction of the grain boundary area.
상기와 같이 에피택셜 C49-TiSi2(25)는 실리콘기판(21)과 반정합 계면을 형성하고 미스피트(Misfit) 전위를 형성하므로서 실리콘기판(21)과 티타늄실리사이드간의 계면에서의 변형에너지를 최소화한다.As described above, the epitaxial C49-TiSi 2 (25) forms a semi-matched interface with the silicon substrate 21 and forms misfit dislocations, thereby minimizing strain energy at the interface between the silicon substrate 21 and titanium silicide. do.
통상적으로 C49-TiSi2에서 C54-TiSi2로의 변태시 C54-TiSi2의 핵은 입계의 높은 에너지 지역에서 형성되는데, 에피택셜 C49-TiSi2(25)는 입계가 존재하지 않고 실리콘과의 계면만이 존재한다.Typically, when C49-TiSi 2 to C54-TiSi 2 is transformed, the nucleus of C54-TiSi 2 is formed in the high energy region of the grain boundary, and epitaxial C49-TiSi 2 (25) has no grain boundary but only an interface with silicon. This exists.
이렇듯 실리콘기판(21)과 에피택셜 C49-TiSi2(25)의 계면은 반정합을 형성하므로써 최소의 에너지만을 가지기 때문에, 일반적인 다결정 구조의 C49-TiSi2에 비해 C54-TiSi2의 핵생성이 일어나기가 어렵다. 따라서 후속 열공정시 에피택셜 C49-TiSi2(25)이 C54-TiSi2로의 상변태가 발생되지 않으며, C54-TiSi2의 핵생성 및 성장에 의한 티타늄실리사이드의 응집이 발생하지 않는다.As such, the interface between the silicon substrate 21 and the epitaxial C49-TiSi 2 (25) has only minimal energy by forming a semi-matched structure, so that nucleation of C54-TiSi 2 occurs as compared with C49-TiSi 2 having a general polycrystalline structure. Is difficult. Therefore, the phase transformation of epitaxial C49-TiSi 2 (25) to C54-TiSi 2 does not occur in the subsequent thermal process, and no aggregation of titanium silicide due to nucleation and growth of C54-TiSi 2 occurs.
도 3은 질소플라즈마처리에 따른 TiSi2상의 구조변화를 나타낸 도면으로서, 질소플라즈마처리를 실시하지 않은 경우(A), (311)면의 C54-TiSi2상이 나타나며, 질소플라즈마처리를 30초동안 실시한 경우(B), (060)면의 C49-TiSi2상이 나타난다.3 is a view showing the structural change of the TiSi 2 phase according to the nitrogen plasma treatment, when the nitrogen plasma treatment was not performed (A), the C54-TiSi 2 phase of the (311) surface appears, the nitrogen plasma treatment was performed for 30 seconds In the case (B), the (060) plane C49-TiSi 2 phase appears.
도 4a 및 도 4b는 질소플라즈마처리의 유무에 따른 TiSi2의 미세구조변화를 도시한 그래프로서, 질소플라즈마처리를 하지 않은 경우, (040)C54-TiSi2, (220) C54-TiSi2, (311)C54-TiSi2만이 나타나며, 질소플라즈마처리를 30초동안 실시한 경우에는 (020)C49-TiSi2, (040)C49-TiSi2, (111)TiN, (060)C49-TiSi2이 나타난다.4A and 4B are graphs showing the microstructural change of TiSi 2 with or without nitrogen plasma treatment, and (040) C54-TiSi 2 , (220) C54-TiSi 2 , (without nitrogen plasma treatment). 311) C54-TiSi 2 only appears, and (020) C49-TiSi 2 , (040) C49-TiSi 2 , (111) TiN, and (060) C49-TiSi 2 when nitrogen plasma treatment was performed for 30 seconds.
도 5a에 도시된 바와 같이, 질소플라즈마처리를 실시하지 않은 경우, 실리콘기판과 C54-TiSi2상의 계면에 입계가 존재함을 알수 있고, 도 5b에 도시된 바와 같이, 질소플라즈마처리(30초)를 실시한 경우, 실리콘기판과 C49-TiSi2의 계면에 입계가 존재하지 않고, C49-TiSi2의 (060)면과 실리콘기판의 (200)면이 평행함을 알 수있다. 여기서, 통상적으로 상기 실리콘기판의 (200)면은 (100)면과 평행하다.As shown in FIG. 5A, when the nitrogen plasma treatment is not performed, it can be seen that grain boundaries exist at the interface between the silicon substrate and the C54-TiSi 2 phase, and as shown in FIG. 5B, the nitrogen plasma treatment (30 seconds) is shown. In this case, it can be seen that no grain boundary exists at the interface between the silicon substrate and the C49-TiSi 2 , and the (060) plane of the C49-TiSi 2 and the (200) plane of the silicon substrate are parallel to each other. Here, typically, the (200) plane of the silicon substrate is parallel to the (100) plane.
도 6은 후속 급속열처리온도에 따른 TiSi2의 구조변화를 도시한 그래프로서, 1000℃의 열처리에서도 C49-TiSi2상이 존재함을 알 수 있는 반면, C54-TiSi2상은 존재하지 않는다.Figure 6 is a graph showing the structural change of the TiSi 2 with the subsequent rapid heat treatment temperature, it can be seen that the presence of the C49-TiSi 2 phase even in the heat treatment at 1000 ℃, while there is no C54-TiSi 2 phase.
상술한 것처럼, 티타늄 증착전에 질소플라즈마 처리를 실시하므로써 에피택셜 C49-TiSi2(25)이 후속 급속열처리공정시 1000℃까지 안정한 상태로 존재한다.As described above, epitaxial C49-TiSi 2 (25) is present in a stable state up to 1000 ° C. in the subsequent rapid heat treatment process by subjecting the nitrogen plasma treatment prior to titanium deposition.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명의 티타늄실리사이드 형성 방법은 실리콘기판에 질소플라즈마처리를 실시하여 실리콘기판의 (100)면과 (060)면이 평행한 에피택셜 C49-TiSi2의 형성하므로써 상변태가 발생하지 않은 열적으로 안정한 실리사이드막을 형성할 수 있는 효과가 있으며, 또한 상기 에피택셜 C49-TiSi2는 후속 열처리공정시 1000℃가지 응집이 발생하지 않으므로 금속비트라인 및 실리콘기판, 금속캐패시터전극과 실리콘기판과의 콘택형성시 저항 및 누설전류를 감소시킬 수 있는 효과가 있다.The titanium silicide formation method of the present invention described above is thermally free from phase transformation by subjecting the silicon substrate to nitrogen plasma treatment to form epitaxial C49-TiSi 2 in parallel with the (100) and (060) planes of the silicon substrate. Epitaxial C49-TiSi 2 is effective to form stable silicide film, and since the epitaxial C49-TiSi 2 does not generate 1000 ℃ of agglomeration in the subsequent heat treatment process, it forms a contact between a metal bit line, a silicon substrate, a metal capacitor electrode, and a silicon substrate. There is an effect that can reduce the resistance and leakage current.
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| JP2004253797A (en) * | 2003-02-21 | 2004-09-09 | Hynix Semiconductor Inc | Semiconductor device having epitaxial silicide titanium layer of C49 phase and method of manufacturing the same |
| GB2428888A (en) * | 2003-02-21 | 2007-02-07 | Hynix Semiconductor Inc | Epitaxial C49 titanium silicide contacts |
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| JP2004253797A (en) * | 2003-02-21 | 2004-09-09 | Hynix Semiconductor Inc | Semiconductor device having epitaxial silicide titanium layer of C49 phase and method of manufacturing the same |
| KR100538806B1 (en) * | 2003-02-21 | 2005-12-26 | 주식회사 하이닉스반도체 | SEMICONDUCTOR DEVICE WITH EPITAXIAL C49-TiSi2 LAYER AND METHOD FOR FABRICATING THE SAME |
| US7037827B2 (en) | 2003-02-21 | 2006-05-02 | Hynix Semiconductor Inc. | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same |
| GB2398927B (en) * | 2003-02-21 | 2006-12-27 | Hynix Semiconductor Inc | Method for fabricating a semiconductor device |
| GB2428888A (en) * | 2003-02-21 | 2007-02-07 | Hynix Semiconductor Inc | Epitaxial C49 titanium silicide contacts |
| GB2428888B (en) * | 2003-02-21 | 2008-02-06 | Hynix Semiconductor Inc | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same |
| US7476617B2 (en) | 2003-02-21 | 2009-01-13 | Hynix Semiconductor Inc. | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same |
| DE10361829B4 (en) * | 2003-02-21 | 2009-12-10 | Hynix Semiconductor Inc., Icheon | Method for producing a semiconductor component |
| US7868458B2 (en) | 2003-02-21 | 2011-01-11 | Hynix Semiconductor Inc. | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same |
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