JP2006332511A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a metallic silicide layer having no facet shape, and to reduce a junction leakage between a source-drain and a silicon board. <P>SOLUTION: The source-drain 5 is formed on the silicon board 1, and a metallic film (an Ni film) 6 for a silicification and a stress film 7 are formed on the source-drain 5. A laminated film composed of a TiN film and a Co film is formed as the stress film 7. When a silicification annealing is conducted under the state, the stress film 7 has a tensile stress 10a. The metallic film 6 for the silicification has a compressive stress 10b so as to correspond to the tensile stress. Accordingly, a reaction velocity is inhibited by silicification-reacting the metallic film 6 for the silicification with the silicon board 1. Consequently, an Ni mono-silicide layer (NiSi) having no facet shape can be formed. Accordingly, a junction leakage current between the source-drain 5 and the silicon board 1 can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal silicide layer for reducing the resistance of a source / drain of a transistor.

With the miniaturization of SoC (system on chip) devices, it is required to form the source and drain of transistors shallowly. In addition, it is required to reduce the resistance of the source and drain in order to increase the device speed. In order to satisfy these requirements, a structure in which a source / drain is formed shallow and a metal silicide layer is provided on the surface has been used.
For example, Patent Document 1 discloses a structure in which a metal silicide layer such as a Co (cobalt) silicide layer or a Ni (nickel) silicide layer is provided on the surface of a source / drain.

Here, an example in which a metal silicide layer is formed on the surface of the source / drain by a conventional method for manufacturing a semiconductor device will be described.
First, as shown in FIG. 25A, the gate insulating film 2 and the gate electrode 3 are formed on the main surface of the silicon substrate 1. Next, sidewalls 4 made of a silicon oxide film are formed on the side surfaces of the gate insulating film 2 and the gate electrode 3. Next, impurities are implanted into the surface of the silicon substrate 1, and the silicon substrate 1 is further heat-treated. As a result, the source / drain 5 is formed as shown in FIG.

  Next, as shown in FIG. 25C, a silicidation metal film 6 such as a Ni film is formed on the entire surface. Further, the silicidation metal film 6 is subjected to silicidation reaction with the silicon substrate 1. At the same time, the silicidation metal film 6 undergoes a silicidation reaction with the gate electrode 3. At this time, the unreacted silicide metal film remains on the silicon substrate 1 and the gate electrode 3. Next, the unreacted silicidation metal film is removed. As a result, as shown in FIG. 25 (d), the Ni monosilicide (NiSi) layer 8 a is exposed on the surface of the source / drain 5, and the Ni monosilicide (NiSi) layer 8 b is exposed on the surface of the gate electrode 3.

JP 2003-37083 A

  In the conventional method for manufacturing a semiconductor device, when the silicidation metal film 6 is silicidized with the silicon substrate 1, the silicidation reaction may locally proceed rapidly. In this case, as shown in FIG. 26, a metal silicide layer 8 a having a facet shape 25 is formed on the surface of the source / drain 5. This facet shape increases the junction leakage current between the source / drain 5 and the silicon substrate 1.

  The present invention has been made to solve the above-mentioned problems, and reduces junction leakage between a source / drain and a silicon substrate by forming a metal silicide layer having no facet shape on the surface of the source / drain. With the goal.

A method of manufacturing a semiconductor device according to the present invention includes: forming a first metal film that causes a silicidation reaction with the silicon substrate on a silicon substrate; and applying a tensile stress to the first metal film. However, the method includes a first step of siliciding the first metal film with the silicon substrate.
Other features of the present invention are described in detail below.

  According to the present invention, a metal silicide layer having no facet shape can be formed on the surface of the source / drain. As a result, junction leakage between the source / drain and the silicon substrate can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment 1 FIG.
1 to 8 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment.
The semiconductor device formed in this embodiment is formed on the main surface of silicon substrate 1 shown in FIG. First, although not shown, element isolation is formed on the surface of the silicon substrate 1. Next, a gate insulating film 2 and a gate electrode 3 are formed on the main surface of the silicon substrate 1. As the gate insulating film 2, for example, a silicon oxide film having a thickness of about 2 to 3 nm is formed. As the gate electrode 3, for example, a polycrystalline silicon film having a thickness of about 100 to 150 nm is formed.
Next, a silicon oxide film is formed on the entire surface of the silicon substrate 1 by chemical vapor deposition (CVD). Further, the entire surface of the silicon oxide film is etched back. As a result, sidewalls 4 are formed on the side surfaces of the gate insulating film 2 and the gate electrode 3 as shown in FIG.

  Next, impurities are ion-implanted into the surface of the silicon substrate 1 using the gate electrode 3 and the sidewalls 4 shown in FIG. Further, the silicon substrate 1 is heat treated. As a result, as shown in FIG. 2, the source / drain 5 is formed on the surface of the silicon substrate 1.

  Next, as shown in FIG. 3, a silicidation metal film 6 is formed on the entire surface of the silicon substrate 1. This film is a film that causes a silicidation reaction with the silicon substrate 1. For example, a Ni (nickel) film is formed with a thickness of about 5 to 10 nm. Further, as shown in FIG. 4, a stress film 7 is formed on the silicidation metal film 6. For example, a TiN (titanium nitride) film is formed with a film thickness of about 5 to 10 nm, and a Co (cobalt) film is formed thereon with a film thickness of about 5 to 10 nm. This film is a film that generates tensile stress inside the film itself (hereinafter referred to as “film having tensile stress”) when the silicidation metal film 6 is silicidized with the silicon substrate 1 in a later step. "). (Similarly, when a film generates a compressive stress inside the film itself, the film is referred to as a “film having a compressive stress”.)

Next, the silicon substrate 1 shown in FIG. 4 is heat-treated to cause the silicidation metal film 6 to undergo a silicidation reaction with the silicon substrate 1. At the same time, the silicidation metal film 6 undergoes a silicidation reaction with the gate electrode 3.
The heat treatment for the silicidation reaction (hereinafter referred to as “silicidation annealing”) is, for example, lamp annealing at a temperature of about 100 to 450 ° C. By performing heat treatment at the above temperature, the silicidation metal film (nickel film) 6 can be silicidized with the silicon substrate 1 and the gate electrode 3.

  As a result of the silicidation reaction, a Ni monosilicide (NiSi) layer 8a is formed on the surface of the source / drain 5 as shown in FIG. In addition, a Ni monosilicide (NiSi) layer 8 b is formed on the surface of the gate electrode 3. At this time, the silicidation metal film 6 a (hereinafter referred to as “unreacted silicidation metal film 6 a”) that has not been consumed by the silicidation reaction is formed on the silicon substrate 1, the gate electrode 3, and the sidewall 4. Remains on top.

In the silicidation reaction, the Ni monosilicide (NiSi) layer 8a shown in FIG. 5 does not have the facet shape 25 (see FIG. 26). The reason for this will be described. In general, it is known that in a solid phase reaction, the reaction proceeds abnormally fast due to the presence of stress, or conversely slows. Therefore, the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed.
Here, FIG. 6 shows an enlarged view of the dotted line portion A shown in FIG. 4 when the silicidation annealing is performed. When the silicidation annealing is performed, the stress film 7 has a tensile stress 10a (about 0.2 GPa). Correspondingly, the silicidation metal film 6 has a compressive stress of 10b (about 0.2 GPa). That is, silicidation annealing is performed in a state where tensile stress is applied to the silicidation metal film 6.
By performing the silicidation annealing in this way, the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed. Thereby, a Ni monosilicide (NiSi) layer 8 a having no facet shape can be formed on the source / drain 5.

Next, the unreacted silicidation metal film 6a shown in FIG. 5 and the stress film 7 thereon are removed with a chemical solution or the like. As a result, as shown in FIG. 7, the Ni monosilicide layer 8 a is exposed on the surface of the source / drain 5, and the Ni monosilicide layer 8 b is exposed on the surface of the gate electrode 3.
A transistor is formed on the main surface of the silicon substrate 1 by the manufacturing method described above. Further, as shown in FIG. 8, an interlayer insulating film 9 such as a silicon oxide film is formed on the entire surface of the silicon substrate 1.

In this embodiment, a Ni film is used as the silicidation metal film 6. The silicidation metal film 6 may be a film such as a Ti (titanium) film, a Co (cobalt) film, or a W (tungsten) film. Alternatively, a NiN (nickel nitride) film, a TiN (titanium nitride) film, a CoN (cobalt nitride) film, or a WN (tungsten nitride) film may be used. Alternatively, any one of a laminated film of a Ni film and a NiN film, a laminated film of a Ti film and TiN, a laminated film of a Co film and a CoN film, and a laminated film of a W film and a WN film may be used. There may be.
These films are films that cause a silicidation reaction with silicon. For this reason, these films can undergo a silicidation reaction with the silicon substrate 1 by silicidation annealing to form a metal silicide layer on the source / drain 5.

  In this embodiment, the silicidation metal film 6 is formed on the silicon substrate 1 (see FIG. 3), and the stress film 7 is formed thereon (see FIG. 4). However, a cap film such as a TiN film may be formed on the silicidation metal film 6 and the stress film 7 may be formed thereon. This cap film is a film for preventing abnormal oxidation of the metal silicide layer during silicidation annealing.

Next, the result of evaluating the junction leakage current between the source / drain 5 of the transistor formed by the manufacturing method of the present embodiment and the silicon substrate 1 will be described.
FIG. 9 is a graph plotting the junction leakage current between the source / drain 5 and the silicon substrate 1 shown in FIG. This graph shows that the leak current is smaller as the plotted curve is shifted to the left side.
A junction leakage current between the source / drain 5 and the silicon substrate 1 formed according to the present embodiment is plotted in a curve 11a. Further, the junction leakage current between the source / drain formed by the conventional technique and the silicon substrate is plotted in a curve 11b. When both are compared, the curve 11a is shifted to the left as a whole than the curve 11b. Therefore, it was confirmed that the junction leakage current between the source / drain 5 formed according to the present embodiment and the silicon substrate 1 is reduced as compared with the prior art.
This is presumably because the Ni monosilicide layer 8a having no facet shape was formed on the source / drain 5 of the transistor formed according to the present embodiment. Therefore, the junction leakage current between the source / drain 5 and the silicon substrate 1 can be reduced by the manufacturing method of the present embodiment.

Next, a modification of the present embodiment will be described.
As the stress film 7 shown in FIG. 4, a film having a tensile stress (a laminated film of a TiN film and a Co film) was formed. However, the stress film 7 may be a film having compressive stress when the silicidation annealing is performed. For example, a film in which a TiN film and a W (tungsten) film are sequentially stacked may be formed. Alternatively, a film in which a TiN film, a WN (tungsten nitride) film, and a W (tungsten) film are sequentially stacked may be formed.
FIG. 10 shows stresses that the stress film 7 and the silicidation metal film 6 have in silicidation annealing in this case. The stress film 7 has a compressive stress 12a of about 3.1 GPa. Corresponding to this stress, the silicidation metal film 6 has a tensile stress 12b. That is, silicidation annealing is performed in a state where compressive stress is applied to the silicidation metal film 6.

Data on the junction leakage current between the source / drain of the transistor formed by this method and the silicon substrate is currently being acquired. (It is considered that there is a possibility that the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed by the material of the silicidation metal film.)
Here, in the prior art, silicidation annealing is performed in a state where a TiN cap film is laminated on a silicidation metal without forming a stress film thereon. In this case, although the TiN cap film has a compressive stress of about 1.8 GPa, the abnormal oxidation of the metal silicide layer could not be sufficiently prevented. Therefore, when a film having a compressive stress is used as the stress film as in this modification, it is expected that a film having a compressive stress greater than 1.8 GPa is preferably used.

Embodiment 2. FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described. Here, the configuration different from that of the first embodiment will be mainly described.
First, in the same manner as in the first embodiment, the process from the step of forming element isolation on the silicon substrate 1 to the step of forming the silicidation metal film (Ni film) 6 (see FIGS. 1 to 3). Do.
Next, as shown in FIG. 11, an alloying metal film 13 is formed on the silicidation metal film 6. This film is a film that can cause an alloying reaction with the silicidation metal film 6 in the subsequent silicidation annealing. At that time, a film having tensile stress is used.
Next, the stress film 7 is formed on the alloying metal film 13 in the same manner as in the first embodiment.

The above-described silicidation metal film 6 and alloying metal film 13 may be continuously formed by the same apparatus. For example, it is formed by using a cluster tool including a chamber for forming the silicidation metal film 6 and a chamber for forming the alloying metal film 13.
FIG. 12 shows a configuration example of the cluster tool. This cluster tool includes transport system units 14 and 15. Around the transfer system unit 14, a silicidation metal film (Ni film or the like) film formation chamber 14a, a cap film (TiN film or the like) film formation chamber 14b, an alloying metal film (Co film, W film or the like) ) Deposition chambers 14c and 14d are provided. Around the transport system unit 15, a sputter etch chamber 15a, a degas (degassig extrusion) chamber 15b, a load lock chamber 15c, and a cooling chamber 15d are provided.
By using the cluster tool having the above configuration, the silicidation metal film 6 and the alloying metal film 13 can be continuously formed by the same apparatus. By forming in this way, oxidation and contamination at the interface of these films can be prevented. Thereby, when the silicidation metal film 6 undergoes a silicidation reaction with the silicon substrate 1, it is possible to suppress abnormal growth of the metal silicide layer.

Next, the silicon substrate 1 shown in FIG. 11 is heat-treated and silicidation annealing is performed. As a result, a Ni monosilicide (NiSi) layer 8a is formed on the surface of the source / drain 5 as shown in FIG. In addition, a Ni monosilicide (NiSi) layer 8 b is formed on the surface of the gate electrode 3.
At this time, the alloying metal film 13 causes an alloying reaction with the silicidation metal film 6 (or the stress film 7). Along with this, these films undergo volume changes. As described above, the alloying metal film 13 is a film having a tensile stress during the alloying reaction. Therefore, at this time, a tensile stress is applied to the silicidation metal film 6.

FIG. 14 shows an enlarged view of a dotted line portion A in FIG. 11 during the silicidation annealing. When the silicidation annealing is performed, the alloying metal film 13 has a tensile stress 16a. Corresponding to this stress, the silicidation metal film 6 has a compressive stress 16b. That is, silicidation annealing is performed in a state where tensile stress is applied to the silicidation metal film 6.
Therefore, as in the first embodiment, the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed. Therefore, a Ni monosilicide (NiSi) layer 8 a having no facet shape can be formed on the source / drain 5.
Other configurations of the present embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

  As described above, according to the manufacturing method of the present embodiment, the Ni monosilicide layer 8a having no facet shape can be formed on the source / drain 5 of the transistor. Therefore, as in the first embodiment, the junction leakage current between the source / drain 5 and the silicon substrate 1 can be reduced.

Embodiment 3 FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described. Here, the configuration different from that of the first embodiment will be mainly described.
First, in the same manner as in the first embodiment, the process from the step of forming element isolation on the silicon substrate 1 to the step of forming the silicidation metal film (Ni film) 6 (see FIGS. 1 to 3). Do.
Next, as shown in FIG. 15, a cap film 17 is formed on the silicidation metal film 6. For example, a metal nitride film such as a TiN film is formed with a thickness of about 5 to 10 nm. Further, a metal film 18 is formed thereon. For example, a pure metal film such as a Co film, a Ti film, a W film, or a Ni film is formed with a thickness of 50 nm or more, for example, a thickness of about 50 to 100 nm.

Next, the silicon substrate 1 shown in FIG. 15 is heat-treated and silicidation annealing is performed. This heat treatment is performed using an infrared lamp heating type annealing apparatus. When heat treatment is performed using this apparatus, a temperature gradient can be provided in the depth direction of the film to be heat-treated by increasing the reflectance of the outermost surface of the film to be heat-treated. Here, since the metal film 18 is formed with a film thickness of about 50 to 100 nm, the reflectance of the surface is increased, and infrared rays are hardly transmitted. For this reason, in the annealing, the temperature of the metal film 18 increases, but the temperature of the silicidation metal film 6 does not increase so much. Then, since the thermal expansions of the metal film 18 and the silicidation metal film 6 are different, stress is generated in each film.
FIG. 16 shows an enlarged view of a dotted line portion A in FIG. 15 during the silicidation annealing. At this time, the metal film 18 and the cap film 17 have a tensile stress 19a. Corresponding to this stress, the silicidation metal film 6 has a compressive stress 19b. That is, silicidation annealing is performed in a state where tensile stress is applied to the silicidation metal film 6.

As a result of the silicidation annealing described above, a Ni monosilicide (NiSi) layer 8a is formed on the surface of the source / drain 5 as shown in FIG. In addition, a Ni monosilicide (NiSi) layer 8 b is formed on the surface of the gate electrode 3.
At this time, as in the first embodiment, the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed. Therefore, a Ni monosilicide (NiSi) layer 8 a having no facet shape can be formed on the source / drain 5.
Other configurations of the present embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

  As described above, according to the manufacturing method of the present embodiment, the Ni monosilicide layer 8a having no facet shape can be formed on the source / drain 5 of the transistor. Therefore, as in the first embodiment, the junction leakage current between the source / drain 5 and the silicon substrate 1 can be reduced.

Embodiment 4 FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described. Here, the configuration different from that of the first embodiment will be mainly described.
First, in the same manner as in the first embodiment, the steps from the step of forming element isolation on the silicon substrate 1 to the step of forming the source / drain 5 on the surface of the silicon substrate 1 (see FIGS. 1 to 2). Do.

  Next, as shown in FIG. 18A, a back surface stress film 20 is formed on the back surface of the silicon substrate 1. Here, when the back surface stress film 20 is formed, a film having tensile stress is formed so that the back surface side of the silicon substrate 1 has a concave shape. Here, an enlarged view of a dotted line portion A in FIG. 18A is shown in FIG. Since the back surface stress film 20 is a film having a tensile stress, the warp 21 occurs so that the back surface side of the silicon substrate 1 has a concave shape.

Next, as shown in FIG. 19A, a silicidation metal film 6 is formed on the silicon substrate 1. An enlarged view of the dotted line portion A in FIG. 19A is shown in FIG. The warp 21 remains on the silicon substrate 1.
Next, as shown in FIG. 20A, the back stress film 20 is removed. An enlarged view of the dotted line portion A in FIG. 20A is shown in FIG. The silicon substrate 1 is flat and flat. The silicidation metal film 6 is formed in a state where the warp 21 is generated in the silicon substrate 1. Therefore, the silicidation metal film 6 has a compressive stress 22.

Next, the silicon substrate 1 shown in FIG. 20A is heat-treated and silicidation annealing is performed. As a result, a Ni monosilicide (NiSi) layer 8a is formed on the surface of the source / drain 5 as shown in FIG. In addition, a Ni monosilicide (NiSi) layer 8 b is formed on the surface of the gate electrode 3.
At this time, silicidation annealing is performed with the silicidation metal film 6 having the compressive stress 22.
Therefore, as in the first embodiment, the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 can be suppressed. Therefore, a Ni monosilicide (NiSi) layer 8 a having no facet shape can be formed on the source / drain 5.

As described above, according to the manufacturing method of the present embodiment, the Ni monosilicide layer 8a having no facet shape can be formed on the source / drain 5 of the transistor. Therefore, as in the first embodiment, the junction leakage current between the source / drain 5 and the silicon substrate 1 can be reduced.
Since other configurations are the same as those in the first embodiment, description thereof is omitted.

Next, a modification of the present embodiment will be described.
As the back stress film 20 shown in FIGS. 18A and 18B, a film having tensile stress was formed at the stage of forming the film. However, the back stress film 20 may be a film having compressive stress when the film is formed.

In this case, cross-sectional views corresponding to FIGS. 18B, 19B, and 20B are shown in FIGS. 22, 23, and 24, respectively. First, as shown in FIG. 22, a film having compressive stress is formed as the back stress film 20. Then, the warp 23 occurs so that the main surface side of the silicon substrate 1 has a concave shape. Next, a silicidation metal film 6 is formed on the silicon substrate 1 as shown in FIG. Here, the warp 23 remains in the silicon substrate 1. Next, as shown in FIG. 24, the back surface stress film 20 is removed. Then, the silicon substrate 1 is flat without being warped. Here, the siliciding metal 6 is formed in a state in which the warp 23 is generated in the silicon substrate 1. For this reason, the silicidation metal film 6 has a tensile stress 24.
In this case, silicidation annealing is performed in a state where the silicidation metal film 6 has a tensile stress 24.
According to this modification, as described in the modification of the first embodiment, there is a possibility that the reaction rate of the silicidation reaction between the silicidation metal film 6 and the silicon substrate 1 may be suppressed.

In the manufacturing method shown in the present embodiment (FIGS. 18 to 21), after forming the back stress film 20 having tensile stress, the silicidation metal film 6 is formed, and then the back stress film 20 is removed. Thus, the silicidation metal film 6 has a compressive stress 22 during silicidation annealing.
In order for the silicidation metal film 6 to have a compressive stress during the annealing, a back stress film is formed so that the main surface side of the silicon substrate 1 has a concave shape after the formation of the silicidation metal film 6. Alternatively, silicidation annealing may be performed. In this case, a film having compressive stress is formed as the back stress film. Even in this case, silicidation annealing can be performed in a state where the silicidation metal film 6 has a compressive stress. If silicidation annealing is performed as described above and then the back stress film 20 is removed, the same effects as in the present embodiment (FIGS. 18 to 21) can be obtained.

FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the stress which generate | occur | produces in silicidation annealing. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 shows a method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the junction leakage current of the interface of a source / drain and a board | substrate. The figure which shows the stress which generate | occur | produces in silicidation annealing. FIG. 6 shows a method for manufacturing a semiconductor device according to the second embodiment. FIG. 4 is a diagram showing a configuration of a semiconductor manufacturing apparatus according to a second embodiment. FIG. 6 shows a method for manufacturing a semiconductor device according to the second embodiment. The figure which shows the stress which generate | occur | produces in silicidation annealing. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device according to the third embodiment. The figure which shows the stress which generate | occur | produces in silicidation annealing. FIG. 10 is a diagram showing a method for manufacturing the semiconductor device according to the third embodiment. FIG. 6 shows a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 6 shows a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 6 shows a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 6 shows a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 10 shows a modification of the fourth embodiment. FIG. 10 shows a modification of the fourth embodiment. FIG. 10 shows a modification of the fourth embodiment. The figure which shows the manufacturing method of the conventional semiconductor. The figure which shows the facet shape of a metal silicide layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2 Gate insulating film, 3 Gate electrode, 4 Side wall, 5 Source / drain, 6 Metal film for silicidation, 7 Stress film, 8a, 8b Ni monosilicide layer, 13 Metal film for alloying, 17 Cap Film, 18 metal film, 20 back stress film, 25 faceted shape.

Claims (7)

Forming a first metal film that causes a silicidation reaction with the silicon substrate on the silicon substrate;
A first step of causing a silicidation reaction between the first metal film and the silicon substrate while applying a tensile stress to the first metal film;
A method for manufacturing a semiconductor device, comprising:   The first step includes forming a second metal film that causes an alloying reaction with the first metal film on the first metal film, and an alloying reaction of these metal films to form the second metal film. The method for producing a semiconductor device according to claim 1, further comprising a step of generating a tensile stress.   The method of manufacturing a semiconductor device according to claim 2, wherein the first metal film and the second metal film are continuously formed by the same apparatus.   The first step includes a step of forming a third metal film having a thickness of 50 nm or more on the first metal film, and heat-treating the surface of the third metal film by infrared lamp annealing to reduce the tensile stress. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of generating stress. Forming a first film on the back surface of the silicon substrate so that the back surface side of the silicon substrate has a concave shape;
Forming a first metal film that causes a silicidation reaction with the silicon substrate on the silicon substrate;
Removing the first film;
The silicidation reaction of the first metal film with the silicon substrate;
In order. Forming a first metal film that causes a silicidation reaction with the silicon substrate on the silicon substrate;
Forming a first film on the back surface of the silicon substrate such that the main surface side of the silicon substrate has a concave shape;
The silicidation reaction of the first metal film with the silicon substrate;
In order. The method of manufacturing a semiconductor device according to claim 1, wherein the silicidation step is performed by a heat treatment at a temperature of 100 to 450 ° C. 7.

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