KR20000066097A - Chip scale package and method of fabricating the same - Google Patents

Abstract

The present invention discloses a chip scale package and a method of manufacturing the same. In the disclosed invention, a ceramic substrate is attached to a surface of a semiconductor chip. Openings are formed in the ceramic substrate to expose the bonding pads of the semiconductor chip. In addition, a stepped portion is formed on both side walls of the opening of the ceramic substrate. A ball land is formed on the upper surface of the ceramic substrate. A metal pattern connecting the ball land and the bottom of the stepped portion is embedded in the ceramic substrate. One end of the metal pattern located at the bottom of the stepped portion is electrically connected to the bonding pad exposed by the metal wire. The opening of the ceramic substrate is molded by an encapsulant applied at the same height as the upper surface of the ceramic substrate. Solder balls are formed on the ball land where the other end of the metal pattern is exposed.

Description

Chip scale package and method of manufacturing the same {Chip scale package and method of fabricating the same}

The present invention relates to a chip scale package and a method of manufacturing the same.

In order to meet the demands of electronic devices such as miniaturization, high speed, and high functionality, semiconductor packages have been continuously developed in new forms and diversified types. In addition, the proper use of semiconductor packages has become important in response to the use of electronic devices. In memory semiconductor products, the miniaturization and thinning of packages is an important subject, and as a memory, there is a strong demand for high-density packaging of large-capacity semiconductor chips. In this respect, a package such as a thin small outlead package (TSOP) with a thickness of 1.0 mm has been developed.

However, since the existing package is too large in size, a chip scale package having a size similar to that of a semiconductor chip has recently been developed in accordance with the trend of light and thin.

Chip scale packages have the advantage that the size of the package can be set to the size of the chip, the research is being continued in accordance with the trend of light and short package. Two examples of a method and structure for manufacturing a conventional chip scale package using a pattern tape among such chip scale packages are shown in FIGS. 1 and 2.

First, in FIG. 1, the pattern film 3 is adhered to the upper portion of the semiconductor chip 1 via the buffer 4, and the pad 2 of the chip 1 is attached to the metal pattern of the pattern film 3 and the peninsula. Is connected by the metal wire 5. The insulating layer 6 is coated between the semiconductor chip 1 and the pattern film 3, and the solder balls 7 are mounted on the ball lands of the pattern film 3 exposed from the insulating layer 6.

Meanwhile, in FIG. 2, bumps 12 are formed on the pads 11 of the semiconductor chip 10, and the insulating layer 13 is coated on the surface of the semiconductor chip 10 to expose the bumps 12. The pattern film 14 is adhere | attached on the insulating layer 13, and the metal pattern is connected to the bump 12. FIG. The solder ball 15 is mounted on the ball land of the pattern film 14.

However, in the packages shown in FIGS. 1 and 2, the packaging process must be performed by first attaching the semiconductor chips separately to the pattern film, so that the packaging process cannot be performed at the wafer level, which is the direction of current package development. There is this.

Moreover, the pattern film which mostly consists of polyimides differs significantly in the material of a semiconductor chip from a thermal expansion coefficient. For this reason, the crack generate | occur | produced in the pattern film in many cases by the heat generate | occur | produced when driving a semiconductor chip.

The most representative and reliable method of forming solder balls is to apply paste solder to the ball lands, and to form solder balls through a reflow process using infrared rays. However, conventionally, ball lands are formed in a pattern film having elasticity or fluidity. When a paste solder is applied to a pattern film having such characteristics and a reflow process is performed, a situation arises in which the height of each solder ball is not constant due to the pattern film being stretched up and down. Inconsistent solder ball height means that lower height solder balls are not mounted on the substrate. Therefore, conventionally, the above-described method is not adopted, and there are inconveniences in that each solder ball prepared in advance at the same height is directly mounted on each ball land, and then bonded to the ball land by a reflow process.

In addition, the semiconductor chip generates very high heat during driving, and conventionally, this heat cannot be easily dissipated to the outside. This is because the thermal conductivity of the pattern film is not excellent. Therefore, in the related art, a heat sink must be separately provided for heat dissipation.

Accordingly, an object of the present invention is to provide a chip scale package and a method of manufacturing the same, which are designed to solve various problems of the conventional chip scale package.

Another object of the present invention is to prevent the occurrence of cracks due to high heat generated in the semiconductor chip by applying a member in which the semiconductor chip and the coefficient of thermal expansion are not very different in place of the pattern film.

Still another object of the present invention is to be able to form a solder ball with a uniform height using a paste-type solder.

An additional object of the present invention is to make heat dissipation very easy without providing a separate heat sink.

1 and 2 are cross-sectional views showing two types of conventional packages.

Figure 3a is a plan view showing a ceramic substrate applied to the package according to the first embodiment of the present invention.

3B is a longitudinal cross-sectional view of the ceramic substrate taken along line IIIb-IIIb of FIG. 3A.

4 to 7 are sectional views sequentially showing a method of manufacturing a chip scale package according to the first embodiment.

8 is a sectional view showing a chip scale package according to a second embodiment of the present invention.

9 is a sectional view showing a chip scale package according to a third embodiment of the present invention.

-Explanation of symbols for the main parts of the drawing-

20; Semiconductor chip 21; Bonding pads

30; Ceramic substrate 31; Opening

32; Stepped portion 33; Boland

34; Metal pattern 40; glue

50; Sealing agent 60; Solder ball

70; Metal wire 80; Suture plate

In order to achieve the above object, the chip scale package according to the present invention has the following configuration.

A ceramic substrate is attached to the surface of the semiconductor chip. Openings are formed in the ceramic substrate to expose the bonding pads of the semiconductor chip. In addition, a stepped portion is formed on both side walls of the opening of the ceramic substrate. A ball land is formed on the upper surface of the ceramic substrate. A metal pattern connecting the ball land and the bottom of the stepped portion is embedded in the ceramic substrate. One end of the metal pattern located at the bottom of the stepped portion is electrically connected to the bonding pad exposed by the metal wire. The opening of the ceramic substrate is molded by an encapsulant applied at the same height as the upper surface of the ceramic substrate. Solder balls are formed on the ball land where the other end of the metal pattern is exposed.

Here, when the bonding pad is disposed at the center of the semiconductor chip, the opening of the ceramic substrate is also formed at the center, and if the bonding pad is disposed at both sides, the bonding pad is composed of two formed at both sides. In addition, in order to prevent moisture penetration between the ceramic substrate and the semiconductor chip, it is preferable that both sides of the ceramic substrate are also molded with an encapsulant. Instead of molding the opening of the ceramic substrate with an encapsulant, a sealing plate for shielding the opening may be provided at the same height on the upper surface of the ceramic substrate.

A method of manufacturing a chip scale package having the above configuration is as follows.

First, a ceramic substrate having an opening, a stepped portion is formed on both side walls of the opening, a ball land is formed on the upper surface, and a metal pattern is formed inside the bottom surface of the stepped portion and the ball land. The ceramic substrate is attached to the entire surface of the wafer including the plurality of semiconductor chips through an adhesive so that the bonding pad of the semiconductor chip is exposed through the opening. The metal wire electrically connects the bonding pad and one end of the metal pattern located at the bottom of the stepped portion. The opening is molded with encapsulant or the opening is shielded with a sealing plate. Subsequently, a paste-type solder is applied to the ball lands of the ceramic substrate, and a reflow process using infrared rays is performed to form solder balls on each ball land. The wafer is cut along the scribe line and separated into individual packages.

According to the configuration of the present invention described above, since a rigid ceramic substrate is used instead of the conventional pattern film, the packaging process is possible at the wafer level. In addition, the solder balls can be formed to have a uniform height, and the high heat generated in the semiconductor chip is easily dissipated to the outside by the ceramic substrate having excellent thermal conductivity.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

Example 1

3A is a plan view showing a ceramic substrate applied to a package according to Embodiment 1 of the present invention, FIG. 3B is a longitudinal cross-sectional view of the ceramic substrate taken along line IIIb-IIIb of FIG. 3A, and FIGS. 4 to 7 are embodiments. 1 is a cross-sectional view sequentially illustrating a method of manufacturing a chip scale package according to FIG. 1.

First, in the present invention, instead of the conventional pattern film, a rigid substrate 30, and in this embodiment, a ceramic substrate 30 is used. The ceramic substrate 30 has an opening 31 formed along the center, as shown in FIGS. 3A and 3B. The position of the opening 31 is varied according to the bonding pad position of the semiconductor chip described later. That is, in the semiconductor chip applied in the first embodiment, since the bonding pads are disposed along the center, the opening 31 is also formed in the center of the ceramic substrate 30. Therefore, if the bonding pads are disposed on both sides of the semiconductor chip, the openings 31 will be composed of a pair disposed on both sides of the ceramic substrate 30.

A step portion 32 is formed on both side walls of the opening 31 of the ceramic substrate 30. In addition, grooves of a predetermined size and shape are formed in the upper surface of the ceramic substrate 30, and the grooves become ball lands 33 in which solder balls are formed. The shape of the ball land 33 is preferably an inverted truncated cone or a square truncated truncated cone. The ball land 33 and the bottom of the stepped portion 32 are electrically connected by the metal pattern 34. One end of the metal pattern 34 is positioned at the bottom of the stepped portion 32, and the other end is positioned at the ball land 33 through the inside of the ceramic substrate 30. As the material of the metal pattern 34, any one of gold, silver, nickel, indium, tin, and indium / tin alloy may be selected. In addition, the other end of the metal pattern 34, that is, the portion disposed on the ball land 33, has a tin / lead, lead / nickel / gold, copper / Selected from nickel / gold, copper / nickel / chrome / gold, copper / nickel / cobalt / gold, copper / nickel / gold / tin, copper / nickel / chrome / gold / tin, or copper / nickel / cobalt / gold / tin It is preferred that the alloy is plated.

A method of manufacturing a chip scale package using the ceramic substrate 30 having such a structure will be described in detail with reference to FIGS. 4 to 7.

First, as shown in FIG. 4, each scribe line of a wafer having a plurality of semiconductor chips 20 is partially etched to form grooves 22. The adhesive 40 is applied evenly to the entire surface of the wafer. The adhesive 40 is applied to the groove 22 thicker than other portions, so that the groove 22 is completely filled. In this way, the groove 22 is formed in the scribe line of the wafer, and the reason why the adhesive 40 is applied to the groove 22 is that the side surfaces of the semiconductor chips 20 are exposed after cutting the wafer individually. This is to prevent the penetration of moisture from the outside. Thereafter, a photosensitive film is applied to the entire surface of the adhesive 40, and the photosensitive film is exposed and developed to form a photosensitive film pattern. The bonding pads 21 are exposed from the adhesive 40 by etching the adhesive 40 using this photosensitive film pattern as an etching mask.

Subsequently, the ceramic substrate 30 prepared in advance is attached onto the wafer via the adhesive 40. In this case, the bonding pads 21 of the semiconductor chips 20 are exposed to the outside through the openings 31 of the ceramic substrate 30. In addition, the portion of the adhesive 40 applied to the grooves 22 is also exposed to the outside through the ceramic substrate 30.

Then, as shown in FIG. 5, one side of the metal pattern 34 positioned on the bottom surface of the step portion 32 and the bonding pad 21 are electrically connected to each other by the metal wire 70. The encapsulant 50 is filled in the portion between the opening 31 and each ceramic substrate 30 at the same height as the upper surface of the ceramic substrate 30, and the encapsulant 50 is cured. Subsequently, a paste-type solder is applied to the ball lands 33 of the ceramic substrate 30, and the solder is formed into a spherical solder ball 60 through a reflow process using infrared rays. Here, in the reflow process, since the ceramic substrate 30 is a rigid body without elasticity and fluidity, it can be always maintained in a flat state, and thus each solder ball 60 can be formed to have a uniform height. Therefore, the package mountability is improved.

Then, as shown in FIG. 6, the backside of the wafer is polished until the adhesive 40 applied to the grooves 22 is exposed, thereby removing a predetermined thickness of the wafer. Subsequently, both sides of each ceramic substrate 30, that is, the side surface of each ceramic substrate 30 and the interface between the encapsulant 50 are cut along and separated into individual packages as shown in FIG. 7. In the chip size package shown in FIG. 7, both sides of the ceramic substrate 30 are exposed to the outside, and heat dissipation is very easy. On the other hand, both sides of the semiconductor chip 20 are coated with an adhesive 40 to prevent moisture penetration. It is a blocked structure.

Example 2

8 is a cross-sectional view illustrating a chip scale package according to Embodiment 2 of the present invention. As shown in FIG. 7, both sides of the ceramic substrate 30 are blocked by the encapsulant 50 without being exposed to the outside. In the cutting process of FIG. 6, the chip scale package having the above-described structure does not cut along the interface between the ceramic substrate 30 and the encapsulant 50, and the center of the encapsulant 50 applied between the ceramic substrate 30 is not cut. By cutting along.

The chip scale package of this structure has an advantage of preventing the penetration of moisture through the ceramic substrate 30 and the adhesive 40.

Example 3

9 is a cross-sectional view illustrating a chip scale package according to Embodiment 3 of the present invention. As shown, in comparison with FIG. 7, the difference is that the opening 31 is not molded with the encapsulant 50. Instead, the upper portion of the opening 31 is sealed with the sealing plate 80.

The chip scale package of this structure is realized by slightly modifying the molding process. That is, before the molding process of FIG. 5, the groove 35 is formed on the innermost top wall of the opening 31 at a depth of about the thickness of the sealing plate 80, and the sealing plate 80 is covered with the groove 35. The surface of the sealing plate 80 and the upper surface of the ceramic substrate 30 are coplanar. Then, by performing the molding step, the encapsulant 50 is not applied into the opening 31, and the encapsulant 50 is applied only between the ceramic substrates 30.

As described above, according to the present invention, a rigid ceramic substrate is used instead of the conventional pattern film. Therefore, the packaging process can be performed at the wafer level.

In addition, due to the use of a ceramic substrate, it is possible to form a solder ball at a uniform height using a paste-type solder.

Since the thermal expansion coefficient of the ceramic, which is a material of the substrate, does not differ significantly from that of the semiconductor chip, cracks are prevented from occurring in the substrate due to heat generated while the semiconductor chip is being driven.

In addition, since the ceramic substrate itself has excellent heat dissipation characteristics, the high heat generated in the semiconductor chip can be more easily dissipated to the outside without providing a separate heat sink.

In particular, the process of adhering the ceramic substrate to the top of the wafer, the wire bonding process, and the process of separating into individual chips are the same as the existing packaging process, so that the existing equipment can be slightly modified and used as it is. Very advantageous.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.

Claims (15)

A semiconductor chip having a bonding pad disposed on a surface thereof; It is attached to the surface of the semiconductor chip via an adhesive, and has an opening for exposing the bonding pads, stepped portions are formed on the inner side wall of the opening, grooves to be a ball land is formed on the upper surface, the ball land and A rigid substrate having a metal pattern exposed at both ends through a bottom surface of the stepped portion; A metal wire electrically connecting the metal pattern positioned on the bottom surface of the stepped portion to the bonding pads; An encapsulant filled in the opening to have the same height as the surface of the substrate; And And a solder ball formed on the ball land of the substrate. The chip scale package of claim 1, wherein the substrate is made of a ceramic material. The chip scale package of claim 1, wherein the adhesive is applied to both sides of the semiconductor chip. The chip scale package of claim 1, wherein the encapsulant is applied to both sides of the substrate. The chip scale package of claim 1, wherein the metal pattern is made of one of gold, silver, nickel, indium, tin, and an indium / tin alloy. The method of claim 1, wherein the ball land comprises tin / lead, lead / nickel / gold, copper / nickel / gold, copper / nickel / chrome / gold, copper / nickel / cobalt / gold, copper / nickel / gold / tin, Chip scale package, characterized in that the plating of any one selected from copper / nickel / chromium / gold / tin, or copper / nickel / cobalt / gold / tin. A semiconductor chip having a bonding pad disposed on a surface thereof; It is attached to the surface of the semiconductor chip via an adhesive, and has an opening for exposing the bonding pads, stepped portions are formed on the inner side wall of the opening, grooves to be a ball land is formed on the upper surface, the ball land and A rigid substrate having a metal pattern exposed at both ends through a bottom surface of the stepped portion; A metal wire electrically connecting the metal pattern positioned on the bottom surface of the stepped portion to the bonding pads; A sealing plate shielding the opening at the same height as the upper surface of the substrate; And And a solder ball formed on the ball land of the substrate. 8. The chip scale package of claim 7, wherein the adhesive is applied to both sides of the semiconductor chip. A rigid substrate having an opening, having a stepped portion formed on both inner walls of the opening, and having a groove to be a ball land on an upper surface thereof, and having a metal pattern embedded therein with both ends exposed through the ball land and the bottom of the stepped portion. Doing; Applying an adhesive to a surface of a wafer composed of a plurality of semiconductor chips, and partially etching the adhesive to expose a bonding pad of the semiconductor chip; Bonding the substrate to expose a bonding pad through an opening on the wafer surface; Electrically connecting the bonding pad and the metal pattern positioned on the bottom surface of the stepped portion with a metal wire; Filling an encapsulant between the opening and each substrate, and curing the encapsulant; Applying paste in the form of solder to the ball land of the substrate, and forming the solder into solder balls through a reflow process using infrared rays; And And cutting the wafer along the scribe line of the wafer between the ceramic substrates and separating the package into individual packages. 10. The method of claim 9, wherein a ceramic is used as a material of the substrate. 10. The method of claim 9, wherein before the adhesive is applied, grooves are formed along each scribe line in the wafer, and the adhesive is evenly applied to completely fill the grooves, and then the rear surface of the wafer is applied to the grooves before the cutting process. And polishing until the exposed adhesive is exposed so that the adhesive applied to the groove of the wafer after the cutting process blocks the side surface of each semiconductor chip. The method of claim 9, wherein, in the cutting process, the substrate is cut along an interface between both sides of the substrate and an encapsulant, thereby exposing both sides of the substrate. 10. The method of claim 9, wherein during the cutting process, the substrate is cut along the center of the encapsulant such that both sides of the substrate are blocked by the encapsulant. 10. The method according to claim 9, wherein the ball land comprises tin / lead, lead / nickel / gold, copper / nickel / gold, copper / nickel / chrome / gold, copper / nickel / cobalt / gold, copper / nickel / gold / tin, A method of manufacturing a chip scale package comprising plating an alloy selected from copper / nickel / chrome / gold / tin or copper / nickel / cobalt / gold / tin. A ceramic substrate having an opening, having a stepped portion formed on both inner walls of the opening, and having a groove to be a ball land on an upper surface thereof, and having a metal pattern embedded therein with both ends exposed through the ball land and the bottom of the stepped portion. step; Forming a groove along a scribe line on a wafer including a plurality of semiconductor chips, applying an adhesive on the surface of the wafer so as to completely fill the groove, and then partially etching the adhesive to expose a bonding pad of the semiconductor chip ; Bonding the substrate to a surface of the wafer such that a bonding pad is exposed through an opening; Electrically connecting the bonding pad and the metal pattern positioned on the bottom surface of the stepped portion with a metal wire; Shielding the opening with a suture plate coplanar with an upper surface of the substrate; Filling an encapsulant between each of the substrates and curing the encapsulant; Applying paste in the form of solder to the ball land of the substrate, and forming the solder into solder balls through a reflow process using infrared rays; Polishing the back side of the wafer until the adhesive applied in the groove of the wafer is exposed; And And cutting the wafer along a scribe line of the wafer and separating the package into individual packages.