CN1316611C - Wafer-level semiconductor package with build-up structure and manufacturing method thereof - Google Patents

Abstract

A wafer level semiconductor package with a build-up structure comprises a glass frame with a through hole, at least one chip accommodated in the through hole of the glass frame, a low-modulus buffer material filled in a gap between the chip and the glass frame, the build-up structure formed on the chip and the glass frame and electrically connected with the chip, and a plurality of conductive components welded on the build-up structure for electrically connecting the chip with an external device; by using the glass frame and the low modulus buffer material, the wafer level semiconductor packaging piece of the invention has no problems of structural warping, cracking and delamination, and can be effectively thinned to meet the requirements of thin products; in addition, the invention can reduce the packaging cost without using a glue injection mould, is not easy to absorb moisture and can improve the reliability of the product; the invention further provides a manufacturing method of the wafer level semiconductor package.

Description

Wafer-level semiconductor package with build-up structure and manufacturing method thereof

technical field

The present invention relates to a wafer-level semiconductor package and its manufacturing method, in particular to a build-up structure formed on the Active Surface of a chip so that the external contacts (External Contacts) for solder ball implantation A wafer-level semiconductor package extending out of the active surface of the chip and its manufacturing method.

Background technique

With the development of electronic products becoming thinner and smaller, the semiconductor packages of the core components of electronic products are also developing in the direction of miniaturization. One form of miniaturized semiconductor package developed in this field is chip scale package (Chip Scale Package, CSP), which is characterized in that the size of this chip scale package is equal to or about 1.2 times larger than the chip size.

In addition to the miniaturization of the size of the semiconductor package, it is also necessary to increase the integration level and the number of input/output terminals (I/O Contact) for electrical connection with external devices such as circuit boards, in order to meet the high performance and high processing requirements of electronic products. The need for speed. The way to increase the number of input/output ports is generally to arrange as many bond pads as possible on the active surface of the chip, but the number of bond pads arranged on the active surface of the chip must be limited by the area of the active surface and the The pitch between pads (Pitch); in order to further arrange a greater number of input/output terminals on a limited area, wafer-level packages, such as wafer-level chip-scale packages (Wafer Level CSP), have emerged.

Wafer-level packaging uses a wire redistribution technology (Redistribution Layer Technology, RDL), which forms a dielectric layer (DielectricLayer) on the active surface of the chip, and then opens a hole in the dielectric layer to expose the active surface of the chip. Welding pads, and then form a plurality of wires on the dielectric layer, so that one end of each wire is electrically connected to the pads on the chip, and the other end forms a contact (contact), and then laying a resistor on the dielectric layer Solder Mask Layer (Solder Mask Layer) to cover the wires and pads, and finally, a plurality of openings (openings) are formed in the solder resist layer so that the contacts of the wires can be exposed from the corresponding openings for soldering ball soldering. Although this kind of build-up layer structure (Build-up Layer) formed by wire redistribution technology can effectively increase the number of input/output terminals electrically connected between the chip and the outside world, it is still limited by the limited area on the active surface of the chip.

In order to further increase the number of input/output terminals connected to the chip externally, the solution is to fan-out the layout range of the input/output terminals to an area outside the active surface of the chip. This kind of semiconductor package that extends the build-up structure to areas other than the chip is shown in U.S. Patent No. 6,271,469. As shown in FIG. In the colloid 62 formed by the program (Molding Process), the active surface 602 of the chip 60 exposes the surface 622 of the colloid 62 after the colloid 62 is formed, and the build-up structure 64 (by the dielectric layer 642, the wire 644 and the solder resist layer 646 structure) is formed on the active surface 602 of the chip 60 and the surface 622 of the colloid 62, the build-up structure 64 is electrically connected to the pad 604 of the chip 60 through a wire 644, so that the solder ball 66 is implanted to the build-up layer After the structure 64 is electrically connected to the wire 644 , the chip 60 can be electrically connected to the outside through the solder ball 66 .

Although the structure of the semiconductor package 6 can provide a larger input/output layout area, thereby increasing the number of input/output terminals, the colloid 62 is not formed on a substrate (Substrate) with higher hardness, and embedded in the middle. The part of the chip 60 is thinner than the surrounding part where the chip is not embedded, so it is easy to warp in the temperature cycle of the subsequent process, and due to the influence of stress concentration, cracking (Crack) often occurs at the place labeled 624; At the same time, since the chip 60 is roughly covered by the colloid 62, the difference in the coefficient of thermal expansion (Coefficient of Thermal Expansion, CTE) between the two will cause delamination (Delamination) between the chip 60 and the colloid, which will affect the quality of the finished product.

In order to solve the disadvantages of the aforementioned semiconductor package in US Pat. No. 6,271,469, US Pat. No. 6,498,387 provides a semiconductor package in which chips are supported on a glass plate. As shown in Figure 8, this semiconductor package 7 is that the chip 70 is stuck on the glass plate 71, then, on the chip 70, coat epoxy resin layer (Epoxy) 72, after the chip 70 is covered, on the The solder pad 702 on the chip 70 is exposed outside the hole in the epoxy resin layer 72, and then, on the epoxy resin layer 72, a plurality of wires 73 electrically connected to the solder pad 702 are formed, and then the epoxy resin layer A solder resist layer 74 is laid on the solder resist layer 72 to cover the wire 73 , and then, the exposed part of the wire 73 outside the hole is opened on the solder resist layer 74 for the solder ball 75 to be implanted on the exposed wire 72 .

The U.S. Patent No. 6,498,387 uses a glass plate 71 as a carrier for the chip 70. The hard property of the glass plate 71 can solve the problem of colloid warping and fragmentation in the No. 6,271,469 patent, and because the glass plate 71 and the chip The CTE of 70 is similar, so there is no problem of delamination caused by the above-mentioned CTE difference; yet, this chip 70 is glued on the glass plate 71, so that the overall thickness of the semiconductor package 7 of the No. 6,498,387 patent is the chip 70, glass The sum of the thicknesses of the board 71 and the build-up structure formed on the chip 70 prevents the semiconductor package 7 from being effectively thinned to meet the requirement. In addition, the chip 70 is completely covered by the epoxy resin layer 72, often due to the difference in the thermal expansion coefficient (CTE Mismatch) between the chip 70 and the epoxy resin layer 72, in the temperature cycle of the subsequent process, the chip 70 is subjected to thermal stress. cracks due to the influence. Simultaneously, the side 720 of this epoxy resin layer 72 is directly exposed to the atmosphere, and because of the high hygroscopicity of the epoxy resin itself, the external water vapor will accumulate on the active surface of the chip 70 through the epoxy resin layer 72, so It will lead to the Popcorn problem, and furthermore, the reliability of the finished product cannot be improved.

It can be seen from the above that the semiconductor packages of the No. 6,271,469 and No. 6,498,387 patents both have some urgent problems to be solved.

Contents of the invention

To overcome the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a wafer-level semiconductor package with a build-up structure that is free from warping, cracking and delamination, and can improve reliability.

Another object of the present invention is to provide a wafer-level semiconductor package with a build-up structure that can be effectively thinned to meet requirements.

Another object of the present invention is to provide a method for manufacturing a wafer-level semiconductor package with a build-up structure that does not require an injection mold and can reduce packaging costs.

Another object of the present invention is to provide a wafer-level semiconductor package with a build-up structure that is less prone to moisture absorption and can improve product reliability.

In order to achieve the above and other objects, the present invention provides a wafer-level semiconductor package with a build-up structure, which includes: a rigid frame with at least one through hole; at least one chip accommodated in the rigid frame, And there is a gap formed between the chip and the hard frame; a low-modulus buffer material used to fill the gap; a build-up structure formed on the chip and the hard frame, so that the build-up structure and the chip form an electrical connection relationship ; and a plurality of conductive components electrically connected to the build-up structure.

When the thickness of the chip is the same as that of the hard frame, the non-active surface (InactiveSurface, relative to the active surface of the chip and the build-up structure) of the chip is exposed to the semiconductor package, which can be used for heat sink (Heat Sink) Or Heat Spreader) is bonded to the non-active surface, so that the heat generated by the chip can be directly dissipated to the outside by the heat sink, thereby improving the heat dissipation effect. When the thickness of the chip is slightly smaller than that of the hard frame, the low-modulus buffer material can cover the non-active surface of the chip to provide a better protection effect for the chip.

The build-up structure, as disclosed in the aforementioned U.S. Patent Nos. 6,271,469 and 6,498,387, consists of at least one dielectric layer, a plurality of wires formed on the dielectric layer and electrically connected to pads on the active surface of the chip, And a solder resist layer coated on the dielectric layer and the wire and forming an opening for electrically connecting the conductive component and the wire.

The present invention also provides a method for manufacturing a wafer-level semiconductor package with a build-up structure, which includes the following steps: preparing a rigid frame with a plurality of through holes arranged in an array and placing it in a jig for carrying ; placing at least one chip on the jig for carrying through the corresponding through hole, and maintaining a preset gap between the peripheral side of the chip and the rigid frame; filling the gap with a low-modulus buffer material, The chip and the hard frame are separated by the low-modulus buffer material; after the buffer material is baked, the jig for carrying is separated from the hard substrate; a build-up structure electrically connected to the chip is formed; A plurality of conductive components electrically connected to the build-up structure are implanted in the build-up structure for the chip to be electrically connected to external devices through the conductive components; Wafer-level semiconductor package with build-up structure.

Another manufacturing method provided by the present invention includes the following steps: placing a module board composed of a plurality of rigid frames with through holes arranged in an array into the receiving groove of the carrying fixture, and making the carrying fixture The plurality of chips bonded on the board are respectively accommodated in the corresponding through holes of the hard frame, and a preset gap is formed between the chip and the corresponding hard frame; the low modulus buffer material is filled in the gap , the chip and the hard frame are separated by the low-modulus buffer material; the module board containing the chip is separated from the jig for carrying; a layer-up structure is formed on the module board and the chip, and the chip is electrically connecting with the build-up structure, and electrically connecting a plurality of conductive components to the build-up structure; and performing singulation operation to form the wafer-level semiconductor package with the build-up structure.

In addition, it should be noted that the "hard frame" in the present invention is defined as a frame made of existing chemical materials, which will not warp or deform at high temperatures or in temperature cycles; low-modulus cushioning materials It is defined as a material with thermoelastic effect (Thermoelastic) and low thermal expansion coefficient.

In summary, the wafer-level semiconductor package and its manufacturing method of the present invention can provide a package with a build-up structure that has no warping, no cracking, and no delamination problems and can improve reliability, and can effectively produce Thinned products are produced to meet the demand, and the cost of packaging can be reduced without the use of injection molds. At the same time, it is not easy to absorb moisture and can improve product reliability.

Description of drawings

1 is a cross-sectional view of a wafer-level semiconductor package according to Embodiment 1 of the present invention;

2A to 2G are schematic flow charts of the steps of the manufacturing method of the wafer-level semiconductor package shown in FIG. 1;

3A to 3D are schematic flowcharts of another embodiment of the steps of the wafer-level semiconductor package shown in FIG. 1 before forming a build-up structure;

4 is a cross-sectional view of a wafer-level semiconductor package according to Embodiment 3 of the present invention;

5 is a cross-sectional view of a wafer-level semiconductor package according to Embodiment 4 of the present invention;

6 is a front view of another embodiment of the rigid frame used in the wafer-level semiconductor package of the present invention;

Figure 7 is a cross-sectional view of U.S. Patent No. 6,271,469; and

Fig. 8 is a cross-sectional view of US Patent No. 6,498,387.

Detailed ways

Example 1

The wafer-level semiconductor package with a build-up structure and its manufacturing method of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1 , the wafer-level semiconductor package 1 with a build-up structure of the present invention is mainly composed of a rigid frame 10 having a through hole 100, a chip 11 accommodated in the through hole 100 of the rigid frame 10, The low-modulus buffer material 12 filled between the rigid frame 10 and the chip 11, the build-up structure 13 formed on the rigid frame 10 and the chip 11, and a plurality of solder balls implanted on the build-up structure 13 (That is, the above-mentioned conductive component) 14 constitutes.

The rigid frame 10 is made of glass material, metal material (such as copper metal, etc.), thermosetting material (such as polyimide resin (Polyimide Resin), BT resin (Bismaleimide Triazine Resin), and FR-4 and other materials. Since the hard frame 10 will not warp and deform under high-temperature environment or temperature cycle in the process, it is used as the main body (Primary Structured body) of the wafer-level semiconductor package 1, and the packaged wafer-level semiconductor package There is no warpage problem, and its rigidity will not cause the colloid to easily produce cracks (Crack) at the corners of the chip grooves as described in the No. 6,271,469 U.S. Patent. The penetration of the rigid frame 10 The hole 100 runs through the first surface 101 and the opposite second surface 102 of the rigid frame 10 , and should be formed in the central portion of the rigid frame 10 .

The chip 11 has an active surface 110 formed with electronic components (Electronic Components) and electronic circuits (Electronic Circuits) and a non-active surface 111 relative to the active surface 110. In the middle, the active surface 110 is coplanar with the first surface 101 of the rigid frame 10, and the non-active surface 111 is coplanar with the second surface 102 of the rigid frame 10, that is, the chip 11 is coplanar with the rigid frame 10 The frame 10 has the same thickness; at the same time, when the chip 11 is placed in the through hole 100 of the rigid frame 10, there is a gap between the chip 11 and the rigid frame 10 so that the two are not in contact. In addition, a plurality of bonding pads 112 are formed on the active surface 110 of the chip 11 .

The low-modulus buffer material 12 is made of low-modulus materials such as polyimide resin, silica gel, epoxy resin, etc. After filling the gap between the chip 11 and the rigid frame 10, it has the characteristics of elasticity and can Become a buffer medium between the chip 11 and the hard frame 10, so that in the temperature cycle of the process, the thermal stress generated by the hard frame 10 on the chip 11 due to the difference in thermal expansion coefficient between the hard frame 10 and the chip 11, It can be effectively released by the low-modulus buffer material 12, so that the chip 11 does not have problems of cracking and delamination, so the yield and reliability of the finished product of the wafer-level semiconductor package 1 of the present invention can be improved.

The build-up structure 13 is mainly composed of a dielectric layer 130 laid on the chip 11 and the rigid frame 10, a plurality of wires 131 formed on the dielectric layer 130 and electrically connected to the pads 112 on the chip 11. and a solder resist layer 132 for covering the dielectric layer 130 and the wires 131 . Since the build-up structure 13 and its forming method are in the prior art, it will not be repeated here. At the same time, the build-up structure 13 can further form at least one dielectric layer and a plurality of wires (not shown) on the dielectric layer 130 and the wires 131 as required.

FIG. 2A to FIG. 2G are schematic diagrams of the steps of the manufacturing method of the above-mentioned wafer-level semiconductor package 1 .

Referring to FIG. 2A, the first step of the wafer-level semiconductor package manufacturing method according to Embodiment 1 of the present invention is to prepare a module board 10' made of glass material, which includes a plurality of rigid frames with a rectangular through hole 100 in the center 10 (separated by dotted lines), and each rigid frame 10 has a first surface 101 and an opposite second surface 102 .

Referring to Fig. 2B, the module board 10' is placed into the receiving groove 160 of the carrying fixture 16, and the carrying fixture 16 is provided with a through hole 161 connected to the receiving groove 160, each of which The opening position of the hole 161 is at the center of the through hole 100 corresponding to the module board 10 ′.

Referring to FIG. 2C, a chip 11 is placed in each through hole 100. The chip 11 is placed in such a way that the active surface 110 of the chip 11 faces down to the through hole 161 of the fixture 16, and its non-active surface 111 faces upward and is exposed. in the atmosphere. At the same time, the thickness of the chip 11 is set to be the same as the thickness of the module board 10', so when the chip 11 is placed in the through hole 100 and carried on the module board 10', the non-active surface 111 is in contact with each rigid frame. The second surface 102 of 10 is coplanar. In addition, the cross-sectional area of the through hole 100 is larger than the area of the chip 11. Therefore, when the chip 11 is inserted into the through hole 100, there will be no contact between the peripheral side of the chip 11 and the wall of the through hole 100, but a pre-defined Let the gap S be. Furthermore, after the chips 11 are carried on the predetermined position of the jig 16 through the through hole 100 , the air in the through hole 161 is exhausted immediately so that each chip 11 is vacuum-adsorbed on the jig 16 for carrying.

Referring to Fig. 2D, since the module board 10' has the function of a screen printing screen, the scraper 15 of the screen printing method will be used such as silicone, ring, etc. without using a screen separately. The low-modulus cushioning material 12 such as epoxy resin or polyimide is filled into the gap S between each chip 11 and the rigid frame 10, that is, the chip 11 is covered by the low-modulus buffer material 12 and the rigid frame 10. separated.

Referring to FIG. 2E , after properly baking the low-modulus buffer material 12 (not shown), the module board 10 ′ containing the chip 11 is separated from the fixture 16 .

Referring to FIG. 2F, a dielectric layer 130 is coated on each of the first surface 101 of the rigid frame 10 and the active surface 110 of the chip 11, and then in a conventional manner, including but not limited to photolithographic techniques (Photolithographic Technique) And laser drilling (Laser Drilling), etc., open a perforation (not marked) at the position corresponding to the welding pad 112 on the active surface 110 of the chip 11; then, in any existing way, including but not limited to photolithography , forming a plurality of patterned (Patterned) wires 131 on the dielectric layer 130, so that one end of each of the wires 131 is electrically connected to the pad 112 on the chip 11 through the through hole of the dielectric layer 130, so as to connect the wire 131 from the pad 112 extends outward from the peripheral side of the chip 11, and makes the other end of each of the wires 131 form a connection terminal (ContactTerminal) (not shown); then, lay a solder resist layer 132 on the wires 131 and the dielectric layer 130 , and then open a plurality of openings (not marked) in any existing way to expose the connection ends of the wires 131, so that a plurality of solder balls 14 can be planted on the connection ends of the wires 131 respectively, so that each solder ball 14 forms an electrical connection with the build-up structure 13 composed of the dielectric layer 130 , the wire 131 and the solder resist layer 132 . The material of the solder ball 14 itself and the way of implanting it on the build-up structure 13 are all prior art, so it will not be described again.

Finally, as shown in FIG. 2G , the singulation operation (Singulation) is performed in any existing manner to form the wafer-level semiconductor package 1 as shown in FIG. 1 .

As can be seen from the above, the chip 11 and the hard frame 10 of the wafer-level semiconductor package 1 of the present invention are separated by the low-modulus buffer material 12, so the heat generated by the hard frame 10 during the temperature cycle of the manufacturing process Stress is effectively relieved by the low modulus cushioning material 12 . At the same time, using the hard frame 10 as the main structural component of the wafer-level semiconductor package 1 does not need to wrap the chip with a packaging compound (Molding Compound) as in the prior art, which can simplify the packaging process and avoid the existing molding compound. The colloid (Encapsulant) is easy to warp and lead to the problem of chip fragmentation and delamination; the rigid frame 10 can also be used as a low modulus buffer to fill the gap S between the chip 11 and the rigid frame 10 by screen printing The stencil required for the material 12 enables the manufacturing method of the present invention to save the use of stencils, thereby saving the production cost of the stencil and material management costs, and further reducing the packaging cost.

In addition, the chip 11 of the wafer-level semiconductor package 1 of the present invention is accommodated in the rigid frame 10, so the height of the wafer-level semiconductor package 1 is equal to that of the rigid frame 10, the build-up structure 13 and the solder balls 14. The sum of the heights is obviously smaller than the height of the package disclosed in U.S. Patent No. 6,498,387 (it is the sum of the heights of the glass carrier, the chip, the build-up structure and the solder balls), making the wafer-level semiconductor package of the present invention Part 1 can meet the requirement of thinning. Therefore, if the wafer-level semiconductor package 1 of the present invention is to be further thinned, after the steps shown in FIG. 111 and the exposed surface of the low-modulus buffer material 12, perform grinding operations (Grinding) in any existing manner, including but not limited to mechanical grinding, so that the hard frame 10, the chip 11 and the low-modulus buffer material 12 is reduced in thickness. Since the grinding operation is a prior art, it will not be described in detail here.

Example 2

The manufacturing method to be disclosed in Embodiment 2 of the present invention is substantially the same as the manufacturing method in Embodiment 1 above, so only the differences will be described with reference to the accompanying drawings.

Referring to FIG. 3A , prepare a module board 20' consisting of a plurality of rigid frames 20 arranged in an array, each rigid frame 20 also has a rectangular through hole 200, a first surface 201 and an opposite second surface 202; meanwhile, Prepare a carrying jig 26 with a storage groove 260, stick a film 27 on the bottom surface of the storage groove 260, and stick a plurality of chips 21 at preset positions on the film 27, and the material of the film 27 is selected and carried A material whose adhesive force between the clips 26 is greater than the adhesive force between the chip 21 and the module board 20' is used.

Referring to Fig. 3B, put the module board 20' into the receiving groove 260 of the carrying jig 26, so that the module board 20' is glued on the film 27, and at the same time, the chips 21 on the film 27 are respectively corresponding and accommodated in the through holes 200 of each rigid frame 20 , and a gap S is formed between the chip 21 and the rigid frame 20 .

Referring to FIG. 3C, the module board 20' is used as a screen, and the low-modulus buffer material 22 is filled into the gap S between the chip 21 and the rigid frame 20 with the scraper 15 of the screen printing method, so that the chip 21 and the rigid frame 20 Rigid frame 20 is separated by low modulus cushioning material 22 . At the same time, the adhesive force between the material of the low modulus buffer material 22 and the film 27 must be smaller than the adhesive force between the carrying fixture 26 and the film 27 .

Referring to FIG. 3D , after the low-modulus cushioning material 22 is baked, the module board 20 ′ containing the chip 21 is separated from the carrying jig 26 , due to the adhesion between the carrying jig 26 and the film 27 The force is greater than the adhesive force between the module board 20', the chip 21, the low-modulus buffer material 22 and the film 27, so after the module board 20' is separated from the carrier fixture 26, the film 27 will still adhere to the carrier. With the clamp 26, it will not be separated from the module board 20'.

The rest of the steps of forming the build-up structure, ball planting, and singulation are the same as those described in Example 1, and the finished product is also the same, so no further description is given.

Example 3

4 is a cross-sectional view of a wafer-level semiconductor package according to Embodiment 3 of the present invention. The structure of the wafer-level semiconductor package 3 of this embodiment 3 is roughly the same as that of the above-mentioned embodiment 1, and the difference is that the thickness of the chip 31 is smaller than the thickness of the rigid frame 30, so the low-mold substrate is printed by screen printing. When the digital buffer material 32 is filled into the gap between the chip 31 and the rigid frame 30, the low modulus buffer material 32 will cover the non-active surface 311 of the chip 31, so that the chip 31 is covered by the low modulus except the active surface 310. Modular cushioning material 32 wraps. In this way, it will reduce the precision requirements on the consistency between the thickness of the hard frame 30 and the chip 31, so when the thickness of the chip 31 is to be smaller than the thickness of the hard frame 30, the gap between the two should be 0.05 to 0.5 mm, but the difference between the two should be 0.1 mm. mm is better.

Example 4

5 is a cross-sectional view of a wafer-level semiconductor package according to Embodiment 4 of the present invention. The structure of the wafer-level semiconductor package 4 of the fourth embodiment is substantially the same as that of the first embodiment, except that, in order to improve the heat dissipation efficiency, the exposed non-active surface 411 of the chip 41 and the second surface of the hard frame 40 402 is coated with a thermally conductive adhesive 48 , and then a heat sink 49 is glued on the thermally conductive adhesive 48 , so that the heat generated by the chip 41 can be directly dissipated into the atmosphere through the heat sink 49 .

Example 5

6 is a front view of another embodiment of the rigid frame used in the wafer-level semiconductor package of the present invention. The rigid frame 50 disclosed in Embodiment 5 is substantially the same as that in the above-mentioned embodiments, the difference is that, in order to further avoid the cracking of the rigid frame 50 at the corner end 500' of the through hole 500 due to stress concentration, the The corner end 500 ′ of the through hole 500 is rounded to effectively release the concentration effect of stress and avoid cracking of the rigid frame 50 .

Claims (27)

1. wafer level semiconductor packaging part with layer reinforced structure is characterized in that this semiconductor package part comprises:

Stereoplasm frame, it has a through hole;

At least one chip, it is accommodated in the through hole of this stereoplasm frame, and and this stereoplasm frame between be formed with the gap;

Low modulus padded coaming, it is filled between this chip and stereoplasm frame in the formed gap;

Layer reinforced structure, it is formed on this stereoplasm frame and the chip, and forms electrical connection with this chip; And

A plurality of conductive components, it is electrically connected to this layer reinforced structure, electrically connects for this chip and external device.

2. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that the thickness of this stereoplasm frame is identical with the thickness of this chip.

3. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that the thickness of this stereoplasm frame is greater than the thickness of this chip.

4. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 3 is characterized in that the thickness difference of this stereoplasm frame and chip chamber is preferably 0.05 to 0.5mm.

5. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 3 is characterized in that the thickness difference of this stereoplasm frame and chip chamber is preferably 0.1mm.

6. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that the non-action face of this chip exposes in the atmosphere.

7. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 6 is characterized in that, also can connect on the non-action face of this chip and establish fin.

8. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, the non-action face of this chip is covered by this low modulus padded coaming.

9. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that this through hole is a rectangular opening.

10. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 9 is characterized in that the angle end of this through hole is by corners.

11. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.

12. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that, this low modulus padded coaming is to be selected from a kind of in the cohort that silica gel, epoxy resin and polyimide resin form.

13. the wafer level semiconductor packaging part with layer reinforced structure as claimed in claim 1 is characterized in that this conductive component is a soldered ball.

14. the method for making with wafer level semiconductor packaging part of layer reinforced structure is characterized in that this method for making comprises the following steps:

Prepare a module board of arranging by a plurality of one-tenth array way that stereoplasm frame constituted with through hole;

This module board is inserted carrying with in the formed accommodating groove of jig;

In each through hole, insert at least one chip, make it to be carried on this carrying, and make between the corresponding stereoplasm frame of this chip and module board and be formed with default gap with on the jig;

To hang down the modulus padded coaming and be filled in this gap, this chip and stereoplasm frame should be separated by low modulus padded coaming;

This module board is separated with jig with carrying;

Form layer reinforced structure on this module board and chip, and make this layer reinforced structure be electrically connected to this chip, and make a plurality of conductive component conductions be connected to this layer reinforced structure; And

Cut single job to form the wafer level semiconductor packaging part that this has layer reinforced structure.

15. method for making as claimed in claim 14 is characterized in that, this low modulus padded coaming is to be web plate with this module board, inserts gap between chip and stereoplasm frame with stencil printing.

16. method for making as claimed in claim 14 is characterized in that, when the thickness of chip and stereoplasm frame was identical, the non-action face of this chip exposed outside this low modulus padded coaming.

17. method for making as claimed in claim 14 is characterized in that, during less than the thickness of this stereoplasm frame, the non-action face of this chip should be covered by low modulus padded coaming at the thickness of chip.

18. method for making as claimed in claim 14 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.

19. method for making as claimed in claim 14 is characterized in that, this low modulus padded coaming is a kind of in the cohort formed of silica gel, epoxy resin and polyimide resin.

20. method for making as claimed in claim 14 is characterized in that, this conductive component is a soldered ball.

21. the method for making with wafer level semiconductor packaging part of layer reinforced structure is characterized in that this method for making comprises the following steps:

To insert carrying with in the accommodating groove of jig by the module board that stereoplasm frame constituted that a plurality of one-tenth array way are arranged with through hole, and make this carrying with on the jig bonding a plurality of chips be accommodated in the through hole of this corresponding stereoplasm frame and the gap that formation is preset between this chip and corresponding stereoplasm frame respectively;

To hang down the modulus padded coaming and be filled in this gap, this chip and stereoplasm frame should be separated by low modulus padded coaming;

This module board of taking in chip is separated with jig with carrying;

Form layer reinforced structure on this module board and chip, and this chip and layer reinforced structure are electrically connected, and make a plurality of conductive components be electrically connected to this layer reinforced structure; And

Cut single job to form the wafer level semiconductor packaging part that this has layer reinforced structure.

22. method for making as claimed in claim 21 is characterized in that, this low modulus padded coaming is to be web plate with this module board, inserts gap between chip and stereoplasm frame with stencil printing.

23. method for making as claimed in claim 21 is characterized in that, when the thickness of chip and stereoplasm frame was identical, the non-action face of this chip exposed outside this low modulus padded coaming.

24. method for making as claimed in claim 21 is characterized in that, during less than the thickness of this stereoplasm frame, the non-action face of this chip should be covered by low modulus padded coaming at the thickness of chip.

25. method for making as claimed in claim 21 is characterized in that, a kind of the making in the cohort that this stereoplasm frame is made up of glass material, metal material and thermosets.

26. method for making as claimed in claim 21 is characterized in that, this low modulus padded coaming is selected from a kind of in the cohort of being made up of silica gel, epoxy resin and polyimide resin.

27. method for making as claimed in claim 21 is characterized in that, this conductive component is a soldered ball.

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