KR102398177B1 - Magnetic memory device - Google Patents

Abstract

The present invention relates to a magnetic memory device, comprising a plurality of first memory cells connected between word lines and first bit lines crossing each other, each of the first memory cells being a first memory element and a first memory cell connected thereto A plurality of second memory cells including a first selection element and connected between the word lines and second bit lines crossing each other, each of the second memory cells is a second memory element and a second selection element connected thereto a device, wherein each of the first and second memory devices includes a magnetic tunnel junction including a pinned layer, a free layer, and a tunnel barrier layer therebetween, wherein the magnetic tunnel of some of the second memory devices The junction provides a magnetic memory device having an irreversible resistance state due to dielectric breakdown of the tunnel barrier layer.

Description

Magnetic memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to magnetic memory devices.

In accordance with the high speed and low power consumption of electronic devices, semiconductor memory devices embedded therein are also required to have fast read/write operations and low operating voltages. A magnetic memory device has been proposed as a semiconductor memory device as a way to satisfy these requirements. The magnetic memory device can operate at a high speed and can have non-volatile characteristics, so it is in the spotlight as a next-generation memory device.

The magnetic memory device may include a magnetic tunnel junction (MTJ). The magnetic tunnel junction may include two magnetic materials and a tunnel barrier layer interposed therebetween. The resistance value of the magnetic tunnel junction may vary according to the magnetization directions of the two magnetic materials. For example, when the magnetization directions of two magnetic materials are antiparallel to each other, the magnetic tunnel junction may have a relatively large resistance value, and when the magnetization directions of the two magnetic materials are parallel to each other, the magnetic tunnel junction may have a relatively small resistance value. there is. The magnetic memory device can write/read data by using the difference in resistance values.

As the electronic industry is highly developed, the demand for high integration and/or low power consumption of the magnetic memory device is increasing. Therefore, many studies are being conducted to satisfy these needs.

An object of the present invention is to provide a highly integrated magnetic memory device.

Another technical object of the present invention is to provide a magnetic memory device having excellent reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A plurality of word lines of a magnetic memory device according to embodiments of the present invention for achieving the above object; a plurality of bit lines intersecting the word lines, the plurality of bit lines including first bit lines, and second bit lines spaced apart from the first bit lines in an extension direction of the word lines; a plurality of first memory cells connected between the word lines crossing each other and the first bit lines, each of the first memory cells including a first memory element and a first selection element connected thereto; and a plurality of second memory cells connected between the word lines and the second bit lines crossing each other, each of the second memory cells comprising a second memory element and a second selection element connected thereto; Each of the first and second memory devices includes a magnetic tunnel junction including a pinned layer, a free layer, and a tunnel barrier layer therebetween, and the magnetic tunnel junction of some of the second memory devices is the tunnel barrier The layer may be dielectric breakdown and have an irreversible resistance state.

According to an embodiment, the first memory cells may constitute a normal memory cell array that can be programmed a plurality of times, and the second memory cells may constitute an OTP memory cell array that can be programmed only once.

In an embodiment, the magnetic tunnel junction of the first memory elements is a first magnetic tunnel junction, the magnetic tunnel junction of the part of the second memory elements is a second magnetic tunnel junction, and the second memory The magnetic tunnel junction of the remaining elements becomes a third magnetic tunnel junction, wherein the first magnetic tunnel junction has a first resistance value corresponding to first data or a second resistance corresponding to second data through a plurality of programming. value, the second magnetic tunnel junction has a third resistance value corresponding to the first data through one programming, and the third magnetic tunnel junction has a third resistance value corresponding to the second data through one programming. It has 4 resistance values, and the first to fourth resistance values may be different from each other.

In example embodiments, the first resistance value is smaller than the second resistance value, the third resistance value is smaller than the first resistance value, and the fourth resistance value is between the first and second resistance values. can be

According to an embodiment, some of the first memory cells are used as first reference cells for a read operation of the first memory cells, and some of the second memory cells are used as first reference cells for a read operation of the second memory cells. 2 It can be used as a reference cell.

According to an embodiment, the first reference cell may be configured such that a pair of first memory cells of the first memory cells are connected in parallel through one first bit line.

In an embodiment, the first magnetic tunnel junction of any one of the pair of first memory cells is programmed to have the first resistance value, and the first magnetic tunnel junction of the other one has the second resistance value. can be programmed to have

According to an embodiment, the second reference cell may include any one of the second memory cells including the second magnetic tunnel junction.

In an embodiment, the display device further includes a control resistor electrically connected to the second reference cell, wherein the reference resistance for the read operation of the second memory cells is the second magnetic tunnel junction constituting the second reference cell. A sum of the third resistance value of and the fifth resistance value of the control resistor may be used.

According to an embodiment, the sum value may be between the third resistance value and the fourth resistance value.

According to an embodiment, a first peripheral circuit electrically connected to the first memory cells through the first bit lines; and a second peripheral circuit electrically connected to the second memory cells through the second bit lines, wherein the second peripheral circuit is at least driven under a higher voltage than a first peripheral transistor of the first peripheral circuit. One second peripheral transistor may be included.

In an embodiment, the first peripheral transistor includes a first peripheral gate dielectric layer and a first peripheral gate electrode, and the second peripheral transistor includes a second peripheral gate dielectric layer and a second peripheral gate electrode, A thickness of the second peripheral gate dielectric layer may be greater than a thickness of the first gate dielectric layer.

According to an embodiment, the second peripheral gate electrode may have a second width greater than a first width of the first peripheral gate electrode.

A memory cell array including a magnetic memory device, a normal cell array, and an OTP cell array according to embodiments of the present invention for achieving the above object; a first peripheral circuit electrically connected to the normal cell array through first bit lines; and a second peripheral circuit electrically connected to the OTP cell array through second bit lines, wherein the normal cell array includes a plurality of first memories including a first magnetic tunnel junction and a first selection transistor connected thereto cells, wherein the OTP cell array includes a plurality of second memory cells including a second magnetic tunnel junction and a second selection transistor connected thereto, wherein some of the second magnetic tunnel junctions have an irreversible resistance state can have

According to an embodiment, the part of the second magnetic tunnel junctions is a first sub-magnetic tunnel junction, and another part of the second magnetic tunnel junctions is a second sub-magnetic tunnel junction, and the first magnetic tunnel The junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming, and the first sub-magnetic tunnel junction corresponds to the first data through a single programming has a third resistance value, the second sub-magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming, the first resistance value is smaller than the second resistance value, and The third resistance value may be smaller than the first resistance value, and the fourth resistance value may be between the first and second resistance values.

According to an embodiment, some of the first memory cells are used as first reference cells for a read operation of the first memory cells, and any one selected from among the second memory cells including the first sub-magnetic tunnel junction may be used as a second reference cell for a read operation of the second memory cells.

According to an embodiment, the second peripheral circuit includes a control resistor electrically connected to the second reference cell, and the reference resistance for the read operation of the second memory cells is the reference resistance constituting the second reference cell. A sum of the third resistance value of the second magnetic tunnel junction and the fifth resistance value of the control resistor may be used.

According to an embodiment, some of the first memory cells are used as first reference cells for the read operation of the first memory cells, and the OTP cell array is a second reference cell for the read operation of the second memory cells. The second reference cell may further include a third selection transistor connected to one of the second bit lines without passing through the variable resistance element.

In an embodiment, the second peripheral circuit includes a control resistor electrically connected to the second reference cell, and the reference resistance for the read operation of the second memory cells is a fifth resistance value of the control resistor. Available.

According to an embodiment, the first peripheral circuit includes at least one first peripheral transistor, and the second peripheral circuit includes at least one second peripheral transistor, wherein the second peripheral transistor includes the first peripheral transistor. It can be driven under a higher voltage than a transistor.

According to embodiments of the present invention, a magnetic memory device optimized for high integration can be provided by implementing a part of the memory cell array as an OTP cell array without forming the OTP memory device in a separate area. In addition, by shorting the magnetic tunnel junction, which is a memory element of the memory cells, it is possible to easily implement OTP memory cells. In addition, by separately forming a reference cell and a peripheral circuit for the OTP memory cells, write and read operations of the OTP memory cells may be optimized. As a result, it is possible to provide a magnetic memory device with improved reliability.

1 is a block diagram of a magnetic memory device according to embodiments of the present invention.
2 is an exemplary circuit diagram for explaining a configuration of a magnetic memory device according to embodiments of the present invention.
3 is an exemplary diagram illustrating a first memory cell according to embodiments of the present invention.
4A and 4B are conceptual views for explaining a first magnetic tunnel junction according to embodiments of the present invention.
5A and 5B are exemplary diagrams illustrating a first sub-cell and a second sub-cell, respectively, according to embodiments of the present invention.
6 is a simplified circuit diagram illustrating a read operation of a first memory cell according to embodiments of the present invention.
7A and 7B are simplified circuit diagrams for explaining a read operation of a second memory cell according to embodiments of the present invention.
8A is an exemplary plan view illustrating a magnetic memory device according to embodiments of the present invention. 8B is a cross-sectional view taken along lines AA' and B-B' of FIG. 8A, and FIG. 8C is a cross-sectional view taken along lines C-C', D-D', and E-E' of FIG. 8A.
9A is an exemplary plan view illustrating a magnetic memory device according to embodiments of the present invention. 9B is a cross-sectional view taken along lines AA' and B-B' of FIG. 9A, and FIG. 9C is a cross-sectional view taken along lines C-C', D-D', and E-E' of FIG. 9A.

In order to fully understand the configuration and effect of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various forms and various modifications may be made. However, it is provided so that the disclosure of the present invention is complete through the description of the present embodiments, and to fully inform those of ordinary skill in the art to which the present invention belongs, the scope of the invention.

In this specification, when a component is referred to as being on another component, it means that it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, the thickness of the components is exaggerated for effective description of the technical content. Parts indicated with like reference numerals throughout the specification indicate like elements.

Embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention. In various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Embodiments described and illustrated herein also include complementary embodiments thereof.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, the terms 'comprises' and/or 'comprising' do not exclude the presence or addition of one or more other components.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram of a magnetic memory device according to embodiments of the present invention.

Referring to FIG. 1 , a magnetic memory device may include a memory cell array 10 for storing data input from the outside, and a peripheral circuit for controlling the memory cell array 10 . The memory cell array 10 may include a normal cell array 10a and an OTP cell array 10b (One Time Programmable Cell Array). That is, a part of the memory cell array 10 may be embodied as the normal cell array 10a, and another part of the memory cell array 10 may be embodied as the OTP cell array 10b. The peripheral circuit may include a row decoder 20 , a column selection circuit 30 , a read/write circuit 40 , and a control logic 50 .

Each of the normal cell array 10a and the OTP cell array 10b may include a plurality of memory cells including at least one memory element and at least one selection element. The memory cells of the normal cell array 10a may be programmed a plurality of times, whereas the memory cells of the OTP cell array 10b may be programmed only once. Memory cells of the normal cell array 10a and the OTP cell array 10b may be connected to word lines and bit lines. For convenience of description below, the memory cells of the normal cell array 10a may be referred to as normal memory cells, and the memory cells of the OTP cell array 10b may be referred to as OTP memory cells. In addition, bit lines connected to the memory cells of the normal cell array 10a may be referred to as first bit lines, and bit lines connected to the memory cells of the OTP cell array 10b may be referred to as second bit lines. there is.

The row decoder 20 may be connected to the normal cell array 10a and the OTP cell array 10b through word lines. The row decoder 20 may select one of the plurality of word lines by decoding an externally input address.

Each of the column selection circuit 30 and the read/write circuit 40 may be divided into two regions corresponding to the normal cell array 10a and the OTP cell array 10b. That is, the column selection circuit 30 may include a first column selection circuit 30a electrically connected to normal memory cells, and a second column selection circuit 30b electrically connected to OTP memory cells. Similarly, the read/write circuit 40 may include a first read/write circuit 40a electrically connected to the normal memory cells, and a second read/write circuit 40b electrically connected to the OTP memory cells. can

In detail, the first column selection circuit 30a is connected to the normal cell array 10a through first bit lines, and may select one of the plurality of first bit lines by decoding an externally input address. The first bit line selected by the first column selection circuit 30a may be connected to the first read/write circuit 40a. The second column selection circuit 30b is connected to the OTP cell array 10b through second bit lines, and may select one of the plurality of second bit lines by decoding an externally input address. The second bit line selected by the second column selection circuit 30b may be connected to the second read/write circuit 40b.

The first read/write circuit 40a may provide a bit line bias for accessing the selected normal memory cell according to the control of the control logic 50 . The first read/write circuit 40a may provide a bit line voltage to a selected bit line to write or read input data to or from a normal memory cell. The first read/write circuit 40a may include a first write driver and a first sense amplifier. The second read/write circuit 40b may provide a bit line bias for accessing the selected OTP memory cell according to the control of the control logic 50 . The second read/write circuit 40b may provide a bit line voltage to a selected bit line to write or read input data to or from the OTP memory cell. The second read/write circuit 40b may include a second write driver and a second sense amplifier.

The control logic 50 may output control signals for controlling the magnetic memory device according to an externally provided command signal. Control signals output from the control logic 50 may control the read/write circuit 40 .

2 is an exemplary circuit diagram for explaining a configuration of a magnetic memory device according to embodiments of the present invention.

Referring to FIG. 2 , the magnetic memory device may include a plurality of word lines WL, bit lines, a memory cell array 10 , a first peripheral circuit PC1 , and a second peripheral circuit PC2 . . The memory cell array 10 may include a first memory cell array 10a and a second memory cell array 10b sequentially arranged in the first direction D1 . The first memory cell array 10a may correspond to the normal cell array 10a of FIG. 1 , and the second memory cell array 10b may correspond to the OTP cell array 10b of FIG. 1 . Here, the first direction D1 may be defined as a direction in which the word lines WL extend. In addition, the second direction D2 crossing the first direction D1 may be defined as a direction in which the bit lines extend. The word lines WL may extend in the first direction D1 to cross the first memory cell array 10a and the second memory cell array 10b. The bit lines may cross the word lines WL. The bit lines may include first bit lines BL1 connected to the first memory cell array 10a and second bit lines BL2 connected to the second memory cell array 10b.

The first memory cell array 10a may include first memory cells MC1 . The first memory cells MC1 may be arranged two-dimensionally or three-dimensionally. The first memory cells MC1 may be connected between the word lines WL and the first bit lines BL1 crossing each other. The first memory cells MC1 may correspond to the normal memory cells described with reference to FIG. 1 . The second memory cell array 10b may include second memory cells MC2 . The second memory cells MC2 may be arranged two-dimensionally or three-dimensionally. The second memory cells MC2 may be connected between the word lines WL and the second bit lines BL2 crossing each other. The second memory cells MC2 may correspond to the OTP memory cells described with reference to FIG. 1 . A plurality of first memory cells MC1 and a plurality of second memory cells MC2 may be connected to one word line WL. In addition, the plurality of first memory cells MC1 constituting one column may be connected to different word lines WL and may share one first bit line BL1 . Similarly, the plurality of second memory cells MC2 constituting one column may be connected to different word lines WL and may share one second bit line BL2 .

Each of the first memory cells MC1 may include a first memory element ME1 and a first selection element SE1 . The first memory device ME1 may be connected between the first bit line BL1 and the first selection device SE1 , and the first selection device SE1 includes the first memory device ME1 and the word line WL. can be connected between The first memory element ME1 may be a variable resistance element that can be switched to two resistance states by an applied electric pulse. According to an embodiment, the first memory device ME1 may be formed to have a thin film structure in which its electrical resistance can be changed by using a spin transfer process by a current passing therethrough. The first memory device ME1 may have a thin film structure configured to exhibit magnetoresistance characteristics, and may include at least one ferromagnetic material and/or at least one antiferromagnetic material. Specifically, the first memory device ME1 may be a magnetic memory device including a magnetic tunnel junction.

The first selection device SE1 may be configured to selectively control the flow of charges passing through the first memory device ME1 . For example, the first selection element SE1 may be one of a diode, a PNP bipolar transistor, an NPM bipolar transistor, an NMOS field effect transistor, and a PMOS field effect transistor. When the first selection element SE1 is configured as a three-terminal bipolar transistor or a MOS field effect transistor, an additional wire (eg, a source line, not shown) may be connected to the first selection element SE1 . The first memory cell MC1 will be described in detail with reference to FIGS. 3, 4A, and 4B .

The second memory cells MC2 may be implemented in substantially the same/similar shape to the first memory cells MC1 . For example, each of the second memory cells MC2 includes a second memory device ME2 implemented in a magnetic tunnel junction shape, and a second selection device SE2 implemented in the same shape as the first selection device SE1 . can do. In this case, some of the second memory elements ME2 of the second memory cells MC2 may be in a blown state, and some of the second memory elements ME2 may be in a non-blown state. blown) state. Here, the blown state means a state in which two magnetic layers constituting the magnetic tunnel junction are short-circuited. This may be achieved by applying a break down voltage to both ends of the two magnetic layers to dielectrically break the tunnel barrier layer between the magnetic layers through one programming operation. The resistance of the blown magnetic tunnel junction is irreversible and may have a value smaller than the resistance of the non-blown magnetic tunnel junction. Consequently, as some of the second memory cells MC2 have the second memory elements ME2 in an irreversible resistance state, the second memory cell array 10b may be implemented as an OTP memory device. For convenience of description, the second memory cell MC2 including the non-blowing second memory device ME2 is referred to as the first sub-cell MC2_1 ( FIG. 5A ), and the blown second memory device ME2 is referred to as the first sub-cell MC2_1 ( FIG. 5A ). ) including the second memory cell MC2 is referred to as a second sub-cell MC2_2 ( FIG. 5B ). The first and second sub-cells MC2_1 and MC2_2 will be described in detail with reference to FIGS. 5A and 5B .

Each of the first memory cells MC1 may be connected to the first peripheral circuit PC1 by each of the first bit lines BL1 , and each of the second memory cells MC2 may be connected to the second bit lines BL1 . BL2) may be connected to the second peripheral circuit PC2. The first peripheral circuit PC1 may include the first column selection circuit 30a and/or the first read/write circuit 40a of FIG. 1 . The second peripheral circuit PC2 may include the second column selection circuit 30b and/or the second read/write circuit 40b of FIG. 1 . According to embodiments of the present invention, the first peripheral transistors constituting the first peripheral circuit PC1 may be implemented as low voltage transistors. In addition, at least some of the second peripheral transistors constituting the second peripheral circuit PC2 may be implemented as high voltage transistors driven under a higher voltage than that of the first peripheral transistors. This may be to apply a stable high voltage to some of the second memory cells MC2 implemented as the second sub-cells MC2_2 .

Meanwhile, some of the first memory cells MC1 may be used as reference cells for the read operation of the first memory cell array 10a. Similarly, for a read operation of the second memory cell array 10b, some of the second memory cells MC2 may be used as reference cells. For convenience of description, a reference cell of the first memory cell array 10a is referred to as a first reference cell RC1 (refer to FIG. 6 ), and a reference cell of the second memory cell array 10b is referred to as a second reference cell ( RC2, see Fig. 7a).

According to an embodiment, the first reference cell RC1 may be connected between two word lines WL adjacent to each other and one first bit line BL1 crossing them. That is, the first reference cell RC1 may include a pair of first memory elements connected in parallel and first selection elements SE1 connected in series to each of the pair of first memory elements. However, embodiments of the present invention are not limited thereto. A plurality of first reference cells RC1 may be provided. For example, the plurality of first reference cells RC1 may be respectively connected between two word lines WL adjacent to each other and first bit lines BL1 crossing them. The first reference cell RC1 will be described again with reference to FIG. 6 .

The second reference cell RC2 may be implemented as a second sub-cell MC2_2. That is, the second reference cell RC2 may include the blown second memory device ME2 . A plurality of second reference cells RC2 may be provided, and the plurality of second reference cells RC2 may be arranged in the second direction D2 to form one column. The plurality of second reference cells RC2 constituting one column may be connected to different word lines WL and may share one second bit line BL2 . The second reference cell RC2 will be described again with reference to FIG. 7A .

3 is an exemplary diagram illustrating a first memory cell according to embodiments of the present invention.

Referring to FIG. 3 , the first memory cell MC1 may include a first magnetic tunnel junction MTJ1 as a memory device and a first selection transistor SE1 as a selection device. A gate electrode of the first selection transistor SE1 is connected to a corresponding word line WL, a source of the first selection transistor SE1 is connected to a corresponding source line SL, and the first selection transistor A drain of SE1 may be connected to a corresponding first bit line BL1 through a first magnetic tunnel junction MTJ1.

The first magnetic tunnel junction MTJ1 may include a pinned layer PL, a free layer FL, and a tunnel barrier layer TBL interposed therebetween. The pinned layer PL has a magnetization direction fixed in one direction, and the free layer FL has a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the pinned layer PL. The electrical resistance of the first magnetic tunnel junction MTJ1 may vary according to the magnetization directions of the pinned layer PL and the free layer FL. When the magnetization directions of the pinned layer PL and the free layer FL are parallel in the first magnetic tunnel junction MTJ1 , the first magnetic tunnel junction MTJ1 is in a low resistance state (eg, first resistance value = R1 ). ), and '0' corresponding to the first data may be written. On the other hand, when the magnetization directions of the pinned layer PL and the free layer FL in the first magnetic tunnel junction MTJ1 are antiparallel, the first magnetic tunnel junction MTJ1 is in a high resistance state (eg, the second magnetic tunnel junction MTJ1). resistance = R2), and '1' corresponding to the second data may be written. For example, the first resistance value R1 may be about 10 kiloohms (kΩ), and the second resistance value R2 may be about 40 kiloohms (kΩ).

For a write operation of the first memory cell MC1 , a turn-on voltage may be applied to the word line WL and a first write voltage may be applied to both ends of the first magnetic tunnel junction MTJ1 . A first write current Iw1 or a second write current Iw2 may flow in the first magnetic tunnel junction MTJ1 according to the direction of the first write voltage applied to the first magnetic tunnel junction MTJ1 . The first write current Iw1 is provided to the first magnetic tunnel junction MTJ1 in a direction flowing from the first bit line BL1 to the source line SL, and the second write current Iw2 is the source line SL. may be provided to the first magnetic tunnel junction MTJ1 in a direction flowing from the to the first bit line BL1 to the first bit line BL1 . The magnetization direction of the free layer FL may be changed by a spin torque of electrons in the above-described write current. As a result, the first memory cell MC1 may store the first resistance value R1 or the second resistance value R2 according to the direction of the write current flowing through the first magnetic tunnel junction MTJ1 , so that a plurality of It may be implemented as a programmable normal memory cell.

In the present embodiment, it is illustrated that the free layer FL is connected to the first bit line BL1 and the pinned layer PL is connected to the first selection transistor SE1, but embodiments of the present invention are not limited thereto. it is not According to another embodiment, unlike illustrated, the pinned layer PL may be connected to the first bit line BL1 , and the free layer FL may be connected to the first selection transistor SE1 . Hereinafter, the first magnetic tunnel junction MTJ1 will be described in detail with reference to FIGS. 4A and 4B .

4A and 4B are conceptual views for explaining a first magnetic tunnel junction according to embodiments of the present invention.

The electrical resistance of the first magnetic tunnel junction MTJ1 may depend on the magnetization directions of the pinned layer PL and the free layer FL. For example, the electrical resistance of the first magnetic tunnel junction MTJ1 may be much greater when the magnetization directions of the pinned layer PL and the free layer FL are antiparallel than when they are parallel. there is. As a result, the electrical resistance of the first magnetic tunnel junction MTJ1 can be adjusted by changing the magnetization direction of the free layer FL, which can be used as a data storage principle in the magnetic memory device according to the present invention.

Referring to FIG. 4A , the pinned layer PL and the free layer FL may be magnetic layers for forming a horizontal magnetization structure in which a magnetization direction is substantially parallel to a top surface of the tunnel barrier layer TBL. In this case, the pinned layer PL may include a layer including an anti-ferromagnetic material and a layer including a ferromagnetic material. According to an embodiment, the layer including the antiferromagnetic material may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. According to another embodiment, the layer including the antiferromagnetic material may include at least one selected from among rare metals. The rare metal may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). Meanwhile, the layer including the ferromagnetic material may include at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12. may include

The free layer FL may include a material having a changeable magnetization direction. The free layer FL may include a ferromagnetic material. For example, the free layer FL may include at least one selected from FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. may include

The free layer FL may include a plurality of layers. For example, it may include a layer including a plurality of ferromagnetic materials and a layer including a non-magnetic material interposed between the layers. In this case, the layers including the ferromagnetic material and the layer including the nonmagnetic material may constitute a synthetic antiferromagnetic layer. The synthetic antiferromagnetic layer can reduce the critical current density of the magnetic memory device and improve the thermal stability.

The tunnel barrier layer TBL is an oxide of magnesium (Mg), an oxide of titanium (Ti), aluminum (Al), an oxide of magnesium-zinc (MgZn), an oxide of magnesium-boron (MgB), and a nitride of titanium (Ti). and at least one of a nitride of vanadium (V). For example, the tunnel barrier layer TBL may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier layer TBL may include a plurality of layers. The tunnel barrier layer (TBL) may be formed using a chemical vapor deposition (CVD) process.

Referring to FIG. 4B , the pinned layer PL and the free layer FL may have a perpendicular magnetization structure in which the magnetization direction is substantially perpendicular to the upper surface of the tunnel barrier layer TBL. In this case, each of the pinned layer PL and the free layer FL may include at least one of a material having an L10 crystal structure, a material having a dense hexagonal lattice, and an amorphous Rare-Earth Transition Metal (RE-TM) alloy. there is. For example, each of the pinned layer PL and the free layer FL may be at least one of materials having an L10 crystal structure including Fe50Pt50, Fe50Pd50, Co50Pt50, Co50Pd50, and Fe50Ni50. In contrast, each of the pinned layer PL and the free layer FL has a dense hexagonal lattice of 10 to 45 at. A cobalt-platinum (CoPt) disordered alloy having a platinum (Pt) content of % or a Co3Pt ordered alloy may be included. In contrast, each of the pinned layer PL and the free layer FL includes at least one selected from iron (Fe), cobalt (Co) and nickel (Ni) and rare earth metals terbium (Tb), dysprosium (Dy) and gadolinium ( It may include at least one selected from an amorphous RE-TM alloy including at least one of Gd).

The pinned layer PL and the free layer FL may include a material having an interface perpendicular magnetic anisotropy. Interfacial perpendicular magnetic anisotropy refers to a phenomenon in which a magnetic layer having intrinsic horizontal magnetization characteristics has a perpendicular magnetization direction due to the influence from the interface with another layer adjacent thereto. Here, the intrinsic horizontal magnetization characteristic means a characteristic in which the magnetic layer has a magnetization direction parallel to its widest surface when there is no external factor. For example, when the magnetic layer having intrinsic horizontal magnetization characteristics is formed on the substrate and there is no external factor, the magnetization direction of the magnetic layer may be substantially parallel to the upper surface of the substrate.

For example, each of the pinned layer PL and the free layer FL may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). In addition, each of the pinned layer PL and the free layer FL is boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), At least one of a non-magnetic material including silver (Ag), gold (Au), copper (Cu), carbon (C), and nitrogen (N) may be further included. For example, each of the pinned layer PL and the free layer FL includes CoFe or NiFe, but may further include boron (B). In addition, in order to lower the saturation magnetization amount of the pinned layer PL and the free layer FL, each of the pinned layer PL and the free layer FL is titanium (Ti), aluminum (Al), silicon (Si), or magnesium. It may further include at least one of (Mg), tantalum (Ta), and silicon (Si).

5A and 5B are exemplary diagrams illustrating a first sub-cell and a second sub-cell, respectively, according to embodiments of the present invention.

Referring to FIG. 5A , the first sub-cell MC2-1 may include a second magnetic tunnel junction MTJ2 as a memory device and a second selection transistor SE2 as a selection device. The gate electrode of the second selection transistor SE2 is connected to the corresponding word line WL, the source of the second selection transistor SE2 is connected to the corresponding source line SL, and the second selection transistor A drain of SE2 may be connected to a corresponding second bit line BL2 through a second magnetic tunnel junction MTJ2. The second magnetic tunnel junction MTJ2 may include a pinned layer PLa, a free layer FLa, and a tunnel barrier layer TBLa interposed therebetween. The pinned layer PLa, the free layer FLa, and the tunnel barrier layer TBLa of the second magnetic tunnel junction MTJ2 are the pinned layer PL, the free layer FL and the tunnel barrier layer of the first magnetic tunnel junction MTJ1, respectively. It may be formed of the same material as the layer TBL. That is, the second magnetic tunnel junction MTJ2 may be implemented in the form of a variable resistance element that can be switched to two resistance states by an applied electric pulse.

Referring to FIG. 5B , the second sub-cell MC2 - 2 may be substantially the same as the first sub-cell MC2-1 except for including the third magnetic tunnel junction MTJ3 as a memory device. The third magnetic tunnel junction MTJ3 may include a pinned layer PLa, a free layer FLa, and a tunnel barrier layer TBLa1 interposed therebetween. The pinned layer PLa, the free layer FLa, and the tunnel barrier layer TBLa1 of the third magnetic tunnel junction MTJ3 are the pinned layer PL, the free layer FL and the tunnel barrier layer of the first magnetic tunnel junction MTJ1, respectively. The layer TBL (or the pinned layer PLa, the free layer FLa, and the tunnel barrier layer TBLa of the second magnetic tunnel junction MTJ2) may be formed of the same material. In this case, the tunnel barrier layer TBLa1 may be in a dielectric breakdown state. Accordingly, the third magnetic tunnel junction MTJ3 may have an irreversible resistance state.

Through one programming for the implementation of the OTP memory cell, a second write voltage is applied to a portion of the second memory cells MC2 implemented as the first sub-cell MC2-1, and the second sub-cell MC2- A third write voltage may be applied to other portions of the second memory cells MC2 implemented as 2). That is, a second write voltage may be applied to both ends of the second magnetic tunnel junction MTJ2 , and a third write voltage may be applied to both ends of the third magnetic tunnel junction MTJ3 . Here, the second write voltage has substantially the same magnitude as the first write voltage applied to both ends of the first magnetic tunnel junction MTJ1 , while the third write voltage may be much greater than the first write voltage. That is, the third write voltage may be greater than or equal to the breakdown voltage of the third magnetic tunnel junction MTJ3 . Accordingly, the tunnel barrier layer TBLa1 of the third self-junction tunnel MTJ3 may be destroyed. Meanwhile, programming of the second memory cells MC2 may be performed before packaging of the magnetic memory device. In this case, the second magnetic tunnel junction MTJ2 may have a first resistance value R1 or It may be programmed to have a second resistance value R2. However, the resistance value of the second magnetic tunnel junction MTJ2 may be changed during the packaging process of the magnetic memory device and/or the subsequent high temperature process. Accordingly, the final resistance value of the second magnetic tunnel junction MTJ2 may have a third resistance value R3 between the first and second resistance values R1 and R2.

As a result, through the aforementioned one-time programming, the second magnetic tunnel junction MTJ2 has the third resistance value R3, and '1' corresponding to the second data may be written. Here, the third resistance value R3 may be between the first resistance value R1 and the second resistance value R2 . Meanwhile, the blown third magnetic tunnel junction MTJ3 has a fourth resistance value R4 that is much smaller than the first resistance value R1, and '0' corresponding to the first data may be written. For example, the fourth resistance value R4 may be 1 kiloohm (kΩ) or less.

6 is a simplified circuit diagram illustrating a read operation of a first memory cell according to embodiments of the present invention.

The data value of the selected first memory cell MC1 may be read by determining a difference between the resistance of the selected first memory cell MC1 and the resistance of the first reference cell RC1 . Referring to FIG. 6 , the first reference cell RC1 is, for example, a pair of first magnetic tunnel junctions MTJ1 connected in parallel and a first magnetic tunnel junction connected in series to each of the pair of first magnetic tunnel junctions MTJ1 . One select transistor SE1 may be included. Although not shown, the source lines SL connected to each of the first selection transistors SE1 of the first reference cell RC1 may be electrically connected to each other. According to another embodiment, a source of each of the first selection transistors SE1 of the first reference cell RC1 may share one source line SL.

Before the read operation is performed, the first magnetic tunnel junctions MTJ1 of the first reference cell RC1 may be programmed to have different resistance values. That is, one of the first magnetic tunnel junctions MTJ1 of the first reference cell RC1 may be programmed to have a first resistance value R1 and the other to have a second resistance value R2 . Accordingly, the resistance of the first reference cell RC1 to which the pair of first magnetic tunnel junctions MTJ1 is connected in parallel is in the middle ((R1+) of the sum of the first resistance value R1 and the second resistance value R2. It may have a value of about R2)/2). Meanwhile, data corresponding to the first resistance value R1 or the second resistance value R2 may be stored in the selected first memory cell MC1 through separate programming.

To perform the read operation, a turn-on voltage may be applied to the word line WL of the selected first memory cell MC1 , and may be applied to the first magnetic tunnel junction MTJ1 of the selected first memory cell MC1 . A first read current Ir1 may flow. In addition, a turn-on voltage may be applied to the word line WL of the first reference cell RC1 , and second read currents MTJ1 may be applied to the first magnetic tunnel junctions MTJ1 of the first reference cell RC1. Ir2_1, Ir2_2) can flow. The first sense amplifier SA1 has a resistance value of the first memory cell MC1 by the first read current Ir1 and a resistance value of the first reference cell RC1 by the second read currents Ir2_1 and Ir2_2 By detecting and amplifying the difference between , it is possible to determine what data is stored in the selected first memory cell MC1 . Meanwhile, the first sense amplifier SA1 may be a part of the first peripheral circuit PC1 described with reference to FIG. 2 .

In the first magnetic tunnel junction MTJ1 of the selected first memory cell MC1 , when the magnetization direction of the free layer FL is parallel to the magnetization direction of the pinned layer PL, the selected first memory cell The data of (MC1) may be read as, for example, '0'. In contrast, when the magnetization direction of the free layer FL is disposed anti-parallel to the magnetization direction of the pinned layer PL in the first magnetic tunnel junction MTJ1 of the selected first memory cell MC1 . , data of the selected first memory cell MC1 may be read as, for example, '1'.

7A and 7B are simplified circuit diagrams for explaining a read operation of a second memory cell according to embodiments of the present invention.

Referring to FIG. 7A , the second reference cell RC2 is selected from among the second sub-cells MC2_2 . Accordingly, the second reference cell RC2 may include the third magnetic tunnel junction MTJ3 having the fourth resistance value R4 . Meanwhile, the selected second memory cell MC2 may be the first sub-cell MC2-1 or the second sub-cell MC2-2. That is, the selected second memory cell MC2 may include a second magnetic tunnel junction MTJ2 or a third magnetic tunnel junction MTJ3 . Accordingly, the selected second memory cell MC2 may have a resistance corresponding to the third resistance value R3 or the fourth resistance value R4 .

The data value of the selected second memory cell MC2 may be read by determining a difference between the resistance of the selected second memory cell MC2 and the resistance of the second reference cell RC2 . In this case, in order to increase the sensing margin, the resistance of the second reference cell RC2 is required to have a value between the fourth resistance value R4 and the third resistance value R3 . According to an embodiment of the present invention, in order to easily achieve such a request, a second bit line BL2 connected to the second reference cell RC2 and a second sensing resistance of the second reference cell RC2 are A control resistor Rct may be provided between the sense amplifier SA2. That is, the third magnetic tunnel junction MTJ3 of the second reference cell RC2 and the control resistor Rct may be electrically connected. As a result, the resistance of the second reference cell RC2 sensed by the read operation is the value of the fourth resistance R4 of the third magnetic tunnel junction MTJ3 and the fifth resistance R5 of the control resistor Rct. It may be a summed value. The above summed value may be between the fourth resistance value R4 and the third resistance value R3 (eg, about 7 kiloohms (kΩ)). can be Meanwhile, the second sense amplifier SA2 and the control resistor Rct may be a part of the second peripheral circuit PC2 described with reference to FIG. 2 .

To perform the read operation, a turn-on voltage may be applied to the word line WL of the selected second memory cell MC2 , and the second memory device (ie, the second memory cell) of the selected second memory cell MC2 . A third read current Ir3 may flow in the magnetic tunnel junction MJT or the third magnetic tunnel junction MTJ3. In addition, a turn-on voltage may be applied to the word line WL of the second reference cell RC2 and the third magnetic tunnel junction MTJ3 and the control resistor Rct of the second reference cell RC2. 4 A read current (Ir4) can flow. The second sense amplifier SA2 detects a difference between the resistance of the second memory cell MC2 by the third read current Ir3 and the resistance of the second reference cell RC2 by the fourth read current Ir4, and By amplifying, it is possible to determine what data is stored in the selected second memory cell MC2 .

When the selected second memory cell MC2 is the first sub-cell MC2-1, data of the selected second memory cell MC2 may be read, for example, as '1'. Alternatively, when the selected second memory cell MC2 is the second sub-cell MC2 - 2 , data of the selected second memory cell MC2 may be read, for example, as '0'.

According to another embodiment, the second reference cell RC2 may be implemented in a form different from that shown in FIG. 7A . For example, the second reference cell RC2 may not include the third magnetic tunnel junction MTJ3 as a memory device.

Referring to FIG. 7B , the second reference cell RC2 may include only the second selection transistor SE2 . In this case, the fifth resistance value R5 of the control resistor Rct may be between the fourth resistance value R4 and the third resistance value R3 . For example, the fifth resistance value R5 of the control resistor Rct may be about 7 kiloohms (kΩ). To perform the read operation, a turn-on voltage may be applied to the word line WL of the selected second memory cell MC2 , and the second memory device (ie, the second memory cell) of the selected second memory cell MC2 . A third read current Ir3 may flow in the magnetic tunnel junction MJT or the third magnetic tunnel junction MTJ3. In addition, a turn-on voltage may be applied to the word line WL of the second reference cell RC2 , and the control resistor Rct of the second reference cell RC2 and the second reference cell RC2 connected to the second reference cell RC2 . A fourth read current Ir4 may flow between the second bit line BL and the source line SL. The second sense amplifier SA2 detects a difference between the resistance of the second memory cell MC2 by the third read current Ir3 and the resistance of the second reference cell RC2 by the fourth read current Ir4, and By amplifying, it is possible to determine what data is stored in the selected second memory cell MC2 .

OTP memory devices are being used to repair semiconductor devices. For example, the semiconductor device may be tested and characteristics of the semiconductor device according to the test result are stored in an OTP memory inside the semiconductor device, and the semiconductor device operates based on the information stored in the OTP memory, thereby preventing malfunction of the semiconductor device. In addition, the OTP memory device may store other information for controlling the semiconductor device. For example, semiconductor devices may have different characteristics while passing through a semiconductor manufacturing process, and the OTP memory device may store information about the different characteristics of the semiconductor device, and the information may be used to control a memory array.

According to embodiments of the present invention, a magnetic memory device optimized for high integration can be provided by implementing a part of the memory cell array as an OTP cell array without forming the OTP memory device as described above in a separate area. . In addition, by shorting the magnetic tunnel junction, which is a memory element of the memory cells, it is possible to easily implement OTP memory cells. In addition, by separately forming a reference cell and a peripheral circuit for the OTP memory cells, write and read operations of the OTP memory cells may be optimized. As a result, it is possible to provide a magnetic memory device with improved reliability.

8A is an exemplary plan view illustrating a magnetic memory device according to embodiments of the present invention. 8B is a cross-sectional view taken along lines A-A' and B-B' of FIG. 8A, and FIG. 8C is a cross-sectional view taken along lines C-C', D-D', and E-E' of FIG. 8A.

8A to 8C , a substrate 100 including a cell array region CR and a peripheral circuit region PR is provided. The substrate 100 may be a silicon substrate, a germanium substrate, and/or a silicon-germanium substrate, but embodiments of the present invention are not limited thereto. The cell array region CR may include a first cell array region CR1 and a second cell array region CR2 . The first cell array region CR1 may be a region in which the first memory cell array 10a of FIG. 2 is formed, and the second cell array region CR2 is formed in the second memory cell array 10b of FIG. 2 . It may be an area where The peripheral circuit region PR may include a first peripheral circuit region PR1 and a second peripheral circuit region PR2 . The first peripheral circuit region PR1 may be a region in which the first peripheral circuit PC1 described with reference to FIG. 2 is formed, and the second peripheral circuit region PR2 is the second peripheral circuit region PR2 described with reference to FIG. 2 . PC2) may be formed.

Device isolation patterns 102 may be provided in the substrate 100 . The device isolation patterns 102 of the first and second cell array regions CR1 and CR2 may define active line patterns ALP. The device isolation patterns 102 and the active line patterns ALP of the first and second cell array regions CR1 and CR2 may be arranged in the first direction D1 . In a plan view, the device isolation patterns 102 and the active line patterns ALP of the first and second cell array regions CR1 and CR2 are disposed in a second direction D2 crossing the first direction D1 . can be extended side by side. The active line patterns ALP may be doped with a dopant of the first conductivity type.

The device isolation patterns 102 of the first and second peripheral circuit regions PR1 and PR2 may define a first peripheral active part PA1 and a second peripheral active part PA2, respectively. The first peripheral active part PA1 and the second peripheral active part PA2 may be doped with a dopant of a first conductivity type or a second conductivity type different from the first conductivity type.

In the first and second cell array regions CR1 and CR2 , isolation recess regions 104 may cross the active line patterns ALP and the device isolation patterns 102 . In a plan view, the isolation recess regions 104 may have groove shapes extending side by side in the first direction D1 . The isolation recess regions 104 may divide each of the active line patterns ALP into cell active portions CA. The cell active portions CA may be a portion of the active line patterns ALP positioned between a pair of adjacent isolation recess regions 104 . That is, the cell active portions CA may be defined by a pair of device isolation patterns 102 adjacent to each other and a pair of isolation recess regions 104 adjacent to each other. In a plan view, the cell active parts CA may be two-dimensionally arranged in the first direction D1 and the second direction D2 .

At least one gate recess region 103 may cross the cell active portions CA arranged in the first direction D1 . The gate recess region 103 may extend parallel to the isolation recess regions 104 . According to an embodiment, a pair of gate recess regions 103 may cross the cell active portions CA arranged in the first direction D1 . In this case, a pair of cell transistors may be respectively formed in the cell active parts CA. The cell transistor of the first cell array region CR1 may correspond to the first selection transistor SE1 described with reference to FIGS. 2 and 3 , and the cell transistor of the second cell array region CR2 is shown in FIGS. 2 and 3 . It may correspond to the second selection transistor SE2 described with reference to FIGS. 5A and 5B .

The height of the lower surfaces of the gate recess regions 103 may be substantially the same as the height of the lower surfaces of the isolation recess regions 104 . The height of the lower surfaces of the gate and isolation recess regions 103 and 104 may be higher than the height of the lower surfaces of the device isolation patterns 102 of the first and second cell array regions CR1 and CR2 .

A word line WL may be disposed in each of the gate recess regions 103 . A cell gate dielectric layer 105 may be disposed between the word line WL and inner surfaces of each of the gate recess regions 103 . Due to the shape of the gate recess regions 103 , the word line WL may have a line shape extending in the first direction D1 . The cell transistor may include a word line WL and a channel region recessed by the gate recess region 103 .

An isolation line IL may be disposed within each isolation recessed region 104 . An isolation gate dielectric layer 106 may be disposed between the isolation line IL and inner surfaces of the isolation recess regions 104 . The isolation line IL may also have a line shape extending in the first direction D1 .

Cell capping patterns 108 may be respectively disposed on the word and isolation lines WL and IL. The cell capping patterns 108 may be disposed in the gate and isolation recess regions 103 and 104 . Top surfaces of the cell capping patterns 108 may be substantially coplanar with the top surface of the substrate 100 .

During operation of the magnetic memory device, an isolation voltage may be applied to the isolation line IL. The isolation voltage may prevent a channel from forming under the inner surface of the isolation recess regions 104 . That is, the isolation channel region under the isolation line IL may be turned off by the isolation voltage. Accordingly, the cell active portions CA divided from the active line patterns ALP may be electrically isolated from each other. For example, when the active line patterns ALP are doped with a P-type dopant, the isolation voltage may be a ground voltage or a negative voltage.

The word line WL may be, for example, a semiconductor material doped with a dopant (eg, doped silicon, etc.), a metal (eg, tungsten, aluminum, titanium and/or tantalum), or a conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.). and/or tungsten nitride) and a metal-semiconductor compound (eg, metal silicide). According to an embodiment, the isolation line IL may be formed of the same material as the word line WL. The cell gate dielectric layer 105 and the isolation gate dielectric layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, and/or a high dielectric material (eg, an insulating metal oxide such as hafnium oxide, aluminum oxide, etc.). The cell capping patterns 108 may include silicon oxide, silicon nitride, and/or silicon oxynitride.

The first impurity region 111 may be disposed in the cell active portions CA of one side of the word line WL, and the second impurity region 112 may be disposed in the cell active portion CA of the other side of the word line WL. CA). According to an embodiment, the first impurity region 111 may be disposed between a pair of word lines WL, and the second impurity regions 112 may be disposed between the word line WL and the isolation line IL. may be respectively disposed in the cell active units CA of . Accordingly, the pair of cell transistors formed in the cell active portions CA may share the first impurity region 111 . The first and second impurity regions 111 and 112 may correspond to source/drain regions of the cell transistor. The first and second impurity regions 111 and 112 may be doped with dopants of a second conductivity type different from the first conductivity type. One of the dopant of the first conductivity type and the dopant of the second conductivity type may be an N-type dopant, and the other may be a P-type dopant.

A first peripheral gate dielectric layer 114a, a first peripheral gate electrode 116a, and a first peripheral capping pattern 118a are sequentially stacked on the first peripheral active part PA1 of the first peripheral circuit region PR1. can The first peripheral source/drain regions 120a may be respectively disposed in the first peripheral active portion PA1 on both sides of the first peripheral gate electrode 116a. First peripheral gate spacers 122a may be disposed on both sidewalls of the first peripheral gate electrode 116a. The first peripheral source/drain regions 120a may be doped with dopants of a conductivity type different from that of the dopants of the first peripheral active portion PA1 . Unlike the cell transistor, the first peripheral transistor including the first peripheral gate electrode 116a may include a planar channel region. That is, the first peripheral transistor may be a planar transistor. However, embodiments of the present invention are not limited thereto. According to another embodiment, the first peripheral gate electrode 116a may have an electrode structure of a Fin-FET device. The first peripheral transistor may be a PMOS transistor or an NMOS transistor.

On the second peripheral active portion PA2 of the second peripheral circuit PC2 region PR1 , the second peripheral gate dielectric layer 114b , the second peripheral gate electrode 116b and the second peripheral capping pattern 118b are formed They can be stacked sequentially. The second peripheral source/drain regions 120b may be respectively disposed in the second peripheral active part PA2 on both sides of the second peripheral gate electrode 116b. Second peripheral gate spacers 122b may be disposed on both sidewalls of the second peripheral gate electrode 116b. The second peripheral source/drain regions 120b may be doped with dopants of a conductivity type different from that of the dopants of the second peripheral active portion PA2 . The second peripheral transistor including the second peripheral gate electrode 116b may be implemented in substantially the same shape as the first peripheral transistor. That is, the second peripheral transistor may be a planar transistor. However, embodiments of the present invention are not limited thereto. According to another embodiment, the second peripheral gate electrode 116b may have an electrode structure of a fin-FET device. The second peripheral transistor may be a PMOS transistor or an NMOS transistor.

According to the concept of the present invention, the first peripheral transistor may be a low voltage transistor operating under a low voltage, and the second peripheral transistor may be a high voltage transistor operating under a high voltage. The channel of the second peripheral transistor may be formed to be longer than the channel of the first peripheral transistor to withstand a high voltage (ie, to prevent punch-through between the second peripheral source/drain regions 120b). That is, the second width W2 of the second peripheral gate electrode 116b may be greater than the first width W1 of the first peripheral gate electrode 116a. In addition, the gate dielectric film of the second peripheral transistor may withstand a high voltage (that is, to withstand a high potential difference between the second peripheral gate electrode 116b and the second peripheral source/drain regions 120b) of the first periphery. It may be formed to be thicker than the gate dielectric layer of the transistor. That is, the second thickness t2 of the second peripheral gate dielectric layer 114b may be greater than the first thickness t1 of the first peripheral gate dielectric layer 114a.

Each of the first and second peripheral gate dielectric layers 114a and 114b may include, for example, silicon oxide and/or a high dielectric material (eg, an insulating metal oxide such as hafnium oxide or aluminum oxide). According to an embodiment, the first peripheral gate dielectric layer 114a may be formed of a relatively thin silicon oxide layer, and the second peripheral gate dielectric layer 114b may be formed of a relatively thick silicon oxide layer. According to another embodiment, the first peripheral gate dielectric layer 114a may be formed as a single layer including a high-k material, and the second peripheral gate dielectric layer 114b may be formed as a double layer in which a silicon oxide layer and a high-k layer are stacked. . Each of the first and second peripheral gate electrodes 114 is formed of a semiconductor material doped with a dopant (eg, doped silicon, etc.), a metal (eg, tungsten, aluminum, titanium and/or tantalum), a conductive metal nitride (ex). , titanium nitride, tantalum nitride, and/or tungsten nitride) and a metal-semiconductor compound (eg, metal silicide). Each of the first and second peripheral capping patterns 116 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. Each of the first and second peripheral gate spacers 122b may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride.

The resistance pattern 124 may be disposed on the device isolation pattern 102 of the second peripheral circuit region PR2 . The resistance pattern 124 may include a semiconductor material. For example, the resistance pattern 124 may include silicon, germanium, or silicon-germanium. According to an embodiment, the semiconductor material included in the resistance pattern 124 may be in a polycrystalline state. The resistance pattern 124 may be doped with a dopant (eg, an n-type dopant or a p-type dopant) for controlling the resistivity of the resistance pattern 124 . According to an embodiment, the entire resistance pattern 124 may be substantially uniformly doped with a dopant for controlling resistivity. Alternatively, the resist pattern 124 may be partially doped. Insulation spacers 126 may be disposed on sidewalls of the resistance pattern 124 , and a protective insulating layer may be disposed on an upper surface of the resistance pattern 124 . Each of the insulating spacers 126 and the protective insulating pattern 128 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. The resistance pattern 124 may correspond to the control resistance Rct described with reference to FIGS. 7A and 7B .

The first interlayer dielectric layer 130 may be disposed on the entire surface of the substrate 100 . The first interlayer dielectric layer 130 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. The source lines SL may penetrate the first interlayer dielectric layer 130 of the first and second cell array regions CR1 and CR2 to make contact with the substrate 100 . The source lines SL may extend in the first direction D1 . The source lines SL may be electrically connected to the first impurity regions 11 arranged in the first direction D1 . Top surfaces of the source lines SL may be substantially coplanar with the top surfaces of the first interlayer dielectric layer 130 of the first and second cell array regions CR1 and CR2. The source lines SL may include a semiconductor material doped with a dopant (eg, doped silicon, etc.), a metal (eg, tungsten, aluminum, titanium and/or tantalum), a conductive metal nitride (eg, titanium nitride, tantalum nitride and/or tantalum). or tungsten nitride) and a metal-semiconductor compound (eg, metal silicide). The first interlayer dielectric layer 130 of the first peripheral circuit region PR1 may cover the first peripheral transistor, and the first interlayer dielectric layer 130 of the second peripheral circuit region PR2 includes the second peripheral transistor and the resistance pattern. (124) can be covered.

The second interlayer dielectric layer 140 may be disposed on the entire surface of the first interlayer dielectric layer 130 . The second interlayer dielectric layer 140 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. In the first cell array region CR1 , the first contact plugs 142 may continuously penetrate the second interlayer dielectric layer 140 and the first interlayer dielectric layer 130 . The first contact plugs 142 may be electrically connected to the second impurity regions 112 of the first cell array region CR1 , respectively. In the second cell array region CR2 , the second contact plugs 144 may continuously penetrate the second interlayer dielectric layer 140 and the first interlayer dielectric layer 130 . The second contact plugs 144 may be electrically connected to the second impurity regions 112 of the second cell array region CR2 , respectively. The first and second contact plugs 144 may be formed of the same conductive material as the source line. Top surfaces of the first and second contact plugs 144 may be substantially coplanar with the top surface of the second interlayer insulating layer 140 .

The first memory devices ME1 may be disposed on the second interlayer insulating layer 140 of the first cell array region CR1 . Each of the first memory elements ME1 may vertically overlap the first contact plugs 142 . That is, the first memory elements ME1 may be respectively connected to the first contact plugs 142 . The first memory elements ME1 may be electrically connected to the second impurity regions 112 of the first cell array region CR1 through the first contact plugs 142 . The first memory elements ME1 may be two-dimensionally arranged in the first direction D1 and the second direction D2 in a plan view. The first memory elements ME1 may correspond to the first memory elements ME1 described with reference to FIGS. 2, 3, 4A, 4B, and 7A. That is, each of the first memory elements ME1 may include a first magnetic tunnel junction MTJ1 . Since the first magnetic tunnel junction MTJ1 is the same as described above, a detailed description thereof will be omitted. A portion of the first memory elements ME1 may constitute the aforementioned first memory cells MC1 , and other portions may constitute the aforementioned first reference cells RC1 . In addition, each of the first memory elements ME1 may further include a first lower electrode BE1 and a first upper electrode TE1 . The first magnetic tunnel junction MTJ1 is disposed between the first lower electrode BE1 and the first upper electrode TE1 . That is, the first lower electrode BE1 is disposed between the first contact plug 142 and the first magnetic tunnel junction MTJ1 , and the first upper electrode TE1 is disposed on the first magnetic tunnel junction MTJ1 . can be Each of the first lower electrode BE1 and the first upper electrode TE1 includes a conductive metal nitride (eg, titanium nitride, tantalum nitride), a transition metal (eg, titanium, tantalum, etc.), and a rare earth metal (eg, , ruthenium, platinum, etc.) may include at least one.

The second memory devices ME2 may be disposed on the second interlayer insulating layer 140 of the second cell array region CR2 . Each of the second memory elements ME2 may vertically overlap the second contact plugs 144 . That is, the second memory elements ME2 may be respectively connected to the second contact plugs 144 . The second memory elements ME2 may be electrically connected to the second impurity regions 112 of the second cell array region CR2 through the second contact plugs 144 . The second memory elements ME2 may be two-dimensionally arranged in the first direction D1 and the second direction D2 in a plan view. The second memory elements ME2 may correspond to FIGS. 2, 5A, 5B, and 7A and the second memory elements ME2 described with reference to FIGS. That is, some of the second memory elements ME2 may include the second magnetic tunnel junction MTJ2 , and others may include the third magnetic tunnel junction MTJ3 . Since the second and third magnetic tunnel junctions MTJ2 and MTJ3 are the same as described above, a detailed description thereof will be omitted. A portion of the second memory elements ME2 may constitute the aforementioned second memory cells MC2 , and other portions may constitute the aforementioned second reference cells RC2 . In addition, each of the second memory elements ME2 may further include a second lower electrode BE2 and a second upper electrode TE2 . Each of the second and third magnetic tunnel junctions MTJ2 and MTJ3 is disposed between the second lower electrode BE2 and the second upper electrode TE2 . The second lower electrode BE2 and the second upper electrode TE2 may include the same material as the first lower electrode BE1 and the second upper electrode TE2, respectively.

A third interlayer insulating layer 150 may be disposed on the entire surface of the second interlayer insulating layer 140 . The third interlayer insulating layer 150 of the first and second cell array regions CR1 and CR2 may contact sidewalls of the first and second memory devices ME1 and ME2 . In addition, the third interlayer insulating layer 150 of the first and second cell array regions CR1 and CR2 may expose top surfaces of the first and second memory devices ME1 and ME2 . The third interlayer dielectric layer 150 may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride.

In the first peripheral circuit PC1 region, the first peripheral plugs 152 may penetrate the first to third interlayer dielectric layers 130 , 140 , and 150 to contact the substrate 100 . The first peripheral plugs 152 may be electrically connected to the first peripheral source/drain regions 120a. In the second peripheral circuit region PR2 , the second peripheral plugs 154 may penetrate the first to third interlayer dielectric layers 130 , 140 , and 150 to contact the substrate 100 . The second peripheral plugs 154 may be electrically connected to the second peripheral source/drain regions 120b. The third peripheral plug 156 passes through the first to third interlayer dielectric layers 130 , 140 , 150 and the protective insulating pattern 128 of the second peripheral circuit region PR2 to electrically connect to the resistance pattern 124 . can be connected. The first to third peripheral plugs 152 , 154 , and 156 may include the same conductive material as the source lines SL.

The first bit lines BL1 may be disposed on the third interlayer insulating layer 150 of the first cell array region CR1 . The first bit lines BL1 may extend in the second direction D2 . Each of the first bit lines BL1 may be in common contact with the plurality of first memory devices ME1 arranged in the second direction D2 . The second bit lines BL2 may be disposed on the third interlayer insulating layer 150 of the second cell array region CR2 . The second bit lines BL2 may extend in the second direction D2 . Each of the second bit lines BL2 may be in common contact with the plurality of second memory devices ME2 arranged in the second direction D2 . The first and second bit lines BL1 and BL2 may include a metal such as copper or aluminum.

The first wirings L1 may be disposed on the third interlayer insulating layer 150 of the first peripheral circuit PC1 region. The first wirings L1 may be electrically connected to the first peripheral plugs 152 , respectively. The second interconnections L2 may be disposed on the third interlayer insulating layer 150 of the second peripheral circuit region PR2 . The second wirings L2 may be electrically connected to the second peripheral plugs 154 , respectively. The third wiring L3 may be disposed on the third interlayer insulating layer 150 of the second peripheral circuit region PR2 . The third wiring L3 may be electrically connected to the third peripheral plug 156 . The first to third interconnections L1 , L2 , and L3 may include the same material as the first and second bit lines BL1 and BL2 .

The cell transistor and the first memory device ME1 of the first cell array region CR1 are connected to the first peripheral source/drain regions of the first peripheral transistor through the first bit line BL1 and the first wiring L1. 120a) and may be electrically connected. The cell transistor and the second memory device ME2 of the second cell array region CR2 are connected to the second peripheral source/drain regions ( ) of the second peripheral transistor through the second bit line BL2 and the second wiring L2 . 120b) and may be electrically connected. In addition, the cell transistor and the second memory device ME2 of the second cell array region CR2 constituting the second reference cell RC2 have a resistance pattern through the second bit line BL2 and the third wiring L3 . It may be electrically connected to (124).

9A is an exemplary plan view illustrating a magnetic memory device according to embodiments of the present invention. 9B is a cross-sectional view taken along lines A-A' and B-B' of FIG. 9A, and FIG. 9C is a cross-sectional view taken along lines C-C', D-D', and E-E' of FIG. 9A. The magnetic memory device of FIGS. 9A to 9C may be the same as the magnetic memory device of FIGS. 8A to 8C , except that some of the second memory elements ME2 are replaced with third contact plugs 146 . . For simplicity of description, descriptions of overlapping components will be omitted.

Referring to FIGS. 9A to 9C , some of the second impurity regions 112 of the second cell array region CR2 may pass through the third interlayer insulating layers 130 , 140 , and 150 . It may be connected to the second bit line BL2 through the contact plug 146 . That is, some of the cell transistors of the second cell array region CR2 may be electrically connected to the second bit line BL2 without passing through the second memory device ME2 . Cell transistors electrically connected to the second bit line BL2 through the third contact plug 146 may correspond to the second reference cells RC2 described with reference to FIG. 7B . As illustrated, a plurality of second reference cells RC2 may be provided, and the plurality of second reference cells RC2 are arranged along the second direction D2 to form one second bit line BL2. can share

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

a plurality of word lines;
a plurality of bit lines intersecting the word lines, the plurality of bit lines comprising first bit lines, and second bit lines spaced apart from the first bit lines in an extension direction of the word lines;
a plurality of first memory cells connected between the word lines crossing each other and the first bit lines, each of the first memory cells including a first memory element and a first selection element connected thereto; and
a plurality of second memory cells connected between the word lines crossing each other and the second bit lines, each of the second memory cells comprising a second memory element and a second selection element connected thereto;
Each of the first and second memory devices includes a magnetic tunnel junction including a pinned layer, a free layer, and a tunnel barrier layer therebetween, and the magnetic tunnel junction of some of the second memory devices is the tunnel barrier The layer is insulated and has an irreversible resistance state,
The magnetic tunnel junction of the first memory elements is a first magnetic tunnel junction;
the magnetic tunnel junction of the part of the second memory elements is a second magnetic tunnel junction;
The first magnetic tunnel junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming;
The second magnetic tunnel junction has a third resistance value corresponding to the first data through one programming,
The first to third resistance values are different from each other. The method of claim 1,
The first memory cells constitute a normal memory cell array that can be programmed a plurality of times,
The second memory cells constitute an OTP memory cell array that can be programmed only once. The method of claim 1,
The magnetic tunnel junction of the remaining of the second memory elements is a third magnetic tunnel junction,
The third magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming,
The first to fourth resistance values are different from each other. 4. The method of claim 3,
The first resistance value is smaller than the second resistance value,
the third resistance value is smaller than the first resistance value;
The fourth resistance value is between the first and second resistance values. 4. The method of claim 3,
Some of the first memory cells are used as first reference cells for a read operation of the first memory cells,
Some of the second memory cells are used as second reference cells for a read operation of the second memory cells. 6. The method of claim 5,
The first reference cell is a magnetic memory device configured such that a pair of first memory cells of the first memory cells are connected in parallel through one first bit line. 7. The method of claim 6,
One of the first magnetic tunnel junctions of the pair of first memory cells is programmed to have the first resistance value, and the other first magnetic tunnel junction is programmed to have the second resistance value. Device. 6. The method of claim 5,
The second reference cell is a magnetic memory device including any one of the second memory cells including the second magnetic tunnel junction. 9. The method of claim 8,
Further comprising a control resistor electrically connected to the second reference cell,
The reference resistance for the read operation of the second memory cells is a magnetic memory device using the sum of the third resistance value of the second magnetic tunnel junction constituting the second reference cell and the fifth resistance value of the control resistor. . 10. The method of claim 9,
The sum value is between the third resistance value and the fourth resistance value. The method of claim 1,
a first peripheral circuit electrically connected to the first memory cells through the first bit lines; and
Further comprising a second peripheral circuit electrically connected to the second memory cells through the second bit lines,
and the second peripheral circuit includes at least one second peripheral transistor driven under a higher voltage than the first peripheral transistor of the first peripheral circuit. 12. The method of claim 11,
the first peripheral transistor includes a first peripheral gate dielectric layer and a first peripheral gate electrode;
The second peripheral transistor includes a second peripheral gate dielectric layer and a second peripheral gate electrode, wherein a thickness of the second peripheral gate dielectric layer is greater than a thickness of the first peripheral gate dielectric layer. 13. The method of claim 12,
The second peripheral gate electrode has a second width greater than a first width of the first peripheral gate electrode. a memory cell array including a normal cell array and an OTP cell array;
a first peripheral circuit electrically connected to the normal cell array through first bit lines; and
a second peripheral circuit electrically connected to the OTP cell array through second bit lines;
The normal cell array includes a plurality of first memory cells including a first magnetic tunnel junction and a first selection transistor connected thereto;
The OTP cell array includes a plurality of second memory cells including a second magnetic tunnel junction and a second selection transistor connected thereto;
Some of the second magnetic tunnel junctions have an irreversible resistance state,
the first peripheral circuit includes at least one first peripheral transistor,
the second peripheral circuit includes at least one second peripheral transistor,
and the second peripheral transistor is driven under a higher voltage than that of the first peripheral transistor. 15. The method of claim 14,
Some of the second magnetic tunnel junctions are first sub magnetic tunnel junctions,
Another part of the second magnetic tunnel junctions is a second sub magnetic tunnel junction,
The first magnetic tunnel junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming;
The first sub-magnetic tunnel junction has a third resistance value corresponding to the first data through one programming,
the second sub-magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming;
The first resistance value is smaller than the second resistance value, the third resistance value is smaller than the first resistance value, and the fourth resistance value is between the first and second resistance values. 16. The method of claim 15,
Some of the first memory cells are used as first reference cells for a read operation of the first memory cells,
One selected one of the second memory cells including the first sub-magnetic tunnel junction is used as a second reference cell for a read operation of the second memory cells. 17. The method of claim 16,
wherein the second peripheral circuit includes a control resistor electrically connected to the second reference cell;
The reference resistance for the read operation of the second memory cells is a magnetic memory device using the sum of the third resistance value of the second magnetic tunnel junction constituting the second reference cell and the fifth resistance value of the control resistor. . 16. The method of claim 15,
Some of the first memory cells are used as first reference cells for a read operation of the first memory cells,
The OTP cell array further includes a second reference cell for a read operation of the second memory cells,
and the second reference cell includes a third selection transistor connected to one of the second bit lines without passing through a variable resistance element. 19. The method of claim 18,
wherein the second peripheral circuit includes a control resistor electrically connected to the second reference cell;
The reference resistance for the read operation of the second memory cells is a magnetic memory device using a fifth resistance value of the control resistance. delete

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