KR20170045081A - Magnetic memory device - Google Patents

Abstract

The present invention relates to a magnetic memory device, comprising: a plurality of first memory cells connected between word lines and first bit lines intersecting each other, each of the first memory cells having a first memory element and a first A plurality of second memory cells, each of the second memory cells including a first select element and being coupled between the word lines and the second bit lines crossing each other, Wherein each of the first and second memory elements comprises a magnetic tunnel junction comprising a pinned layer, a free layer and a tunnel barrier layer therebetween, and wherein the magnetic tunnel junction of some of the second memory elements, The junction provides a magnetic memory device in which the tunnel barrier layer is insulated and has an irreversible resistance state.

Description

Magnetic memory device < RTI ID = 0.0 >

The present invention relates to a semiconductor device, and more particularly to a magnetic memory device.

As the speed of electronic devices is reduced and the power consumption is lowered, a semiconductor memory device embedded therein is also required to have a fast read / write operation and a low operating voltage. A magnetic memory device has been proposed as a semiconductor memory device in order to meet these demands. The magnetic memory element can operate at a high speed and can have nonvolatile characteristics, and has been popular as a next generation memory element.

The magnetic storage element may include a magnetic tunnel junction (MTJ). The magnetic tunnel junction may include two magnetic bodies and a tunnel barrier layer interposed therebetween. The resistance value of the magnetic tunnel junction can be changed according to the magnetization directions of the two magnetic bodies. For example, if the magnetization directions of two magnetic bodies are antiparallel to each other, the magnetic tunnel junction can have a relatively large resistance value, and if the magnetization directions of the two magnetic bodies are parallel, the magnetic tunnel junction can have a relatively small resistance value have. Using the difference in resistance values, the magnetic storage element can write / read data.

As the electronics industry develops, demands for high integration and / or low power consumption of magnetic storage elements are intensifying. Therefore, many studies are under way to meet these demands.

SUMMARY OF THE INVENTION The present invention provides a highly integrated magnetic memory device.

Another object of the present invention is to provide a magnetic memory device having excellent reliability.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a magnetic memory device comprising: a plurality of word lines; A plurality of bit lines crossing the word lines, the plurality of bit lines comprising first bit lines and second bit lines spaced apart from the first bit lines in an extending direction of the word lines; A plurality of first memory cells coupled between the word lines and the first bit lines intersecting each other, each of the first memory cells including a first memory device and a first select device coupled thereto; And a plurality of second memory cells coupled between the word lines and the second bit lines intersecting each other, each of the second memory cells including a second memory device and a second select device coupled thereto, Wherein each of the first and second memory elements comprises a magnetic tunnel junction comprising a fixed layer, a free layer and a tunnel barrier layer therebetween, and wherein the magnetic tunnel junction of a portion of the second memory elements comprises a tunnel barrier The layer is insulated and can have an irreversible resistance state.

According to one embodiment, the first memory cells constitute a normal memory cell array which can be programmed a plurality of times, and the second memory cells constitute an OTP memory cell array which can be programmed only once.

According to one embodiment, the magnetic tunnel junction of the first memory devices is a first magnetic tunnel junction, the magnetic tunnel junction of the portion of the second memory devices is a second magnetic tunnel junction, Wherein the magnetic tunnel junction of the remaining of the elements is a third magnetic tunnel junction, the first magnetic tunnel junction having a first resistance value corresponding to the first data or a second resistance corresponding to the second data Wherein said second magnetic tunnel junction has a third resistance value corresponding to said first data through one programming and said third magnetic tunnel junction has a value corresponding to said second data through one programming, 4, and the first to fourth resistance values may be different from each other.

According to an embodiment, the first resistance value is smaller than the second resistance value, the third resistance value is smaller than the first resistance value, and the fourth resistance value is between the first and second resistance values Lt; / RTI >

According to an embodiment, a part of the first memory cells is used as a first reference cell for a read operation of the first memory cells, and a part of the second memory cells is used as a first reference cell for a read operation of the second memory cells. 2 reference cell.

According to one embodiment, the first reference cell may be configured such that a pair of first memory cells of the first memory cells are connected in parallel via one first bit line.

According to one embodiment, the first magnetic tunnel junction of any one of the pair of first memory cells is programmed to have the first resistance value, and the other one of the first magnetic tunnel junctions is programmed to have the second resistance value Lt; / RTI >

According to one embodiment, the second reference cell may be comprised of any of the second memory cells including the second magnetic tunnel junction.

According to an embodiment of the present invention, the memory cell further includes a control resistance electrically connected to the second reference cell, wherein a reference resistance for a read operation of the second memory cells includes a second magnetic tunnel junction The sum of the third resistance value of the control resistor and the fifth resistance value of the control resistor may be used.

According to one embodiment, the summed value may be between the third resistance value and the fourth resistance value.

According to an embodiment, a first peripheral circuit electrically connected to the first memory cells through the first bit lines; And a second peripheral circuit electrically connected to the second memory cells via the second bit lines, wherein the second peripheral circuit is at least a first transistor driven at a higher voltage than the first peripheral transistor of the first peripheral circuit And may include one second peripheral transistor.

According to one embodiment, the first peripheral transistor includes a first peripheral gate dielectric layer and a first peripheral gate electrode, and the second peripheral transistor includes a second peripheral gate dielectric layer and a second peripheral gate electrode, The thickness of the second peripheral gate dielectric layer may be greater than the thickness of the first gate dielectric layer.

According to one embodiment, the second peripheral gate electrode may have a second width greater than the first width of the first peripheral gate electrode.

A memory cell array including a magnetic memory device, a normal cell array, and an OTP cell array according to embodiments of the present invention; A first peripheral circuit electrically connected to the normal cell array through first bit lines; And a second peripheral circuit electrically connected to the OTP cell array through second bit lines, wherein the normal cell array comprises: a plurality of first memory cells including a first magnetic tunnel junction and a first select transistor connected thereto; Cells, wherein the OTP cell array includes a plurality of second memory cells, the second memory cells including a second magnetic tunnel junction and a second select transistor coupled thereto, wherein some of the second magnetic tunnel junctions are in an irreversible resistance state Lt; / RTI >

According to one embodiment, the portion of the second magnetic tunnel junctions is a first sub-magnetic tunnel junction and the other portion of the second magnetic tunnel junctions is a second sub-magnetic tunnel junction, The junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming, the first sub-magnetic tunnel junction corresponding to the first data through one programming Wherein the second sub-magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming, the first resistance value is smaller than the second resistance value, and the second resistance value is smaller than the second resistance value, The third resistance value may be less than the first resistance value, and the fourth resistance value may be between the first and second resistance values.

According to one embodiment, some of the first memory cells are used as a first reference cell for a read operation of the first memory cells, and a selected one of the second memory cells including the first sub- May be used as a second reference cell for a read operation of the second memory cells.

According to an embodiment of the present invention, the second peripheral circuit includes a control resistor electrically connected to the second reference cell, and a reference resistor for a read operation of the second memory cells may include a second reference cell, The sum of the third resistance value of the second magnetic tunnel junction and the fifth resistance value of the control resistance may be used.

According to one embodiment, some of the first memory cells are used as a first reference cell for a read operation of the first memory cells, and the OTP cell array is used as a second reference cell for a read operation of the second memory cells. And the second reference cell may include a third selection transistor connected to one of the second bit lines without passing through the variable resistance element.

According to one embodiment, the second peripheral circuit includes a control resistor electrically connected to the second reference cell, and a reference resistor for a read operation of the second memory cells may include a fifth resistor value of the control resistor Can be used.

According to one embodiment, the first peripheral circuit includes at least one first peripheral transistor, and the second peripheral circuit includes at least one second peripheral transistor, It can be driven at a higher voltage than the transistor.

According to the embodiments of the present invention, a part of the memory cell array is implemented as an OTP cell array without forming the OTP memory device in a separate area, so that a magnetic memory device optimized for high integration can be provided. In addition, by shorting the magnetic tunnel junction which is the memory element of the memory cells, it is possible to easily implement OTP memory cells. In addition, by separately forming reference cells and peripheral circuits for the OTP memory cells, the write and read operations of the OTP memory cells can be optimized. As a result, a magnetic memory device with improved reliability can be provided.

1 is a block diagram of a magnetic memory device in accordance with embodiments of the present invention.
2 is an exemplary circuit diagram for explaining a configuration of a magnetic memory device according to embodiments of the present invention.
3 is an exemplary diagram illustrating a first memory cell in accordance with embodiments of the present invention.
4A and 4B are conceptual diagrams illustrating a first magnetic tunnel junction according to embodiments of the present invention.
5A and 5B are exemplary diagrams illustrating a first sub-cell and a second sub-cell, respectively, in accordance with embodiments of the present invention.
6 is a simplified circuit diagram illustrating a read operation of a first memory cell according to embodiments of the present invention.
FIGS. 7A and 7B are simplified circuit diagrams illustrating a read operation of a second memory cell according to embodiments of the present invention.
8A is an exemplary top view showing a magnetic memory device according to embodiments of the present invention. 8B is a cross-sectional view taken along line AA 'and B-B' in FIG. 8A, and FIG. 8C is a cross-sectional view taken along line C-C ', D-D', and E-E 'in FIG. 8A.
9A is an exemplary top view showing a magnetic memory device according to embodiments of the present invention. FIG. 9B is a cross-sectional view taken along line AA 'and B-B' in FIG. 9A, and FIG. 9C is a cross-sectional view taken along line C-C ', D-D', and E-E 'in FIG. 9A.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a magnetic memory device in accordance with embodiments of the present invention.

Referring to FIG. 1, a magnetic memory device may include a memory cell array 10 for storing externally input data, and a peripheral circuit for controlling the memory cell array 10. The memory cell array 10 may include a normal cell array 10a and an OTP cell array 10b. That is, a part of the memory cell array 10 may be implemented as a normal cell array 10a and another part of the memory cell array 10 may be implemented as an OTP cell array 10b. The peripheral circuitry may include a row decoder 20, a column select circuit 30, a read / write circuit 40, and control logic 50.

Each of the normal cell array 10a and the OTP cell array 10b may be composed of a plurality of memory cells including at least one memory element and at least one selection element. The memory cells of the normal cell array 10a can be programmed a plurality of times while the memory cells of the OTP cell array 10b can be programmed only once. The memory cells of the normal cell array 10a and the OTP cell array 10b may be connected to word lines and bit lines. For convenience of description, the memory cells of the normal cell array 10a are referred to as normal memory cells, and the memory cells of the OTP cell array 10b may be referred to as OTP memory cells. In addition, the bit lines connected to the memory cells of the normal cell array 10a are referred to as first bit lines, and the bit lines connected to the memory cells of the OTP cell array 10b may be referred to as second bit lines have.

The row decoder 20 may be connected to the normal cell array 10a and the OTP cell array 10b through word lines. The row decoder 20 may decode an externally input address to select one of a plurality of word lines.

Each of the column selection circuit 30 and the read / write circuit 40 can be divided into two regions corresponding to the normal cell array 10a and the OTP cell array 10b. That is, the column selecting circuit 30 may include a first column selecting circuit 30a electrically connected to the normal memory cells, and a second column selecting circuit 30b electrically connected to the OTP memory cells. Similarly, the read / write circuit 40 includes a first read / write circuit 40a in electrical communication with the normal memory cells and a second read / write circuit 40b in electrical communication with the OTP memory cells .

In detail, the first column selection circuit 30a is connected to the normal cell array 10a through the first bit lines, and can decode an address input from the outside to select one of the plurality of first bit lines. The first bit line selected in the first column select circuit 30a may be coupled to the first read / write circuit 40a. The second column selection circuit 30b is connected to the OTP cell array 10b through the second bit lines and can decode an address input from the outside to select one of the plurality of second bit lines. The second bit line selected by the second column selection circuit 30b may be connected to the second read / write circuit 40b.

The first read / write circuit 40a may provide a bit line bias for accessing the selected normal memory cell under the control of the control logic 50. [ The first read / write circuit 40a may provide the bit line voltage to the selected bit line to write or read the input data to the normal memory cell. The first read / write circuit 40a may include a first write driver and a first sense amplifier. The second read / write circuit 40b may provide a bit line bias for accessing the selected OTP memory cell under the control of the control logic 50. [ The second read / write circuit 40b may provide the bit line voltage to the selected bit line to write or read the input data to the OTP memory cell. The second read / write circuit 40b may include a second write driver and a second sense amplifier.

The control logic 50 may output control signals for controlling the magnetic memory device in accordance with an externally provided command signal. The control signals output from the control logic 50 may control the read / write circuit 40.

2 is an exemplary circuit diagram for explaining a configuration of a magnetic memory device according to embodiments of the present invention.

2, a magnetic memory device may include a plurality of word lines WL, bit lines, a memory cell array 10, a first peripheral circuit PC1, and a second peripheral circuit PC2 . The memory cell array 10 may include a first memory cell array 10a and a second memory cell array 10b that are sequentially arranged along a first direction D1. The first memory cell array 10a may correspond to the normal cell array 10a of FIG. 1 and the second memory cell array 10b may correspond to the OTP cell array 10b of FIG. Here, the first direction D1 may be defined as a direction in which the word lines WL extend. A second direction D2 intersecting with the first direction D1 may be defined as a direction in which the bit lines extend. The word lines WL may extend in the first direction D1 to cross the first memory cell array 10a and the second memory cell array 10b. The bit lines may intersect the word lines WL. The bit lines may include first bit lines BL1 connected to the first memory cell array 10a and second bit lines BL2 connected to the second memory cell array 10b.

The first memory cell array 10a may include first memory cells MC1. The first memory cells MC1 may be arranged two-dimensionally or three-dimensionally. The first memory cells MC1 may be connected between the word lines WL and the first bit lines BL1 intersecting with each other. The first memory cells MC1 may correspond to the normal memory cells described with reference to FIG. The second memory cell array 10b may include second memory cells MC2. The second memory cells MC2 may be arranged two-dimensionally or three-dimensionally. The second memory cells MC2 may be connected between the word lines WL and the second bit lines BL2 which intersect with each other. The second memory cells MC2 may correspond to the OTP memory cells described with reference to FIG. A plurality of first memory cells MC1 and a plurality of second memory cells MC2 may be connected to one word line WL. The plurality of first memory cells MC1 constituting one column may be connected to different word lines WL and may share one first bit line BL1. Similarly, a plurality of second memory cells MC2 constituting one column may be connected to different word lines WL, and may share one second bit line BL2.

Each of the first memory cells MC1 may include a first memory element ME1 and a first select element SE1. The first memory element ME1 may be coupled between the first bit line BL1 and the first select element SE1 and the first select element SE1 may be coupled between the first memory element ME1 and the word line WL, Respectively. The first memory element ME1 may be a variable resistive element which can be switched into two resistance states by an applied electrical pulse. According to one embodiment, the first memory element ME1 may be formed to have a thin film structure whose electrical resistance can be changed using a spin transfer process by the current passing therethrough. The first memory device ME1 may have a thin film structure configured to exhibit magnetoresistance characteristics and may include at least one ferromagnetic material and / or at least one antiferromagnetic material. Specifically, the first memory element ME1 may be a magnetic storage element including a magnetic tunnel junction.

The first select element SE1 may be configured to selectively control the flow of charge through the first memory element ME1. For example, the first selection element SE1 may be one of a diode, a bipolar bipolar transistor, an entien bipolar transistor, an emmos field effect transistor, and a pmos field effect transistor. When the first selection element SE1 is composed of a bipolar transistor or a MOS field effect transistor which is a three-terminal element, an additional wiring (for example, a source line, not shown) may be connected to the first selection element SE1. The first memory cell MC1 will be described in detail with reference to FIGS. 3, 4A and 4B.

The second memory cells MC2 may be implemented in substantially the same or similar form as the first memory cells MC1. For example, each of the second memory cells MC2 includes a second memory element ME2 implemented in the form of a magnetic tunnel junction, and a second selection element SE2 implemented in the same form as the first selection element SE1 can do. At this time, a part of the second memory elements ME2 of the second memory cells MC2 may be in a blown state, and a part of the second memory elements ME2 may be in an un- blown state. Here, the blown state means that two magnetic layers constituting the magnetic tunnel junction are short-circuited to each other. This can be achieved by applying a breakdown voltage across the two magnetic layers through one programming operation to break down the tunnel barrier layer between the magnetic layers. The resistance of the blown magnetic tunnel junction is irreversible and may have a value less than the resistance of the unblown magnetic tunnel junction. Consequently, the second memory cell array 10b can be implemented as an OTP memory device, as some of the second memory cells MC2 have second memory elements ME2 in an irreversible resistance state. The second memory cell MC2 including the second memory device ME2 that is not blown is referred to as a first sub cell MC2_1 (Fig. 5A), and the second memory device ME2 ) Is referred to as a second sub-cell MC2_2 (FIG. 5B). The first and second sub-cells MC2_1 and MC2_2 will be described in detail with reference to FIGS. 5A and 5B.

Each of the first memory cells MC1 may be connected to the first peripheral circuit PC1 by each of the first bit lines BL1 and each of the second memory cells MC2 may be connected to the second bit lines BL1 BL2 to the second peripheral circuit PC2. The first peripheral circuit PC1 may include the first column select circuit 30a and / or the first read / write circuit 40a of Fig. The second peripheral circuit PC2 may include the second column select circuit 30b and / or the second read / write circuit 40b of Fig. According to embodiments of the present invention, the first peripheral transistors constituting the first peripheral circuit PC1 may be implemented as low-voltage transistors. At least a part of the second peripheral transistors constituting the second peripheral circuit PC2 may be implemented as a high-voltage transistor driven under a higher voltage than the first peripheral transistors. This may be for applying a stable high voltage to a part of the second memory cells MC2 implemented in the second sub-cell MC2_2.

Meanwhile, some of the first memory cells MC1 may be used as reference cells for the read operation of the first memory cell array 10a. Similarly, for the read operation of the second memory cell array 10b, some of the second memory cells MC2 may be used as reference cells. The reference cell of the first memory cell array 10a is referred to as a first reference cell RC1 (see FIG. 6) and the reference cell of the second memory cell array 10b is referred to as a second reference cell RC2, see Fig. 7A).

According to one embodiment, the first reference cell RC1 may be connected between two adjacent word lines WL and one first bit line BL1 intersecting them. That is, the first reference cell RC1 may include first select elements SE1 connected in series to a pair of first memory elements and a pair of first memory elements connected in parallel. However, the embodiments of the present invention are not limited thereto. A plurality of first reference cells RC1 may be provided. For example, the plurality of first reference cells RC1 may be connected between two adjacent word lines WL and the first bit lines BL1 intersecting the two word lines WL. The first reference cell RC1 will be described again with reference to FIG.

And the second reference cell RC2 may be implemented as a second sub-cell MC2_2. That is, the second reference cell RC2 may include the second memory element ME2 that has been blown. A plurality of second reference cells RC2 may be provided and a plurality of second reference cells RC2 may be arranged in a second direction D2 to form one row. The plurality of second reference cells RC2 forming one column may be connected to different word lines WL and may share one second bit line BL2. The second reference cell RC2 will be described again with reference to Fig. 7A.

3 is an exemplary diagram illustrating a first memory cell in accordance with embodiments of the present invention.

Referring to FIG. 3, the first memory cell MC1 may include a first magnetic tunnel junction MTJ1 as a memory element and a first selection transistor SE1 as a selection element. The gate electrode of the first selection transistor SE1 is connected to the corresponding word line WL and the source of the first selection transistor SE1 is connected to the corresponding source line SL, The drain of SE1 may be connected to the corresponding first bit line BL1 via a first magnetic tunnel junction MTJ1.

The first magnetic tunnel junction MTJ1 may include a pinned layer PL, a free layer FL, and a tunnel barrier layer TBL interposed therebetween. The pinned layer PL has a magnetization direction fixed in one direction and the free layer FL has a magnetization direction changeable so as to be parallel or antiparallel to the magnetization direction of the pinned layer PL. The electrical resistance of the first magnetic tunnel junction MTJ1 may vary depending on the magnetization directions of the pinned layer PL and the free layer FL. When the magnetization directions of the pinned layer PL and the free layer FL are parallel in the first magnetic tunnel junction MTJ1, the first magnetic tunnel junction MTJ1 has a low resistance state (for example, a first resistance value = R1 ), And '0' corresponding to the first data can be written. Alternatively, when the magnetization directions of the pinned layer PL and the free layer FL are antiparallel in the first magnetic tunnel junction MTJ1, the first magnetic tunnel junction MTJ1 has a high resistance state (for example, Resistance value = R2), and a '1' corresponding to the second data can be written. For example, the first resistance value Rl may be about 10 kilohms (k [Omega]) and the second resistance value R2 may be about 40 kilohms (k [Omega]).

For the write operation of the first memory cell MC1, a turn-on voltage may be applied to the word line WL, and a first write voltage may be applied to both ends of the first magnetic tunnel junction MTJ1. The first write current Iw1 or the second write current Iw2 may flow through the first magnetic tunnel junction MTJ1 in accordance with the direction of the first write voltage applied to the first magnetic tunnel junction MTJ1. The first write current Iw1 is supplied to the first magnetic tunnel junction MTJ1 in the direction from the first bit line BL1 to the source line SL and the second write current Iw2 is supplied to the source line SL, May be provided to the first magnetic tunnel junction MTJ1 in the direction from the first bit line BL1 to the first bit line BL1. The magnetization direction of the free layer FL can be changed by the spin torque of the electrons in the write current described above. As a result, the first memory cell MC1 can store the first resistance value R1 or the second resistance value R2 according to the direction of the write current flowing through the first magnetic tunnel junction MTJ1, And can be implemented as a programmable normal memory cell.

In the present embodiment, the free layer FL is connected to the first bit line BL1 and the pinned layer PL is connected to the first selection transistor SE1, however, the embodiments of the present invention are limited thereto It is not. According to another embodiment, unlike the illustrated embodiment, the pinned layer PL may be connected to the first bit line BL1 and the free layer FL may be connected to the first select transistor SE1. Hereinafter, the first magnetic tunnel junction MTJ1 will be described in detail with reference to Figs. 4A and 4B.

4A and 4B are conceptual diagrams illustrating a first magnetic tunnel junction according to embodiments of the present invention.

The electrical resistance of the first magnetic tunnel junction MTJ1 may depend on the magnetization directions of the pinned layer PL and the free layer FL. For example, the electrical resistance of the first magnetic tunnel junction MTJ1 may be much larger when antiparallel to the magnetization directions of the pinned layer PL and the free layer FL, have. As a result, the electrical resistance of the first magnetic tunnel junction MTJ1 can be adjusted by changing the magnetization direction of the free layer FL, which can be used as a data storage principle in the magnetic memory device according to the present invention.

Referring to FIG. 4A, the pinned layer PL and the free layer FL may be magnetic layers for forming a horizontal magnetization structure in which the magnetization direction is substantially parallel to the top surface of the tunnel barrier layer (TBL). In this case, the pinned layer PL may comprise a layer comprising an anti-ferromagnetic material and a layer comprising a ferromagnetic material. According to one embodiment, the layer comprising the antiferromagnetic material may comprise at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO and Cr. According to another embodiment, the layer comprising the antiferromagnetic material may comprise at least one selected from the precious metals. The rare metal may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au) or silver (Ag). At least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12 .

The free layer FL may comprise a material having a changeable magnetization direction. The free layer FL may comprise a ferromagnetic material. For example, the free layer FL may comprise at least one selected from FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12 . ≪ / RTI >

The free layer FL may be composed of a plurality of layers. As an example, it may comprise a layer comprising a plurality of ferromagnetic materials and a layer comprising a non-magnetic material interposed between the layers. In this case, the layers including the ferromagnetic material and the layer including the non-magnetic material may constitute a synthetic antiferromagnetic layer. The synthetic antiferromagnetic layer can reduce the critical current density of the magnetic memory element and improve the thermal stability.

The tunnel barrier layer (TBL) is made of an oxide of magnesium (Mg), an oxide of titanium (Ti), an oxide of aluminum (Al), an oxide of magnesium-zinc (MgZn), an oxide of magnesium- And a nitride of vanadium (V). As an example, the tunnel barrier layer (TBL) may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier layer (TBL) may comprise a plurality of layers. The tunnel barrier layer (TBL) may be formed using a chemical vapor deposition (CVD) process.

Referring to FIG. 4B, the pinned layer PL and the free layer FL may have a perpendicular magnetization structure in which the magnetization direction is substantially perpendicular to the top surface of the tunnel barrier layer (TBL). In this case, each of the pinned layer PL and the free layer FL may include at least one of a material having an L10 crystal structure, a material having a dense hexagonal lattice, and an amorphous RE-TM (Rare-Earth Transition Metal) have. In one example, each of the pinned layer PL and the free layer FL may be at least one of materials having an L10 crystal structure including Fe50Pt50, Fe50Pd50, Co50Pt50, Co50Pd50, and Fe50Ni50. Alternatively, each of the pinned layer (PL) and the free layer (FL) may have a thickness of 10 to 45 at. Platinum (CoPt) disordered alloy or a Co3Pt ordered alloy having a platinum (Pt) content in the range of 1 to 5%. Alternatively, each of the pinned layer PL and the free layer FL may comprise at least one selected from among iron (Fe), cobalt (Co) and nickel (Ni) and at least one selected from the group consisting of rare earth metals such as terbium (Tb), dysprosium (Dy) and gadolinium Gd). ≪ / RTI >

The pinned layer PL and the free layer FL may comprise a material having interface perpendicular magnetic anisotropy. The interface perpendicular magnetic anisotropy refers to a phenomenon in which a magnetic layer having an inherent horizontal magnetization property has a perpendicular magnetization direction due to an influence from an interface with another layer adjacent thereto. Herein, the inherent horizontal magnetization characteristic means a characteristic in which, when there is no external factor, the magnetic layer has a magnetization direction parallel to its widest surface. For example, when a magnetic layer having inherent horizontal magnetization characteristics is formed on a substrate and there are no external factors, the magnetization direction of the magnetic layer may be substantially parallel to the top surface of the substrate.

In one example, each of the pinned layer PL and the free layer FL may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). Each of the pinned layer PL and the free layer FL may be formed of at least one of boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta) Magnetic material including silver (Ag), gold (Au), copper (Cu), carbon (C), and nitrogen (N). In one example, each of the pinned layer PL and the free layer FL includes CoFe or NiFe, and may further include boron (B). In addition, in order to lower the saturation magnetization of the pinned layer PL and the free layer FL, each of the pinned layer PL and the free layer FL is made of titanium (Ti), aluminum (Al), silicon (Si) (Mg), tantalum (Ta), and silicon (Si).

5A and 5B are exemplary diagrams illustrating a first sub-cell and a second sub-cell, respectively, in accordance with embodiments of the present invention.

Referring to FIG. 5A, the first sub-cell MC2-1 may include a second magnetic tunnel junction MTJ2 as a memory element and a second selection transistor SE2 as a selection element. The gate electrode of the second selection transistor SE2 is connected to the corresponding word line WL and the source of the second selection transistor SE2 is connected to the corresponding source line SL, The drain of SE2 may be connected to the corresponding second bit line BL2 through a second magnetic tunnel junction MTJ2. The second magnetic tunnel junction MTJ2 may include a pinned layer PLa, a free layer FLa, and a tunnel barrier layer TBLa interposed therebetween. The pinned layer PLa, the free layer FLa and the tunnel barrier layer TBLa of the second magnetic tunnel junction MTJ2 are connected to the pinned layer PL of the first magnetic tunnel junction MTJ1, Layer (TBL). That is, the second magnetic tunnel junction MTJ2 can be realized in the form of a variable resistance element that can be switched to two resistance states by an applied electric pulse.

Referring to FIG. 5B, the second sub-cell MC2-2 may be substantially the same as the first sub-cell MC2-1 except that it includes a third magnetic tunnel junction MTJ3 as a memory element. The third magnetic tunnel junction MTJ3 may include a pinned layer PLa, a free layer FLa, and a tunnel barrier layer TBLa1 interposed therebetween. The pinned layer PLa, the free layer FLa and the tunnel barrier layer TBLa1 of the third magnetic tunnel junction MTJ3 are connected to the fixed layer PL of the first magnetic tunnel junction MTJ1, Layer may be formed of the same material as the layer TBL (or the pinned layer PLa, the free layer FLa and the tunnel barrier layer TBLa of the second magnetic tunnel junction MTJ2). At this time, the tunnel barrier layer TBLa1 may be in an insulated state. Accordingly, the third magnetic tunnel junction MTJ3 may have an irreversible resistance state.

OTP memory cell, a second write voltage is applied to a part of the second memory cells MC2 implemented by the first sub-cell MC2-1, and a second write voltage is applied to the second sub-cell MC2- 2 may be applied to another portion of the second memory cells MC2. That is, a second write voltage may be applied to both ends of the second magnetic tunnel junction MTJ2, and a third write voltage may be applied to both ends of the third magnetic tunnel junction MTJ3. Here, the second write voltage may be substantially the same magnitude as the first write voltage applied across the first magnetic tunnel junction (MTJ1), while the third write voltage may be much larger than the first write voltage. That is, the third write voltage may be greater than the break down voltage of the third magnetic tunnel junction MTJ3. As a result, the tunnel barrier layer TBLa1 of the third magnetic junction tunnel MTJ3 can be destroyed. On the other hand, programming of the second memory cells MC2 can be performed before packaging of the magnetic memory device. At this time, the second magnetic tunnel junction MTJ2 is set to the first resistance value R1 or the second resistance value R1 or the second resistance value R1 or the second resistance value R1 or the second resistance value R1 or the second resistance value R1 depending on the direction of the second write voltage (in other words, the direction of the write current flowing in the second magnetic tunnel junction MTJ2) And may have a second resistance value R2. However, the resistance value of the second magnetic tunnel junction (MTJ2) may fluctuate through the packaging process of the magnetic memory device and / or the subsequent high temperature process. Accordingly, the final resistance value of the second magnetic tunnel junction MTJ2 may have a third resistance value R3 between the first and second resistance values R1 and R2.

As a result, through the above-described one programming, the second magnetic tunnel junction MTJ2 has the third resistance value R3, and a '1' corresponding to the second data can be written. Here, the third resistance value R3 may be between the first resistance value R1 and the second resistance value R2. Meanwhile, the third magnetic tunnel junction MTJ3 that is blown has a fourth resistance value R4 which is much smaller than the first resistance value R1, and '0' corresponding to the first data can be written. For example, the fourth resistance value R4 may be less than or equal to 1 kilo ohm (k).

6 is a simplified circuit diagram illustrating a read operation of a first memory cell according to embodiments of the present invention.

The data value of the selected first memory cell MC1 can be read by discriminating the difference between the resistance of the selected first memory cell MC1 and the resistance of the first reference cell RC1. Referring to FIG. 6, the first reference cell RC1 includes, for example, a pair of first magnetic tunnel junctions MTJ1 and a pair of first magnetic tunnel junctions MTJ1 connected in parallel, 1 select transistors SE1. Although not shown, the source lines SL connected to the first selection transistors SE1 of the first reference cell RC1 may be electrically connected to each other. According to another embodiment, the source of each of the first select transistors SE1 of the first reference cell RC1 may share one source line SL.

Before performing the read operation, the first magnetic tunnel junctions MTJ1 of the first reference cell RC1 may be programmed to have different resistance values. That is, one of the first magnetic tunnel junctions MTJ1 of the first reference cell RC1 may be programmed to have a first resistance value R1 and the other to have a second resistance value R2. The resistance of the first reference cell RC1 connected in parallel with the pair of first magnetic tunnel junctions MTJ1 is equal to the sum of the sum of the first resistance value R1 and the second resistance value R2 R2) / 2). On the other hand, data corresponding to the first resistance value R1 or the second resistance value R2 may be stored in the selected first memory cell MC1 through separate programming.

A turn-on voltage may be applied to the word line (WL) of the selected first memory cell (MC1) for performing a read operation and a turn-on voltage may be applied to the first magnetic tunnel junction (MTJ1) of the selected first memory cell The first read current Ir1 may flow. In addition, a turn-on voltage may be applied to the word line WL of the first reference cell RC1 and the second read currents < RTI ID = 0.0 > Ir2_1, Ir2_2) can flow. The first sense amplifier SA1 detects the resistance value of the first memory cell MC1 by the first read current Ir1 and the resistance value of the first reference cell RC1 by the second read currents Ir2_1 and Ir2_2 To detect what is stored in the selected first memory cell MC1. On the other hand, the first sense amplifier SA1 may be a part of the first peripheral circuit PC1 described with reference to Fig.

When the magnetization direction of the free layer FL is arranged in parallel with the magnetization direction of the fixed layer PL in the first magnetic tunnel junction MTJ1 of the selected first memory cell MC1, The data of the data MC1 may be read out as '0', for example. Alternatively, in the first magnetic tunnel junction MTJ1 of the selected first memory cell MC1, when the magnetization direction of the free layer FL is anti-parallel to the magnetization direction of the pinned layer PL , The data of the selected first memory cell MC1 may be read as '1', for example.

FIGS. 7A and 7B are simplified circuit diagrams illustrating a read operation of a second memory cell according to embodiments of the present invention.

Referring to FIG. 7A, the second reference cell RC2 is selected from the second sub-cells MC2_2. Accordingly, the second reference cell RC2 may include a third magnetic tunnel junction MTJ3 having a fourth resistance value R4. Meanwhile, the selected second memory cell MC2 may be the first sub-cell MC2-1 or the second sub-cell MC2-2. That is, the selected second memory cell MC2 may include a second magnetic tunnel junction (MTJ2) or a third magnetic tunnel junction (MTJ3). Accordingly, the selected second memory cell MC2 may have a resistance corresponding to the third resistance value R3 or the fourth resistance value R4.

The data value of the selected second memory cell MC2 can be read by discriminating the difference between the resistance of the selected second memory cell MC2 and the resistance of the second reference cell RC2. At this time, in order to increase the sensing margin, it is required that the resistance of the second reference cell RC2 has a value between the fourth resistance value R4 and the third resistance value R3. According to an embodiment of the present invention, in order to easily achieve such a requirement, a second bit line BL2 connected to a second reference cell RC2 and a second bit line BL2 connected to a second reference cell RC2, A control resistor Rct may be provided between the sense amplifiers SA2. That is, the third magnetic tunnel junction MTJ3 of the second reference cell RC2 and the control resistance Rct may be electrically connected. As a result, the resistance of the second reference cell RC2 sensed by the read operation is larger than the fourth resistance value R4 of the third magnetic tunnel junction MTJ3 and the resistance value of the fifth resistance R5 of the control resistor Rct May be a summed value. The summed value may be between the fourth resistance value R4 and the third resistance value R3 (e.g., about 7 kilohms (k?)). Lt; / RTI > On the other hand, the second sense amplifier SA2 and the control resistor Rct may be a part of the second peripheral circuit PC2 described with reference to Fig.

A turn-on voltage may be applied to the word line WL of the selected second memory cell MC2 for performing the read operation and the second memory device of the selected second memory cell MC2 Magnetic tunnel junction (MJT) or third magnetic tunnel junction (MTJ3)) can flow through the third read current (Ir3). Also, the turn-on voltage may be applied to the word line WL of the second reference cell RC2 and the third magnetic tunnel junction MTJ3 and the control resistance Rct of the second reference cell RC2 may be applied 4 read current Ir4 may flow. The second sense amplifier SA2 detects and detects the difference between the resistance of the second memory cell MC2 by the third read current Ir3 and the resistance of the second reference cell RC2 by the fourth read current Ir4, And the data stored in the selected second memory cell MC2 can be determined.

If the selected second memory cell MC2 is the first sub cell MC2-1, the data of the selected second memory cell MC2 may be read as '1', for example. Alternatively, when the selected second memory cell MC2 is the second sub-cell MC2-2, the data of the selected second memory cell MC2 may be read as '0', for example.

According to another embodiment, the second reference cell RC2 may be implemented in a form different from that shown in FIG. 7A. For example, the second reference cell RC2 may not include the third magnetic tunnel junction MTJ3 as a memory element.

Referring to FIG. 7B, the second reference cell RC2 may be composed only of the second selection transistor SE2. In this case, the fifth resistance value R5 of the control resistance Rct may be between the fourth resistance value R4 and the third resistance value R3. For example, the fifth resistance value R5 of the control resistance Rct may be about 7 kilohms (k?). A turn-on voltage may be applied to the word line WL of the selected second memory cell MC2 for performing the read operation and the second memory device of the selected second memory cell MC2 Magnetic tunnel junction (MJT) or third magnetic tunnel junction (MTJ3)) can flow through the third read current (Ir3). Also, the turn-on voltage may be applied to the word line WL of the second reference cell RC2, and the control resistance Rct of the second reference cell RC2 and the control resistance Rct of the second reference cell RC2, The fourth read current Ir4 can flow between the two-bit line BL and the source line SL. The second sense amplifier SA2 detects and detects the difference between the resistance of the second memory cell MC2 by the third read current Ir3 and the resistance of the second reference cell RC2 by the fourth read current Ir4, And the data stored in the selected second memory cell MC2 can be determined.

OTP memory devices have been used to repair semiconductor devices. For example, it is possible to test the semiconductor device, store the characteristics of the semiconductor device according to the test result in the OTP memory inside the semiconductor device, and prevent malfunction of the semiconductor device by operating the semiconductor device based on the information stored in the OTP memory. In addition, the OTP memory device may store other information for controlling the semiconductor device. For example, a semiconductor device may have different characteristics while passing through a semiconductor manufacturing process, and an OTP memory device stores information on different characteristics of such a semiconductor device, and information can be used to control the memory array.

 According to the embodiments of the present invention, a part of the memory cell array is implemented as an OTP cell array without forming the OTP memory device as described above in a separate area, so that a magnetic memory device optimized for high integration can be provided . In addition, by shorting the magnetic tunnel junction which is the memory element of the memory cells, it is possible to easily implement OTP memory cells. In addition, by separately forming reference cells and peripheral circuits for the OTP memory cells, the write and read operations of the OTP memory cells can be optimized. As a result, a magnetic memory device with improved reliability can be provided.

8A is an exemplary top view showing a magnetic memory device according to embodiments of the present invention. 8B is a cross-sectional view taken along line A-A 'and B-B' in FIG. 8A, and FIG. 8C is a cross-sectional view taken along line C-C ', D-D', and E-E 'in FIG. 8A.

8A to 8C, a substrate 100 including a cell array region CR and a peripheral circuit region PR is provided. The substrate 100 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate, but the embodiments of the present invention are not limited thereto. The cell array region CR may include a first cell array region CR1 and a second cell array region CR2. The first cell array region CR1 may be a region where the first memory cell array 10a of FIG. 2 is formed and the second cell array region CR2 may be a region where the second memory cell array 10b of FIG. 2 is formed Lt; / RTI > The peripheral circuit region PR may include a first peripheral circuit region PR1 and a second peripheral circuit region PR2. The first peripheral circuit region PR1 may be a region where the first peripheral circuit PC1 described with reference to Fig. 2 is formed and the second peripheral circuit region PR2 may be an area where the second peripheral circuit PR2 described with reference to Fig. PC2) is formed.

Device isolation patterns 102 may be provided in the substrate 100. [ The device isolation patterns 102 of the first and second cell array regions CR1 and CR2 may define the active line patterns ALP. The device isolation patterns 102 and active line patterns ALP of the first and second cell array regions CR1 and CR2 may be arranged along the first direction D1. The device isolation patterns 102 and the active line patterns ALP of the first and second cell array regions CR1 and CR2 extend in the second direction D2 intersecting the first direction D1. . ≪ / RTI > Active line patterns (ALP) may be doped with a dopant of the first conductivity type.

The device isolation patterns 102 of the first and second peripheral circuit regions PR1 and PR2 may define a first peripheral active portion PA1 and a second peripheral active portion PA2, respectively. The first peripheral active portion PA1 and the second peripheral active portion PA2 may be doped with a first conductive type or a second conductive type dopant different from the first conductive type.

In the first and second cell array regions CR1 and CR2, isolation recess regions 104 may traverse active line patterns ALP and device isolation patterns 102. [ From a plan viewpoint, the isolation recess regions 104 may have groove shapes extending in a first direction D1. The isolation recess regions 104 may divide each of the active line patterns ALP into cell active portions CA. The cell active portions CA may be part of the active line patterns ALP located between a pair of adjacent isolation recess regions 104. [ That is, the cell active portions CA may be defined by a pair of device isolation patterns 102 adjacent to each other and a pair of adjacent isolation recess regions 104 adjacent to each other. From a plan viewpoint, the cell active portions CA may be two-dimensionally arranged along the first direction D1 and the second direction D2.

At least one gate recess region 103 may traverse the cell active portions CA arranged along the first direction D1. The gate recess region 103 may extend parallel to the isolation recess regions 104. According to one embodiment, a pair of gate recess regions 103 may traverse cell active portions CA arranged in a first direction D1. In this case, a pair of cell transistors may be formed in the cell active portions CA, respectively. The cell transistor of the first cell array region CR1 may correspond to the first select transistor SE1 described with reference to FIGS. 2 and 3, and the cell transistor of the second cell array region CR2 may correspond to the first select transistor SE1 described with reference to FIGS. And the second selection transistor SE2 described with reference to FIGS. 5A and 5B.

The height of the bottom surface of the gate recess regions 103 may be substantially the same as the height of the bottom surface of the isolation recess regions 104. The heights of the lower surfaces of the gate and isolation recess regions 103 and 104 may be higher than the heights of the bottom surfaces of the element isolation patterns 102 of the first and second cell array regions CR1 and CR2.

Word lines WL may be disposed in each gate recess regions 103. [ The cell gate dielectric film 105 may be disposed between the word line WL and the inner surfaces of the respective gate recess regions 103. [ Due to the shape of the gate recess regions 103, the word line WL may have a line shape extending in the first direction D1. The cell transistor may include a word line (WL), and a channel region recessed by the gate recess region (103).

An isolation line IL may be disposed in each isolation recess regions 104. A isolation gate dielectric 106 may be disposed between the isolation line IL and the inner surface of each isolation recess regions 104. The isolation line IL may also have a line shape extending in the first direction D1.

Cell capping patterns 108 may be disposed on the word and isolation lines WL and IL, respectively. The cell capping patterns 108 may be disposed in the gate and isolation recess regions 103, The top surfaces of the cell capping patterns 108 may be substantially coplanar with the top surface of the substrate 100.

In operation of the magnetic memory device, an isolation voltage may be applied to the isolation line IL. The isolation voltage can prevent the channel from being formed below the inner surface of the isolation recess regions 104. That is, the isolated channel region under the isolation line IL may be turned off by the isolation voltage. Thus, the cell active portions CA divided from the active line patterns ALP can be electrically isolated from each other. In one example, if the active line patterns ALP are doped with a P-type dopant, the isolation voltage may be a ground voltage or a negative voltage.

The word line WL may comprise, for example, doped semiconductor material (ex, doped silicon, etc.), metal (ex, tungsten, aluminum, titanium and / or tantalum), conductive metal nitride (ex, titanium nitride, And / or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide). According to one embodiment, the isolation line IL may be formed of the same material as the word line WL. The cell gate dielectric film 105 and the isolation gate dielectric film 106 may comprise silicon oxide, silicon nitride, silicon oxynitride and / or a high dielectric material (e.g., an insulating metal oxide such as hafnium oxide, aluminum oxide, etc.). The cell capping patterns 108 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

The first impurity region 111 can be disposed in the cell active portions CA on one side of the word line WL and the second impurity region 112 can be disposed in the cell active portion on the other side of the word line WL CA). The first impurity region 111 may be disposed between a pair of word lines WL and the second impurity regions 112 may be disposed between the word line WL and the isolation line IL. Respectively, within the cell active portions CA of the cell. As a result, a pair of cell transistors formed in the cell active portions CA can share the first impurity region 111. The first and second impurity regions 111 and 112 may correspond to the source / drain regions of the cell transistor. The first and second impurity regions 111 and 112 may be doped with dopants of a second conductivity type different from the first conductivity type. One of the dopant of the first conductivity type and the dopant of the second conductivity type may be an N type dopant and the other may be a P type dopant.

The first peripheral gate dielectric layer 114a, the first peripheral gate electrode 116a and the first peripheral capping pattern 118a are sequentially stacked on the first peripheral active portion PA1 of the first peripheral circuit region PR1 . The first peripheral source / drain regions 120a may be disposed in the first peripheral active portion PA1 on either side of the first peripheral gate electrode 116a. First peripheral gate spacers 122a may be disposed on both sidewalls of the first peripheral gate electrode 116a. The first peripheral source / drain regions 120a may be doped with dopants of a different conductivity type than that of the dopants of the first peripheral active region PA1. Unlike the cell transistor, the first peripheral transistor including the first peripheral gate electrode 116a may include a planar channel region. That is, the first peripheral transistor may be a planar transistor. However, the embodiments of the present invention are not limited thereto. According to another embodiment, the first peripheral gate electrode 116a may have an electrode structure of a Fin-FET device. The first peripheral transistor may be a PMOS transistor or an NMOS transistor.

 The second peripheral gate dielectric film 114b, the second peripheral gate electrode 116b and the second peripheral capping pattern 118b are formed on the second peripheral active portion PA2 of the second peripheral circuit PC2 region PR1, Can be stacked in order. And the second peripheral source / drain regions 120b may be disposed in the second peripheral active portion PA2 on both sides of the second peripheral gate electrode 116b. Second peripheral gate spacers 122b may be disposed on both sidewalls of the second peripheral gate electrode 116b. The second peripheral source / drain regions 120b may be doped with dopants of a different conductivity type than those of the dopants of the second peripheral active portion PA2. The second peripheral transistor including the second peripheral gate electrode 116b may be implemented in substantially the same form as the first peripheral transistor. That is, the second peripheral transistor may be a planar transistor. However, the embodiments of the present invention are not limited thereto. According to another embodiment, the second peripheral gate electrode 116b may have an electrode structure of a fin-FET device. The second peripheral transistor may be a PMOS transistor or an NMOS transistor.

According to the inventive concept, the first peripheral transistor may be a low voltage transistor operating under a low voltage, and the second peripheral transistor may be a high voltage transistor operating under a high voltage. The channel of the second peripheral transistor may be formed longer than the channel of the first peripheral transistor so as to withstand a high voltage (i.e., to prevent punch through between the second peripheral source / drain regions 120b). That is, the second width W2 of the second peripheral gate electrode 116b may be greater than the first width W1 of the first peripheral gate electrode 116a. In addition, the gate dielectric layer of the second peripheral transistor may be configured to withstand a high voltage (i.e., withstand a high potential difference between the second peripheral gate electrode 116b and the second peripheral source / drain regions 120b) It can be formed thicker than the gate dielectric film of the transistor. That is, the second thickness t2 of the second peripheral gate dielectric 114b may be greater than the first thickness t1 of the first peripheral gate dielectric 114a.

Each of the first and second peripheral gate dielectric layers 114a and 114b may comprise, for example, silicon oxide and / or a high dielectric material (e.g., an insulating metal oxide such as hafnium oxide, aluminum oxide, etc.). According to one embodiment, the first peripheral gate dielectric 114a may be formed of a relatively thin silicon oxide film and the second peripheral gate dielectric 114b may be formed of a relatively thick silicon oxide film. According to another embodiment, the first peripheral gate dielectric layer 114a may be formed of a single layer containing a high dielectric material, and the second peripheral gate dielectric layer 114b may be formed of a double layer of a silicon oxide layer and a high-k dielectric layer . Each of the first and second peripheral gate electrodes 114 is formed of a semiconductor material doped with a dopant (ex, doped silicon, etc.), a metal (ex, tungsten, aluminum, titanium and / or tantalum), a conductive metal nitride , Titanium nitride, tantalum nitride and / or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide). Each of the first and second peripheral capping patterns 116 may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. Each of the first and second peripheral gate spacers 122b may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

The resistance pattern 124 may be disposed on the element isolation pattern 102 of the second peripheral circuit region PR2. The resist pattern 124 may comprise a semiconductor material. For example, the resist pattern 124 may comprise silicon, germanium or silicon-germanium. According to one embodiment, the semiconductor material included in the resistance pattern 124 may be in a polycrystalline state. The resist pattern 124 may be doped with a dopant (ex, n-type dopant or p-type dopant) for adjusting the resistivity of the resist pattern 124. [ According to one embodiment, the entire resist pattern 124 may be substantially uniformly doped with a dopant for resistivity adjustment. Alternatively, the resistive pattern 124 may be partially doped. Insulating spacers 126 may be disposed on the sidewalls of the resistance pattern 124 and a protective insulating film may be disposed on the upper surface of the resistance pattern 124. [ Each of the insulating spacers 126 and the protective insulating pattern 128 may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The resistance pattern 124 may correspond to the control resistance Rct described with reference to Figs. 7A and 7B.

The first interlayer dielectric film 130 may be disposed on the entire surface of the substrate 100. [ The first interlayer dielectric film 130 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The source lines SL can be in contact with the substrate 100 through the first interlayer dielectric film 130 of the first and second cell array regions CR1 and CR2. The source lines SL may extend in the first direction D1. The source lines SL may be electrically connected to the first impurity regions 11 arranged along the first direction D1. The upper surface of the source lines SL may be substantially coplanar with the upper surface of the first interlayer dielectric film 130 of the first and second cell array regions CR1 and CR2. The source lines SL may be formed of a semiconductor material doped with a dopant (ex, doped silicon, etc.), a metal (ex, tungsten, aluminum, titanium and / or tantalum), a conductive metal nitride (ex, titanium nitride, tantalum nitride and / Or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide). The first interlayer dielectric film 130 of the first peripheral circuit region PR1 may cover the first peripheral transistor and the first interlayer dielectric film 130 of the second peripheral circuit region PR2 may cover the second peripheral transistor and the resistance pattern (Not shown).

The second interlayer dielectric layer 140 may be disposed on the front surface of the first interlayer dielectric layer 130. The second interlayer dielectric film 140 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. In the first cell array region CR1, the first contact plugs 142 can continuously penetrate the second interlayer dielectric film 140 and the first interlayer dielectric film 130. [ The first contact plugs 142 may be electrically connected to the second impurity regions 112 of the first cell array region CR1, respectively. In the second cell array region CR2, the second contact plugs 144 can continuously penetrate the second interlayer dielectric film 140 and the first interlayer dielectric film 130. [ And the second contact plugs 144 may be electrically connected to the second impurity regions 112 of the second cell array region CR2, respectively. The first and second contact plugs 144 may be formed of the same conductive material as the source line. The upper surfaces of the first and second contact plugs 144 may be substantially coplanar with the upper surface of the second interlayer insulating film 140.

The first memory elements ME1 may be disposed on the second interlayer insulating film 140 of the first cell array region CR1. The first memory elements ME1 may vertically overlap with the first contact plugs 142, respectively. That is, the first memory elements ME1 may be connected to the first contact plugs 142, respectively. The first memory elements ME1 may be electrically connected to the second impurity regions 112 of the first cell array region CR1 through the first contact plugs 142. [ The first memory elements ME1 may be two-dimensionally arranged along the first direction D1 and the second direction D2 from a plan viewpoint. The first memory elements ME1 may correspond to the first memory elements ME1 described with reference to Figs. 2, 3, 4A, 4B and 7A. That is, each of the first memory elements ME1 may include a first magnetic tunnel junction MTJ1. Since the first magnetic tunnel junction MTJ1 has been described above, a detailed description thereof will be omitted. A part of the first memory elements ME1 may constitute the first memory cells MC1 described above, and the other part may constitute the first reference cells RC1 described above. In addition, each of the first memory elements ME1 may further include a first lower electrode BE1 and a first upper electrode TE1. The first magnetic tunnel junction MTJ1 is disposed between the first lower electrode BE1 and the first upper electrode TE1. That is, the first lower electrode BE1 is disposed between the first contact plug 142 and the first magnetic tunnel junction MTJ1, and the first upper electrode TE1 is disposed on the first magnetic tunnel junction MTJ1 . Each of the first lower electrode BE1 and the first upper electrode TE1 is formed of a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a transition metal (e.g., titanium, tantalum etc.) , Ruthenium, platinum, and the like).

The second memory elements ME2 may be disposed on the second interlayer insulating film 140 of the second cell array region CR2. The second memory elements ME2 may be vertically overlapped with the second contact plugs 144, respectively. That is, the second memory elements ME2 may be connected to the second contact plugs 144, respectively. The second memory elements ME2 may be electrically connected to the second impurity regions 112 of the second cell array region CR2 through the second contact plugs 144. [ The second memory elements ME2 can be two-dimensionally arranged along the first direction D1 and the second direction D2 from a plan viewpoint. The second memory elements ME2 may correspond to the second memory elements ME2 described with reference to Figs. 2, 5A, 5B and 7A. That is, some of the second memory elements ME2 may include a second magnetic tunnel junction (MTJ2), and others may include a third magnetic tunnel junction (MTJ3). Since the second and third magnetic tunnel junctions MTJ2 and MTJ3 are as described above, detailed description thereof will be omitted. A part of the second memory elements ME2 can constitute the second memory cells MC2 described above, and the other part can constitute the second reference cells RC2 described above. In addition, each of the second memory elements ME2 may further include a second lower electrode BE2 and a second upper electrode TE2. Each of the second and third magnetic tunnel junctions MTJ2 and MTJ3 is disposed between the second lower electrode BE2 and the second upper electrode TE2. The second lower electrode BE2 and the second upper electrode TE2 may include the same materials as the first lower electrode BE1 and the second upper electrode TE2, respectively.

The third interlayer insulating film 150 may be disposed on the entire surface of the second interlayer insulating film 140. [ The third interlayer insulating film 150 of the first and second cell array regions CR1 and CR2 may be in contact with the sidewalls of the first and second memory devices ME1 and ME2. In addition, the third interlayer insulating film 150 of the first and second cell array regions CR1 and CR2 may expose the upper surfaces of the first and second memory elements ME1 and ME2. The third interlayer dielectric film 150 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

The first peripheral plugs 152 may contact the substrate 100 through the first to third interlayer dielectric layers 130, 140 and 150 in the first peripheral circuit PC1 region. The first peripheral plugs 152 may be electrically connected to the first peripheral source / drain regions 120a. The second peripheral plugs 154 may be in contact with the substrate 100 through the first to third interlayer dielectric layers 130, 140 and 150 in the second peripheral circuit region PR2. And the second peripheral plugs 154 may be electrically connected to the second peripheral source / drain regions 120b. The third peripheral plug 156 is electrically connected to the resistance pattern 124 through the first to third interlayer dielectric layers 130, 140 and 150 of the second peripheral circuit region PR2 and the protective insulation pattern 128 Can be connected. The first to third peripheral plugs 152, 154, and 156 may include the same conductive material as the source lines SL.

The first bit lines BL1 may be disposed on the third interlayer insulating film 150 of the first cell array region CR1. The first bit lines BL1 may extend in the second direction D2. Each of the first bit lines BL1 may be in common contact with a plurality of first memory elements ME1 arranged in a second direction D2. And the second bit lines BL2 may be disposed on the third interlayer insulating film 150 of the second cell array region CR2. And the second bit lines BL2 may extend in the second direction D2. Each of the second bit lines BL2 may be in common contact with the plurality of second memory elements ME2 arranged in the second direction D2. The first and second bit lines BL1 and BL2 may comprise a metal such as copper or aluminum.

The first interconnects L1 may be disposed on the third interlayer insulating film 150 in the region of the first peripheral circuit PC1. The first wirings L1 may be electrically connected to the first peripheral plugs 152, respectively. The second wirings L2 may be disposed on the third interlayer insulating film 150 in the second peripheral circuit region PR2. And the second wirings L2 may be electrically connected to the second peripheral plugs 154, respectively. The third interconnection L3 may be disposed on the third interlayer insulating film 150 in the second peripheral circuit region PR2. And the third wiring (L3) can be electrically connected to the third peripheral plug (156). The first to third wirings L1, L2, and L3 may include the same material as the first and second bit lines BL1 and BL2.

The cell transistor and the first memory element ME1 of the first cell array region CR1 are connected to the first peripheral source / drain regions of the first peripheral transistor via the first bit line BL1 and the first wiring L1 120a, respectively. The cell transistor of the second cell array region CR2 and the second memory element ME2 are connected to the second peripheral source / drain regions (second peripheral transistor) of the second peripheral transistor through the second bit line BL2 and the second wiring L2 120b. The cell transistor and the second memory element ME2 of the second cell array region CR2 constituting the second reference cell RC2 are electrically connected to the second bit line BL1 through the second bit line BL2 and the third wiring L3, (Not shown).

9A is an exemplary top view showing a magnetic memory device according to embodiments of the present invention. FIG. 9B is a cross-sectional view taken along the line A-A 'and B-B' in FIG. 9A, and FIG. 9C is a cross-sectional view taken along line C-C ', D-D', and E-E 'in FIG. 9A. The magnetic memory device of Figures 9A-9C may be the same as the magnetic memory device of Figures 8A-8C except that a portion of the second memory elements ME2 are replaced by third contact plugs 146 . For the sake of simplicity of description, a description of overlapping configurations is omitted.

9A to 9C, a part of the second impurity regions 112 of the second cell array region CR2 may be formed in a portion corresponding to the third, fourth, fifth, sixth, seventh, And may be connected to the second bit line BL2 through the contact plug 146. [ That is, some of the cell transistors of the second cell array region CR2 may be electrically connected to the second bit line BL2 without passing through the second memory device ME2. The cell transistors electrically connected to the second bit line BL2 through the third contact plug 146 may correspond to the second reference cells RC2 described with reference to FIG. 7B. As shown, the second reference cells RC2 may be provided in a plurality and the second reference cells RC2 may be arranged in the second direction D2 to form one second bit line BL2. You can share.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (20)

A plurality of word lines;
A plurality of bit lines crossing the word lines, the plurality of bit lines comprising first bit lines and second bit lines spaced apart from the first bit lines in an extending direction of the word lines;
A plurality of first memory cells coupled between the word lines and the first bit lines intersecting each other, each of the first memory cells including a first memory device and a first select device coupled thereto; And
A plurality of second memory cells coupled between the word lines and the second bit lines intersecting each other, each of the second memory cells comprising a second memory device and a second select device coupled thereto,
Wherein each of the first and second memory elements comprises a magnetic tunnel junction comprising a fixed layer, a free layer and a tunnel barrier layer therebetween, and wherein the magnetic tunnel junction of a portion of the second memory elements comprises a tunnel barrier Wherein the layer is insulatingly broken and has an irreversible resistance state. The method according to claim 1,
Wherein the first memory cells constitute a normal memory cell array which can be programmed a plurality of times,
Wherein the second memory cells constitute an OTP memory cell array that can be programmed only once. The method according to claim 1,
Wherein the magnetic tunnel junction of the first memory elements is a first magnetic tunnel junction,
The magnetic tunnel junction of the portion of the second memory elements is a second magnetic tunnel junction,
The remaining of the second memory elements being a third magnetic tunnel junction,
Wherein the first magnetic tunnel junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming,
The second magnetic tunnel junction having a third resistance value corresponding to the first data through one programming,
Wherein the third magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming,
Wherein the first to fourth resistance values are different from each other. The method of claim 3,
Wherein the first resistance value is smaller than the second resistance value,
Wherein the third resistance value is smaller than the first resistance value,
And the fourth resistance value is between the first and second resistance values. The method of claim 3,
Some of the first memory cells are used as a first reference cell for a read operation of the first memory cells,
Wherein some of the second memory cells are used as a second reference cell for a read operation of the second memory cells. 6. The method of claim 5,
Wherein the first reference cell is configured such that a pair of first memory cells of the first memory cells are connected in parallel via a first bit line. The method according to claim 6,
Wherein the first magnetic tunnel junction of any one of the pair of first memory cells is programmed to have the first resistance value and the other one of the first magnetic tunnel junctions is programmed to have the second resistance value, Device. 6. The method of claim 5,
Wherein the second reference cell comprises the second one of the second memory cells. 9. The method of claim 8,
And a control resistor electrically connected to the second reference cell,
Wherein the reference resistance for the read operation of the second memory cells is a sum of the third resistance value of the second magnetic tunnel junction constituting the second reference cell and the fifth resistance value of the control resistance, . 10. The method of claim 9,
Wherein the summed value is between the third resistance value and the fourth resistance value. The method according to claim 1,
A first peripheral circuit electrically connected to the first memory cells via the first bit lines; And
And a second peripheral circuit electrically connected to the second memory cells via the second bit lines,
And the second peripheral circuit includes at least one second peripheral transistor driven under a higher voltage than the first peripheral transistor of the first peripheral circuit. 12. The method of claim 11,
Wherein the first peripheral transistor includes a first peripheral gate dielectric layer and a first peripheral gate electrode,
Wherein the second peripheral transistor includes a second peripheral gate dielectric layer and a second peripheral gate electrode, wherein the thickness of the second peripheral gate dielectric layer is greater than the thickness of the first gate dielectric layer. 13. The method of claim 12,
And the second peripheral gate electrode has a second width greater than the first width of the first peripheral gate electrode. A memory cell array including a normal cell array and an OTP cell array;
A first peripheral circuit electrically connected to the normal cell array through first bit lines; And
And a second peripheral circuit electrically connected to the OTP cell array through second bit lines,
The normal cell array includes a plurality of first memory cells including a first magnetic tunnel junction and a first select transistor connected thereto,
The OTP cell array includes a plurality of second memory cells including a second magnetic tunnel junction and a second select transistor coupled thereto,
Wherein some of the second magnetic tunnel junctions have an irreversible resistance state. 15. The method of claim 14,
The portion of the second magnetic tunnel junctions being a first sub-magnetic tunnel junction,
A second portion of the second magnetic tunnel junctions being a second sub-magnetic tunnel junction,
Wherein the first magnetic tunnel junction has a first resistance value corresponding to the first data or a second resistance value corresponding to the second data through a plurality of programming,
Wherein the first sub-magnetic tunnel junction has a third resistance value corresponding to the first data through one programming,
Wherein the second sub-magnetic tunnel junction has a fourth resistance value corresponding to the second data through one programming,
Wherein the first resistance value is less than the second resistance value, the third resistance value is less than the first resistance value, and the fourth resistance value is between the first and second resistance values. 16. The method of claim 15,
Some of the first memory cells are used as a first reference cell for a read operation of the first memory cells,
Wherein one selected from the second memory cells including the first sub-magnetic tunnel junction is used as a second reference cell for a read operation of the second memory cells. 17. The method of claim 16,
Wherein the second peripheral circuit includes a control resistor electrically connected to the second reference cell,
Wherein the reference resistance for the read operation of the second memory cells is a sum of the third resistance value of the second magnetic tunnel junction constituting the second reference cell and the fifth resistance value of the control resistance, . 16. The method of claim 15,
Some of the first memory cells are used as a first reference cell for a read operation of the first memory cells,
The OTP cell array further includes a second reference cell for a read operation of the second memory cells,
And the second reference cell includes a third selection transistor connected to one of the second bit lines without passing through a variable resistance element. 19. The method of claim 18,
Wherein the second peripheral circuit includes a control resistor electrically connected to the second reference cell,
Wherein a reference resistance for a read operation of the second memory cells utilizes a fifth resistance value of the control resistor. 15. The method of claim 14,
Wherein the first peripheral circuit comprises at least one first peripheral transistor,
Wherein the second peripheral circuit includes at least one second peripheral transistor,
And the second peripheral transistor is driven under a higher voltage than the first peripheral transistor.

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