CN107039579A - Including reversible and single programmable magnetic tunnel-junction semiconductor devices - Google Patents

Abstract

A kind of semiconductor devices, it includes memory cell array, and the memory cell array further comprises the array of the first magnetic memory cell and the array of the second magnetic memory cell.Each in first magnetic memory cell includes the first magnetic tunnel junction structure with reversible impedance state, and each in the second magnetic memory cell includes the second magnetic tunnel junction structure with single programmable (OTP) impedance state.

Description

Including reversible and single programmable magnetic tunnel-junction semiconductor devices

Technical field

Example embodiment is related to semiconductor devices, such as magnetic memory device.

Background technology

Due to the demand gradually increased to the semiconductor devices with faster speed and/or more low-power consumption, semiconductor device Part needs faster arithmetic speed and/or lower operating voltage.Magnetic memory device has been suggested to meet such want Ask.For example, magnetic memory device can provide such as relatively low wait and/or non-volatile.As a result, magnetic memory device just quilt It is considered upcoming memory device of future generation.

Magnetic memory device can include MTJ (MTJ).MTJ can include two magnetospheres and be interposed in them Between tunneling barrier layer.MTJ impedance can depend on the magnetospheric direction of magnetization.For example, MTJ impedance is magnetospheric It is higher when parallel than them during direction of magnetization antiparallel.This species diversity in impedance can be used for storing in magnetic memory device Data.

The content of the invention

One or more example embodiments of present inventive concept provide more highly integrated magnetic memory device.

One or more example embodiments of present inventive concept provide more highly reliable magnetic memory device.

At least one example embodiment provides a kind of semiconductor devices, and it includes：Multiple wordline；It is multiple through described The bit line of multiple wordline, the multiple bit line includes the first bit line and the second bit line, second bit line and first bit line It is spaced apart on the direction that multiple wordline extend；Multiple first memory cell, the multiple first storage power supply is connected to multiple Between wordline and the first bit line, each in multiple first memory cell includes the first memory element and first choice element, First memory element and first choice element are connected to each other；And multiple second memory cell, the multiple second memory cell Be connected between multiple wordline and the second bit line, each in the multiple second memory cell include the second memory element and Second selection element, the second memory element and the second selection element are connected to each other.First memory element includes the first magnetic tunnel Road knot, and each that second memory element is included in the second magnetic tunnel-junction, first and second magnetic tunnel-junction includes Nailed layer, free layer and the tunneling barrier layer between the nailed layer and free layer.The of second magnetic tunnel-junction The tunneling barrier layer of a part has irreversible impedance state.

At least one other example embodiment provides a kind of semiconductor devices, and it includes：Memory cell array, this is deposited Storage unit array includes Reprogrammable cellular array and single programmable (OTP) cellular array；It is electrically connected by the first bit line It is connected to the first peripheral circuit of Reprogrammable cellular array；And the array of OTP unit is electrically connected to by the second bit line Second peripheral circuit.Reprogrammable cellular array is included in multiple first memory cell, the multiple first memory cell Each includes the first magnetic tunnel-junction and first choice transistor, and the first magnetic tunnel-junction and first choice transistor are connected to each other. The array of OTP unit includes multiple second memory cell, and each in the multiple second memory cell includes the second magnetic tunnel Road knot and the second selection transistor, the second magnetic tunnel-junction and the second selection transistor are connected to each other.Second magnetic tunnel-junction Part I has irreversible impedance state.

At least one other example embodiment provides a kind of semiconductor devices, and it includes：Memory cell array, this is deposited Storage unit array includes the array of the first magnetic memory cell and the array of the second magnetic memory cell, the first magnetic memory cell In each include the first magnetic tunnel junction structure with reversible impedance state, and each in the second magnetic memory cell Including the second magnetic tunnel junction structure with single programmable (OTP) impedance state.

Brief description of the drawings

Example embodiment will be more clearly understood that from the brief description provided below in conjunction with the accompanying drawings.Accompanying drawing shows non- Limited example embodiment, as described in this.

Fig. 1 is the block diagram for the magnetic memory device for showing some example embodiments according to present inventive concept；

Fig. 2 is the circuit of a part for the magnetic memory device for showing some example embodiments according to present inventive concept Figure；

Fig. 3 is the view for the first memory cell for schematically showing some example embodiments according to present inventive concept；

Fig. 4 A and 4B are two distinct types of first magnetic for showing some example embodiments according to present inventive concept The schematic diagram of tunnel knot；

Fig. 5 A and 5B are to schematically show the first subelement and according to some example embodiments of present inventive concept The view of two subelements；

Fig. 6 is the example read operation for the first memory cell for showing some example embodiments according to present inventive concept Schematic circuit；

Fig. 7 A and 7B be show some example embodiments according to present inventive concept the second memory cell it is exemplary The schematic circuit of read operation；

Fig. 8 A are the planes of the example for the magnetic memory device for showing some example embodiments according to present inventive concept Figure；

Fig. 8 B are the profiles along Fig. 8 A line A-A ' and B-B ' interception；

Fig. 8 C are the profiles along Fig. 8 A line C-C ', D-D ' and E-E ' interception；

Fig. 9 A are the planes of the example for the magnetic memory device for showing some example embodiments according to present inventive concept Figure；

Fig. 9 B are the profiles along Fig. 9 A line A-A ' and B-B ' interception；And

Fig. 9 C are the profiles along Fig. 9 A line C-C ', D-D ' and E-E ' interception.

It should be noted that these figures are intended to method, structure and/or the material that explanation is utilized in particular example embodiment The usual characteristic of material simultaneously supplements the word description being presented below.But, these figures be not in proportion and can be inaccurate Ground reflects the precision architecture or performance characteristics of any given embodiment, and should not be construed as defining or limiting example embodiment The number range or characteristic covered.For example, molecule, layer, region and/or the relative thickness of structural detail and positioning are in order to clear And can be reduced or exaggerated.Similar or same reference numerals use is intended to indicate that similar or similar elements in various figures Or the presence of feature.

Embodiment

The example embodiment for the present inventive concept explained and illustrated herein includes their complementary corresponding parts.Identical Reference or identical accompanying drawing mark represent similar elements throughout the specification.

Fig. 1 is the block diagram for the magnetic memory device for showing some example embodiments according to present inventive concept.

Reference picture 1, magnetic memory device can include memory cell array 10, and the memory cell array is configured to storage From the data of outside input, and including peripheral circuit, the peripheral circuit is configured to control memory cell array 10.Memory cell Array 10 can include normal cell arrays (being also referred to as Reprogrammable cell array herein) 10a and single programmable (OTP) is single Element array 10b.In other words, for example, a part of memory cell array 10 may be used as normal cell arrays 10a, and another part Memory cell array 10 may be used as OTP unit array 10b.Peripheral circuit can include row decoder 20, column decoder 30, Read/write circuit 40 and control logic 50.

Each in normal cell arrays 10a and OTP unit array 10b can include multiple memory cell, Mei Gecun Storage unit includes at least one memory element and at least one selection element.Normal cell arrays 10a memory cell can be It is re-writable enter memory cell, and OTP unit array 10b memory cell can be one-time programmable memory.Normal cell Array 10a and OTP unit array 10b memory cell may be coupled to wordline and bit line.Below, for the sake of brief, just Constant element array 10a memory cell is referred to as ' normal memory cell ', and OTP unit array 10b memory cell is referred to as ' OTP memory cell '.In addition, the bit line for being connected to normal memory cell is referred to as ' the first bit line ', and it is connected to ' OTP storages Unit ' bit line be referred to as ' the second bit line '.

Row decoder 20 can be connected to normal cell arrays 10a and OTP unit array 10b by wordline.Row decoder 20 can be configured to decoding from outside transmit address information and based on decoding address information selection wordline in one.

Each column select circuit 30 and read/write circuit 40 are segmented into two regions, described two regions respectively with normally Cell array 10a and OTP unit array 10b is associated.In other words, for example, column select circuit 30 can include being electrically connected to just First column select circuit 30a of normal memory cell and the second column select circuit 30b for being electrically connected to OTP memory cell.Similarly, Read/write circuit 40 can include being electrically connected to the first read/write circuit 40a of normal memory cell and be electrically connected to OTP storage lists Second read/write circuit 40b of member.

In more detail, for example, the first column select circuit 30a can be connected to normal cell arrays by the first bit line 10a and the address information that decoding is transmitted from outside can be configured to, and based on the address information selection a plurality of the being decoded One in one bit line.First read/write circuit 40a may be coupled to by the first column select circuit 30a the first bit lines selected.The Two column select circuit 30b can be connected to OTP unit array 10b by the second bit line, it is possible to be configured to decoding and passed from outside Defeated address information, and based on one in a plurality of second bit line of address information selection being decoded.By the second column select circuit Second bit line of 30b selections may be coupled to the second read/write circuit 40b.

Under the control of control logic 50, the first read/write circuit 40a can be configured to provide the first bit line bias, use Selected one in access normal memory cell.For example, the first read/write circuit 40a can be configured to selected The first bit line the first bit-line voltage is provided, and here, first bit-line voltage can be used for the selection in normal memory cell One upper execution read or write.First read/write circuit 40a can include the first write driver and the first sensing amplifier. Under the control of control logic 50, the second read/write circuit 40b can be configured to provide the second bit line bias, for access from At least one of OTP memory cell selection.For example, the second read/write circuit 40b can be configured to selected second bit line Second bit-line voltage is provided, and here, the second bit-line voltage can be used for being chosen execution on one in OTP memory cell Read or write.Second read/write circuit 40b can include the second write driver and the second sensing amplifier.

Control logic 50 can be configured to the command signal output control signal in response to being inputted from outside, for controlling Magnetic memory device.The control signal can be used for controlling read/write circuit 40.

Fig. 2 is the circuit of a part for the magnetic storage device for showing some example embodiments according to present inventive concept Figure.

Reference picture 2, magnetic memory device can include multiple wordline WL, multiple bit lines, memory cell array 10, first week Side circuit PC1 and the second peripheral circuit PC2.Memory cell array 10 can include first arranged in the first direction dl successively Memory cell array 10a and the second memory cell array 10b.First memory cell array 10a can correspond to Fig. 1 normal list Element array 10a, and the second memory cell array 10b can correspond to Fig. 1 OTP unit array 10b.Here, first direction D1 It can be selected to parallel to or be arranged essentially parallel to wordline WL.Second direction D2 can be selected to through first direction D1 or Person is parallel or substantially parallel to bit line.Wordline WL can extend with through the first memory cell array in the first direction dl 10a and the second memory cell array 10b.Bit line can be arranged through wordline WL.Bit line can include being connected to the first storage Cell array 10a the first bit line BL1 and the second bit line BL2 for being connected to the second memory cell array 10b.

First memory cell array 10a can include the first memory cell MC1.First memory cell MC1 can be two-dimentional Or three dimensional arrangement.The first memory cell MC1 can be arranged between wordline WL and the first bit line BL1 and be connected to wordline WL With the first bit line BL1.First memory cell MC1 can correspond to the normal memory cell of the description of reference picture 1.Second memory cell Array 10b can include the second memory cell MC2.Second memory cell MC2 can be by two dimension or three dimensional arrangement.Second storage is single First MC2 can be arranged between wordline WL and the second bit line BL2 and be connected to wordline WL and the second bit line BL2.Second storage is single First MC2 can correspond to the OTP memory cell of the description of reference picture 1.Multiple first memory cell MC1 and multiple second memory cell MC2 can be commonly connected to each bit line WL.Moreover, constituting multiple first memory cell MC1 of each column can be connected respectively to On same wordline WL and a corresponding first bit line BL1 can not shared.Similarly, multiple the second of each column is constituted to deposit Storage unit MC2 can be connected respectively to not same wordline WL and can share a corresponding second bit line BL2.

Each first memory cell MC1 can include the first memory element ME1 and first choice element SE1.First storage Element ME1 can be arranged between the first bit line BL1 and first choice element SE1 and be connected to the first bit line BL1 and the first choosing Select element SE1, and first choice element SE1 can be arranged between the first memory element ME1 and wordline WL and be connected to first Memory element ME1 and wordline WL.First memory element ME1 can be variable-impedance device, and its impedance can be by putting on it On electric pulse and be switched to one at least two states.In at least some example embodiments, the first memory element ME1 can have hierarchy, and its resistance can change by using the spin transfer process of the electric current through it.For example, First memory element ME1 can have hierarchy, and the hierarchy is configured to that magnetoresistive characteristic is presented, it is possible to including at least One ferromagnetic material and/or at least one antiferromagnetic materials.In at least some example embodiments, the first memory element ME1 can include magnetic tunnel-junction.

First choice element SE1 can be configured to control through the electric current flowing of the first memory element ME1 electric charge.Example Such as, first choice element SE1 can be diode, pnp bipolar transistors, npn bipolar transistors, NMOS (n-channel metal oxidations Thing semiconductor) one kind in field-effect transistor (FET) and PMOS (p-channel metal-oxide semiconductor (MOS)) FET.In first choice In the case that element SE1 is three terminal switch devices (for example, bipolar transistor or MOSFET), line in addition is (for example, source electrode Line) (not shown) may be coupled to first choice element SE1.By reference picture 3,4A and 4B the first memory cell described in more detail MC1 example embodiment.

Second memory cell MC2 can be arranged to have similar to the first memory cell MC1 or with the first memory cell MC1 Identical structure.For example, each in the second memory cell MC2 can include the selection members of the second memory element ME2 and second Part SE2, second memory element is arranged to the form of magnetic tunnel-junction, and the second selection element SE2 is configured to have and the One selection element SE1 essentially identical configurations.But, some second memory element ME2 may be at blown state (blown State), and others may be at non-blown state (un-blown state).Here, blown state means each Short circuit is formed between two memory element ME2 two magnetospheres.For example, performing single programming operation to be applied to two magnetospheres Increase in the case of the voltage of breakdown voltage, dielectric breakdown phenomenon, and thus the second storage can occur in tunneling barrier layer Element ME2 can turn into blown state.The dielectric breakdown phenomenon of tunneling barrier layer can be irreversible, and the magnetic channel that fuses The electrical impedance of knot can be less than the electrical impedance of non-fusing magnetic tunnel-junction.In a word, because some second memory element ME2 can be set For irreversible impedance state, the second memory cell array 10b can be used for realizing otp memory part.Below, for concise edge Therefore, the second memory cell MC2 that its second memory element ME2 is in non-blown state is referred to as the first subelement (for example, Fig. 5 A MC2_1), and its second memory element ME2 be in blown state the second memory cell MC2 be referred to as the second subelement (example Such as, Fig. 5 B MC2_2).By reference picture 5A and 5B the first and second subelements MC2_1 and MC2_2 described in more detail example Embodiment.

Each first memory cell MC1 can be connected to the first peripheral circuit by a corresponding first bit line BL1 PC1, and each second memory cell MC2 can be connected to the second peripheral circuit PC2 by a corresponding second bit line BL2.The One peripheral circuit PC1 can include Fig. 1 the first column select circuit 30a and/or the first read/write circuit 40a.Second peripheral circuit PC2 can include Fig. 1 the second column select circuit 30b and/or the second read/write circuit 40b.According at least the one of present inventive concept A little example embodiments, the first peripheral circuit PC1 can include the first peripheral transistor, and they are low voltage transistors.Second week Side circuit PC2 can include the second peripheral transistor, and at least one second peripheral transistor can be high voltage transistor, its threshold Threshold voltage is higher than the threshold voltage of the first peripheral transistor.This makes it possible to allow high pressure is more stable to be applied to some and second deposit On storage unit MC2, second memory cell is realized using the second subelement MC2_2.

When read operation is performed on the first memory cell array 10a, some first memory cell MC1 may be used as base Quasi- unit.Similarly, when read operation is performed on the second memory cell array 10b, some second memory cell MC2 can be with As reference cell.Below, the first memory cell array 10a reference cell will be referred to as the first reference cell RC1, and second Memory cell array 10b reference cell will be referred to as the second reference cell RC2.

In at least some example embodiments, the first reference cell RC1 can be arranged on adjacent pair wordline WL and wear Cross between their wherein one the first bit line BL1 and be connected to the adjacent pair wordline WL and described wherein one first Bit line BL1.For example, the first reference cell RC1 can include a pair first memory elements in parallel with the first bit line BL1, and Connect a pair of first choice element SE1 of the memory element of this pair first respectively.But, present inventive concept should not be limited to this.The One reference cell RC1 can be arranged to multiple.For example, multiple first reference cell RC1 can be arranged on adjacent pair wordline WL And through their the first bit line BL1 and it is connected to the adjacent pair wordline WL and the first bit line BL1.First Reference cell RC1 example embodiment describes reference picture 6 again.

Second reference cell RC2 can be realized using the second subelement MC2_2.In other words, for example, the second reference cell RC2 can include the second memory element ME2 in blown state.Second reference cell RC2 can be arranged to multiple and multiple Second reference cell RC2 can be arranged along second direction D2, thus constitute row.Constitute multiple second reference cells of each row RC2 may be coupled on not same wordline WL and can share a corresponding second bit line BL2.Second reference cell RC2 will Reference picture 7A is described again.

Fig. 3 is the view for the first memory cell for schematically showing some embodiments according to present inventive concept.

Reference picture 3, the first memory cell MC1 can include the first magnetic tunnel-junction MTJ1 and the conduct for acting as memory device The first choice transistor SE1 of selection element.First choice transistor SE1 gate electrode may be coupled to a corresponding wordline WL, first choice transistor SE1 source electrode may be coupled to a corresponding source electrode line SL, and first choice transistor SE1 Drain electrode can be connected to a corresponding first bit line BL1 by the first magnetic tunnel-junction MTJ1.

First magnetic tunnel-junction MTJ1 can include nailed layer PL, free layer FL and sandwiched tunneling barrier layer therebetween TBL.Nailed layer PL can be configured to fixed magnetisation direction, and free layer FL can be configured to changeable magnetization Direction (for example, or antiparallel parallel with the nailed layer PL direction of magnetization).First magnetic tunnel-junction MTJ1 can have electrical impedance, The electrical impedance depends on nailed layer PL and free layer FL opposite magnetization direction.In the first magnetic tunnel-junction MTJ1 nailed layer In the case that PL and free layer FL have the direction of magnetization parallel to each other, the first magnetic tunnel-junction MTJ1 can have low impedance state The state of (for example, with first impedance R1) or data ' 0 ' corresponding to the first data.Alternatively, in the first magnetic channel Knot MTJ1 nailed layer PL and free layer FL has in the state of the antiparallel direction of magnetization each other, the first magnetic tunnel-junction MTJ1 There can be the state of high impedance status (for example, with second impedance R2) or the data ' 1 ' corresponding to the second data.Example Such as, the first impedance R1 can be about 10k Ω, and the second impedance R2 can be about 40k Ω.

When performing write operation on the first memory cell MC1, cut-in voltage can be applied on wordline WL, and first Write-in voltage can be applied between the first magnetic tunnel-junction MTJ1 two ends.Depending on being applied to the first magnetic tunnel-junction MTJ1 On first write-in voltage polarity, the first reset current Iw1 or the second reset current Iw2 can flow through the first magnetic tunnel-junction MTJ1.First reset current Iw1 can flow upwardly through the first magnetic tunnel-junction from the first side from bit line BL1 to source electrode line SL MTJ1, and the second reset current Iw2 can flow upwardly through the first magnetic tunnel-junction from source electrode line SL to the first bit line BL1 side MTJ1.The free layer FL direction of magnetization can be changed using the spin-torque phenomenon for the electric charge for constituting reset current.In a word, lead to Cross and change through the direction of the first magnetic tunnel-junction MTJ1 reset current, it is possible to reversibly by the first memory cell MC1 electricity Impedance changes over one in the first and second impedance R1 and R2, and thus, the first memory cell MC1 can act as normally depositing Storage unit, its data can change several times.

As shown in figure 3, free layer FL and nailed layer PL can be connected respectively to the first bit line BL1 and first choice crystal Pipe SE1, but present inventive concept should not be limited to this.In at least some example embodiments, although not shown, nailed layer PL may be coupled to the first bit line BL1, and free layer FL may be coupled to first choice transistor SE1.Next, with reference to Fig. 4 A The first magnetic tunnel-junction MTJ1 is described in more detail with 4B.

Fig. 4 A and 4B be two kinds of the first magnetic tunnel-junction for showing some example embodiments according to present inventive concept not The schematic diagram of same type.

First magnetic tunnel-junction MTJ1 electrical impedance can depend on nailed layer PL and free layer FL opposite magnetization direction. For example, the first magnetic tunnel-junction MTJ1 electrical impedance can be in nailed layer PL and free layer FL direction of magnetization antiparallel each other (for example, be much larger than or considerably larger than) can be more than when they are parallel to each other.As a result, the first magnetic tunnel-junction MTJ1 resistance It is anti-to be controlled by changing the free layer FL direction of magnetization, and this may be used as some examples according to present inventive concept Data storage mechanism in the magnetic memory device of embodiment.

Reference picture 4A, nailed layer PL and free layer FL can be configured to magnetization configuration in face, for example, in them Each can be or including at least one magnetized layer, its direction of magnetization be arranged essentially parallel to tunneling barrier layer TBL top table Face.In this case, nailed layer PL can include the layer comprising antiferromagnetic materials and another layer comprising ferromagnetic material. In at least some example embodiments, the layer comprising antiferromagnetic materials can include PtMn, IrMn, MnO, MnS, MnTe, MnF₂、FeCl₂、FeO、CoCl₂、CoO、NiCL₂, at least one of NiO and Cr.In at least some example embodiments, bag Layer containing antiferromagnetic materials can include at least one of precious metal.The precious metal can include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), golden (Au) or silver-colored (Ag).On the contrary, the layer comprising ferromagnetic material can include CoFeB、Fe、Co、Ni、Gd、Dy、CoFe、NiFe、MnAs、MnBi、MnSb、CrO₂、MnOFe₂O₃、FeOFe₂O₃、NiOFe₂O₃、 CuOFe₂O₃、MgOFe₂O₃, EuO and Y₃Fe₅O₁₂At least one of.

Free layer FL can be configured to alterable or the changeable direction of magnetization.Free layer FL can include ferromagnetic Material.As an example, free layer FL can include FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂、MnOFe₂O₃、FeOFe₂O₃、NiOFe₂O₃、CuOFe₂O₃、MgOFe₂O₃, EuO and Y₃Fe₅O₁₂At least one of.

Free layer FL can include multiple layers.As an example, free layer FL can include multiple ferromagnetic layers and be interposed in iron Nonmagnetic layer between magnetosphere.In this case, ferromagnetic layer and nonmagnetic layer may be constructed synthetic anti-ferromagnetic structure.Synthesis is anti- The presence of ferromagnetic structure can allow magnetic memory device to have the critical current density and/or improved heat endurance reduced.

Tunneling barrier layer TBL can include magnesium oxide, titanium oxide, aluminum oxide, magnesium-zinc oxide, magnesium boron oxygen At least one of thing, titanium nitride and vanadium nitride.As an example, tunneling barrier layer TBL can be the magnesium oxide of individual layer (MgO).Alternatively, tunneling barrier layer TBL can include multiple layers.Tunneling barrier layer TBL can utilize chemical vapor deposition (CVD) technique is formed.

Reference picture 4B, nailed layer PL and free layer FL can be configured to perpendicular magnetization structure；For example, in them Each can be or including at least one magnetosphere, the magnetospheric direction of magnetization is orthogonal or is substantially normal to tunnel barrier Layer TBL top surface.In at least some example embodiments, each in nailed layer and free layer can include having L1₀The material of crystal structure, the material with close-packed hexagonal (HCP) structure and unsetting rare-earth transition metal (RE-TM) alloy At least one of.As an example, each in nailed layer PL and free layer FL can include at least one L1₀Material, Such as Fe₅₀Pt₅₀、Fe₅₀Pd₅₀、Co₅₀Pt₅₀、Co₅₀Pd₅₀And Fe₅₀Ni₅₀.In at least some example embodiments, nailed layer PL It can include unordered HCP cobalts-platinum (CoPt) alloy and orderly HCP Co with each in free layer FL₃At least one in Pt alloys Kind, the unordered HCP cobalt-platinum alloys include the platinum of about 10% to about 45% atomicity.In at least some example embodiments In, each in nailed layer PL and free layer and FL can include at least one amorphous RE-TM alloy and at least one Rare earth metal, the amorphous RE-TM alloy includes at least one of iron (Fe), cobalt (Co) and nickel (Ni), the rare earth gold The all terbiums in this way (Tb) of category, dysprosium (Dy) and ruthenium (Gd).

At least one in the nailed layer PL and free layer FL can be included with interface perpendicular magnetic anisotropic Material.Interface perpendicular magnetic anisotropic can refer to perpendicular magnetization phenomenon, this can be arranged in magnetosphere near another layer or with During this another layer contact, the magnetospheric interface of magnetization characteristic is seen in intrinsic face.Here, term is " in intrinsic face Magnetization characteristic " will be used to mean when no external magnetic field is applied thereto the magnetospheric direction of magnetization parallel to or substantially Parallel to its longitudinal direction orientation.For example, the magnetosphere of magnetization characteristic is formed on substrate and not had in intrinsic face In the case that external magnetic field is applied thereto, the magnetospheric direction of magnetization can parallel to or be arranged essentially parallel to the top table of substrate Planar orientation.

As an example, each in nailed layer PL and free layer FL can include cobalt (Co), iron (Fe) and nickel (Ni) At least one of.In addition, each in nailed layer PL and free layer FL may further include in nonmagnetic substance At least one, the nonmagnetic substance includes boron (B), zinc (Zn), aluminium (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), silver (Ag), golden (Au), copper (Cu), carbon (C) and nitrogen (N).As an example, each in nailed layer PL and free layer FL can be wrapped CoFe or NiFe layer are included, wherein adding boron (B).In addition, at least one in nailed layer PL and free layer FL can enter one Step includes at least one of titanium (Ti), aluminium (Al), magnesium (Mg), tantalum (Ta) and silicon (Si), to reduce its saturated magnetization.

Fig. 5 A and 5B are to schematically show the first subelement and according to some example embodiments of present inventive concept The view of two subelements.

Reference picture 5A, the first subelement MC2-1 can include the second magnetic tunnel-junction MTJ2 and work for acting as memory device With the second selection transistor SE2 for selection element.Second selection transistor SE2 gate electrode may be coupled to corresponding one Wordline WL, the second selection transistor SE2 source electrode may be coupled to a corresponding source electrode line SL, and the second selection transistor SE2 drain electrode can be connected to a corresponding second bit line BL2 by the second magnetic tunnel-junction MTJ2.Second magnetic tunnel-junction MTJ2 can include nailed layer PLa, free layer FLa and sandwiched tunnel barrier layer TBLa therebetween.Second magnetic channel Nailed layer PLa, the free layer FLa and tunneling barrier layer TBLa for tying MTJ2 can be by pinned with the first magnetic tunnel-junction MTJ1 Material layer PL, free layer FL identical or substantially the same with tunneling barrier layer TBL is formed.In other words, for example, the second magnetic tunnel Road knot MTJ2 can be or including variable-impedance device that its impedance can switch at least two by the electric pulse being applied to thereon One in individual state.

Reference picture 5B, the second subelement MC2-2 can be similar or substantially the same with the first subelement MC2-1, except Three magnetic tunnel-junction MTJ3 are used as its memory device.3rd magnetic tunnel-junction MTJ3 can include nailed layer PLa, free layer FLa and Sandwiched tunneling barrier layer TBLa1 therebetween.3rd magnetic tunnel-junction MTJ3 nailed layer PLa, free layer FLa and tunneling barrier Layer TBLa1 can by with the first magnetic tunnel-junction MTJ1 nailed layer PL, free layer FL and tunneling barrier layer TBL and/or second Material shape identical or substantially the same with tunneling barrier layer TBLa magnetic tunnel-junction MTJ2 nailed layer PLa, free layer FLa Into.Here, tunneling barrier layer TBLa1 may be at dielectric breakdown state or under blown state.Then, the 3rd magnetic tunnel-junction MTJ3 can have can not inverse impedance.

According at least some example embodiments, single programming operation can be performed to realize OTP memory cell.In list In secondary programming operation, the second write-in voltage can be applied in the second memory cell MC2 realized using the first subelement MC2-1 Some, and the 3rd write-in voltage can be applied to using the second subelement MC2-2 realize the second memory cell MC2 in its He.In other words, for example, the second write-in voltage can be applied on second of tunnel knot MTJ2 two ends, and the 3rd writes Entering voltage can be applied on the 3rd magnetic tunnel-junction MTJ3 two ends.Here, the second write-in voltage can be with being applied to the The first write-in voltage on one magnetic tunnel-junction MTJ1 two ends is identical or substantially the same, but the 3rd write-in voltage can be with More than (such as be much larger than or considerably larger than) first write-in voltage.For example, the 3rd write-in voltage can be selected to be more than the 3rd Magnetic tunnel-junction MTJ3 breakdown voltage.Then, the 3rd magnetic tunnel-junction MTJ3 tunneling barrier layer TBLa1 can be with breakdown.Meanwhile, Programming operation on the second memory cell MC2 can in advance be performed before the technique of encapsulation magnetic memory device.Second magnetic Tunnel knot MTJ2 can be programmed, with the direction depending on the second write-in voltage (for example, writing through the second magnetic tunnel-junction MTJ2 Enter sense of current) and with one in the first and second impedance R1 and R2.But, in subsequent heat treatment (for example, encapsulation Technique and/or annealing process) on magnetic memory device perform in the case of, the second magnetic tunnel-junction MTJ2 impedance can be changed Become.For example, the second magnetic tunnel-junction MTJ2 final impedance can have the 3rd resistance between the first and second impedance R1 and R2 Anti- R3.

As the result of above-mentioned single programming operation, the second magnetic tunnel-junction MTJ2, which can have, corresponds to data ' 1 ' state Or second data the 3rd impedance R3.Here, the 3rd impedance R3 can be between the first impedance R1 and the second impedance R2.Fuse shape The 3rd magnetic tunnel-junction MTJ3 under state can have and be less than (for example, be much smaller than or considerably smaller than) first impedance R1 and corresponding to number According to the 4th impedance R4 of ' 0 ' state or the first data.For example, the 4th impedance R4 can be less than or equal to about 1k Ω.

Fig. 6 is the example read operation for the first memory cell for showing some example embodiments according to present inventive concept Schematic circuit.

Selected first memory cell MC1 data can be from selected first memory cell MC1 and the first benchmark The difference determination of electrical impedance between unit R C1.Reference picture 6, the first reference cell RC1 can include being parallel to the first bit line respectively BL1 a pair of first magnetic tunnel-junction MTJ1 and a pair of first choice transistor SE1 for being connected in series to a pair of first magnetic tunnel-junction MTJ1. Being connected respectively to the first reference cell RC1 first choice transistor SE1 source electrode line SL can be electrically connected to each other.At least one In a little example embodiments, the first reference cell RC1 first choice transistor SE1 can have a shared source electrode line SL's Source electrode.

Before read operation, the first reference cell RC1 the first magnetic tunnel-junction MTJ1 can be programmed to have each other Different impedances.For example, the first reference cell RC1 one of them first magnetic tunnel-junction MTJ1 can be programmed to have first Impedance R1, and another can be programmed to have the second impedance R2.In this case, the first reference cell RC1 can have There is the impedance of about (R1+R2)/2.Extra programming operation can be performed on the first memory cell MC1 of selection, with choosing The the first memory cell MC1 memory storages selected correspond to the first impedance R1 or the second impedance R2 data.

In read operation, the first reading electric current Ir1 can be applied in the of the first memory cell MC1 to flow through selection One magnetic tunnel-junction MTJ1, simultaneously turns on the wordline WL that voltage is applied to the first memory cell MC1 of selection.Second reads electric current Ir2_1 and Ir2_2 can be applied in flow through the first reference cell RC1 the first magnetic tunnel-junction MTJ1, simultaneously turned on voltage and applied It is added to the first reference cell RC1 wordline WL.First sensing amplifier SA1 can be configured to sense and amplify the first storage list Difference between first MC1 and the first reference cell RC1 impedance, the impedance is read electric current Ir1 and second with first respectively and read Electric current Ir2_1 is associated with Ir2_2, and is determined for by the first sensing amplifier SA1 results obtained in selection The state of the data of first memory cell MC1 memory storages.In at least some example embodiments, the first sensing amplifier SA1 It can be the part for the first peripheral circuit PC1 that reference picture 2 is described.

There are that in the first memory cell MC1 of selection the first magnetic tunnel-junction MTJ1 free layer FL and nailed layer PL In the case of this parallel direction of magnetization, selected first memory cell MC1 can be interpreted to be in data ' 0 ' state. Alternatively, have in the first memory cell MC1 of selection the first magnetic tunnel-junction MTJ1 free layer FL and nailed layer PL Each other in the case of the antiparallel direction of magnetization, the first memory cell MC1 of selection can be interpreted to be in data ' 1 ' shape State.

Fig. 7 A and 7B are that the example for the second memory cell for showing some example embodiments according to present inventive concept is read The schematic circuit of extract operation.

Reference picture 7A, the second reference cell RC2 can be selected from the second subelement MC2_2.Then, the second reference cell RC2 can include the 3rd magnetic tunnel-junction MTJ3 with the 4th impedance R4.Second memory cell MC2 of selection can be the first son Unit MC2-1 or the second subelement MC2-2.In other words, the second memory cell MC2 of selection can include the second magnetic tunnel-junction MTJ2 or the 3rd magnetic tunnel-junction MTJ3.Then, selected second memory cell MC2 can have and the 3rd impedance R3 or the 4th Electrical impedance identical or substantially the same impedance R4.

Second memory cell MC2 of selection data can be from the second memory cell MC2 of selection and the second reference cell The difference of electrical impedance between RC2 is determined.Here, in order to increase sensing allowance, the second reference cell RC2 can be constructed such that Its electrical impedance is obtained between the 4th impedance R4 and the 3rd impedance R3.Therefore, control resistor Rct can be arranged on the second bit line BL2 is upper or between the second reference cell RC2 and the second sensing amplifier SA2.In other words, for example, the second reference cell RC2 The 3rd magnetic tunnel-junction MTJ3 may be electrically connected to control resistor Rct.Then, in read operation, the second reference cell RC2 There can be with the 3rd magnetic tunnel-junction MTJ3 the 4th impedance R4 and control resistor Rct the 5th impedance R5 sums identical or base (that is, R4+R5) identical in sheet.R4+R5 sums can be between the 4th impedance R4 and the 3rd impedance R3 (for example, about 7k Ω). In at least some example embodiments, the second sensing amplifier SA2 and control resistor Rct can be that reference picture 2 is described A second peripheral circuit PC2 part.

In read operation, third reading obtaining current Ir3 can be applied in of the second memory cell MC2 to flow through selection Two memory elements (for example, second or the 3rd magnetic tunnel-junction MTJ2 or MTJ3), simultaneously turn on voltage and are applied to the second of selection and deposit Storage unit MC2 wordline WL.4th reading electric current Ir4 can be applied in flow through the second reference cell RC2 the 3rd magnetic channel MTJ3 and control resistor Rct is tied, the wordline WL that voltage is applied to the second reference cell RC2 is simultaneously turned on.Second sensing amplification Device SA2 can be configured to sense and amplify the difference between the second memory cell MC2 and the second reference cell RC2 impedance, institute State impedance associated with the reading electric currents of third reading obtaining current Ir3 and the 4th Ir4 respectively, and obtained by the second sensing amplifier SA2 Result be determined for state in the data of the second memory cell MC2 memory storages of selection.

When selected second memory cell MC2 is the first subelement MC2-1, the second memory cell MC2 of selection can To be interpreted to be in data ' 1 ' state.Alternatively, when the second memory cell MC2 of selection is the second subelement MC2-2 When, the second memory cell MC2 of selection can be interpreted to be in data ' 0 ' state.

In at least some example embodiments, the second reference cell RC2 structure can be from the modification shown in Fig. 7 A. For example, acting as the 3rd magnetic tunnel-junction MTJ3 of memory element can be not arranged in the second reference cell RC2.

Reference picture 7B, the second reference cell RC2 can include the second selection transistor SE2.In this case, electricity is controlled The 5th impedance R5 for hindering device Rct can be between the 4th impedance R4 and the 3rd impedance R3.For example, the 5th of control resistor Rct the Impedance R5 can be about 7k Ω.In read operation, what third reading obtaining current Ir3 can be applied in flow through selection second deposits Storage unit MC2 the second memory element (such as second or the 3rd magnetic tunnel-junction MJT2 or MJT3), simultaneously turns on voltage and is applied to Second memory cell MC2 of selection wordline WL.4th reading electric current Ir4 can be applied in flow through control resistor Rct, the Two bit line BL2 and source electrode line SL, they are connected to the second reference cell RC2, simultaneously turn on voltage and are applied to the second reference cell On RC2 wordline WL.Second sensing amplifier SA2 can be configured to sense and amplify the second memory cell MC2 and the second base Difference between quasi- unit R C2 impedance, the impedance is associated with the reading electric currents of third reading obtaining current Ir3 and the 4th Ir4 respectively, And the second memory cell MC2 memory storages in selection are determined for by the second sensing amplifier SA2 results obtained Data state.

Otp memory part can be used for repairing semiconductor device.For example, otp memory part can be used for storage on half The information of the operating characteristic of conductor device, the operating characteristic is obtained by performing test technology on the semiconductor device, and And the information stored in otp memory part can be used for suppressing and/or prevent the failure of semiconductor devices.In addition, OTP is stored The other information that device can be used for needed for storage control semiconductor devices.For example, semiconductor devices can be made to have The physics and/or operating characteristic changed from Location-to-Location, and otp memory part can be configured to storage on semiconductor devices This change in location information.In this case, the information can be used for the storage array for controlling semiconductor devices.

According at least some example embodiments of present inventive concept, because a part for memory cell array is used for reality Existing OTP unit array, it is not necessary to form the other region for otp memory part.It is more highly integrated that this makes it possible to realization Magnetic memory device.In addition, the method by forming short circuit in the magnetic tunnel-junction as the memory element of memory cell, OTP memory cell can be realized more easily.In addition, by the way that reference cell and periphery for OTP memory cell is provided separately Circuit, it is possible to improve and/or optimize the read/write operations in OTP memory cell.This makes it possible to realize that more height can The magnetic memory device leaned on.

Fig. 8 A are the planes of the example for the magnetic memory device for showing some example embodiments according to present inventive concept Figure.Fig. 8 B are the profiles along Fig. 8 A line A-A ' and B-B ' interception.Fig. 8 C are line C-C ', D-D ' and the E-E ' along Fig. 8 A The profile of interception.

Reference picture 8A to 8C, can prepare the substrate 100 including cell array region CR and peripheral circuit area PR.Substrate 100 can be silicon wafer, germanium eyeglass and/or silicon-germanium eyeglass, but present inventive concept is not limited to this.Cell array region CR First module array region CR1 and second unit array region CR2 can be included.Fig. 2 the first memory cell array 10a can be with It is arranged on first module array region CR1, and Fig. 2 the second memory cell array 10b can be arranged on second unit array On the CR2 of region.Peripheral circuit area PR can include the first peripheral circuit area PR1 and the second peripheral circuit area PR2.Fig. 2 The first peripheral circuit PC1 can be arranged on the first peripheral circuit area PR1, and Fig. 2 the second peripheral circuit PC2 can be set Put on the second peripheral circuit area PR2.

Device isolation pattern 102 can be arranged in substrate 100.First and second cell array region CR1 and CR2 device Part isolation pattern 102 can limit active line pattern ALP.First and second cell array region CR1 and CR2 device isolation figure Case 102 and active line pattern ALP can be arranged in the first direction dl.When being observed in plan, the battle array of Unit first and second Column region CR1 and CR2 device isolation pattern 102 and active line pattern ALP can be in the second directions through first direction D1 Extend on D2.Active line pattern ALP can be doped with the first conduction type.

First periphery active part PA1 and the second periphery active part PA2 can be limited by device isolation pattern 102, The device isolation pattern is separately positioned on the first and second peripheral circuit area PR1 and PR2.First periphery active part PA1 and the second periphery active part PA2 can be doped with the first conduction type and different from the first conduction type Two conduction types.

On the first and second cell array region CR1 and CR2, isolation sunk area 104 can be disposed through active Line pattern ALP and device isolation pattern 102.When observing in plan view, isolation sunk area 104 can be with D1 in a first direction It is upper to extend and be shaped like groove.Each active line pattern ALP can be divided into multiple units by isolation sunk area 104 Active part CA.Unit active part CA can be active line pattern ALP some, and the multiple part is positioned at isolation Between sunk area 104.In other words, for example, each unit active part CA can pass through adjacent pairs of device isolation pattern 102 and adjacent pairs of isolation sunk area 104 limit.When observing in plan view, unit active part CA can be Two-dimensional arrangement on first direction D1 and second direction D2.

At least one gate recess region 103 can be disposed through multiple unit active part CA, and it is in a first direction Arranged on D1.Gate recess region 103 can parallel to or be arranged essentially parallel to isolation sunk area 104 extend.At least one In a little example embodiments, at least one pair of gate recess region 103 can be disposed through the list set in the first direction dl First active part CA.In this case, a pair of cell transistors can be respectively formed on unit active part CA.First is single Element array region CR1 cell transistor can correspond to the first choice transistor SE1 of the description of reference picture 2 and 3, and the second list Element array region CR2 cell transistor can correspond to the second selection transistor SE2 of reference picture 2,5A and 5B descriptions.

Gate recess region 103 can have basal surface, and the basal surface is positioned at the basal surface with isolating sunk area 104 In identical or substantially the same height.The basal surface of gate recess region 103 and isolation sunk area 104 can be positioned at than the One and second unit array region CR1 and CR2 device isolation pattern 102 the higher height of basal surface at.

Wordline WL can be separately positioned in gate recess region 103.Cell gate dielectric layer 105 can be arranged on wordline Between WL and the inner surface in each gate recess region 103.Because wordline WL is arranged in gate recess region 103, wordline WL Can be in the first direction dl or parallel to the linear structure of the extension of gate recess region 103.Cell transistor can include Wordline WL and the channel region being recessed by gate recess region 103.

Shielding wire IL can be separately positioned in isolation sunk area 104.Isolated gate dielectric layer 106 can be arranged on every Between the inner surface of offline IL and each isolation sunk area 104.Shielding wire IL can also extend in the first direction dl Linear structure.

Unit cover pattern 108 can be separately positioned on wordline WL and shielding wire IL.Unit cover pattern 108 can be arranged on In grid and isolation sunk area 103 and 104.Unit cover pattern 108 can have top surface, the top surface and substrate 100 Top surface is coplanar or substantially coplanar.

When magnetic memory device is operated, isolation voltage can be applied on shielding wire IL.Isolation voltage can be chosen To suppress and/or prevent channel region formation under shielding wire IL or isolation sunk area 104.In other words, for example, by Shielding wire IL applies isolation voltage, and the isolation channel region under shielding wire IL may be at non-conductive state.Then, unit Active part CA can be with electrically separated from each other.In the case where active line pattern ALP is p-type, isolation voltage can be ground voltage Or negative voltage.

Wordline WL can include the semi-conducting material silicon of doping (for example) of such as doping, metal material (for example, tungsten, Aluminium, titanium and/or tantalum), conductive metal nitride (for example, titanium nitride, tantalum nitride and/or tungsten nitride) and metal semiconductor At least one of compound (for example, metal silicide).In at least some example embodiments, shielding wire IL can by with Material identical or substantially the same wordline WL is formed.Unit and isolated gate dielectric layer 105 and 106 can be aoxidized by such as silicon Thing, silicon nitride, silicon nitrogen oxides and/or the high k including insulating metal oxide (for example, hafnium oxide or aluminum oxide) are situated between Electric material formation includes these materials.Unit cover pattern 108 can be by Si oxide, silicon nitride and silicon nitrogen oxides At least one of formed or including at least one of Si oxide, silicon nitride and silicon nitrogen oxides.

First and second extrinsic regions 111 and 112 can be arranged in unit active part CA and between wordline WL Or between wordline WL and shielding wire IL.For example, the first extrinsic region 111 can be formed in unit active part CA in wordline WL Between, and the second extrinsic region 112 can be formed in unit active part CA between wordline WL and shielding wire IL.Then, First extrinsic region 111 can be shared by a pair of cell transistors, and the pair of cell transistor is in each unit active part On CA.First and second extrinsic regions 111 and 112 can correspond to the regions and source/drain of cell transistor.First and second Extrinsic region 111 and 112 can be doped, with the second conduction type.One in first and second conduction types can be with It is n-type, and another can be p-type.

First periphery gates dielectric layer 114a, the first periphery gate electrode 116a and the first peripheral cover pattern 118a can be successively It is layered on the first peripheral circuit area PR1 the first periphery active part PA1.First periphery regions and source/drain 120a can Be arranged on the first periphery active part PA1 respectively positioned at the first periphery gate electrode 116a both sides at separated region in. First periphery gates sept 122a can be arranged on the first periphery gate electrode 116a two side.First periphery source/drain Polar region domain 120a can be doped with dopant, with the conduction type different from the first periphery active part PA1.Different from list First transistor, including the first periphery gate electrode 116a the first peripheral transistor can include planar channeling region.In other words, For example, the first peripheral transistor can be the transistor of plane type.But, present inventive concept is not limited to this.For example, extremely In some few example embodiments, the first periphery gate electrode 116a can be arranged to the electrode knot for Fin-FET devices Structure.First peripheral transistor can be PMOS or nmos pass transistor.

Second periphery gate dielectric 114b, the second periphery gate electrode 116a and the second peripheral cover pattern 118b can be according to It is secondary to be layered on second week side circuit region PR2 the second periphery active part PA2.Second periphery regions and source/drain 120b The Disengagement zone of the second periphery active part PA2 two ends for being located at the second periphery gate electrode 116b respectively can be arranged on In domain.Second periphery grid spacer 122b can be arranged on the second periphery gate electrode 116b two side walls.Second periphery Regions and source/drain 120b can be doped with dopant, with the conduction type different from the second periphery active part PA2. The second peripheral transistor with the second periphery gate electrode 116b can be arranged to have with the first peripheral transistor identical or base Identical shape in sheet.In other words, for example, the second peripheral transistor can be arranged to the form of planar transistor.But, this Inventive concept should not be limited to this.In at least some example embodiments, the second periphery gate electrode 116b can have with The identical or substantially the same structure of the gate electrode of fin-FET devices.Second peripheral transistor can be PMOS or NMOS crystal Pipe.

In at least some example embodiments, the first peripheral transistor can be low voltage transistor, and it is in low operation electricity Pressing operation, and the second peripheral transistor can be high voltage transistor, it is operated under high operation voltage.Second peripheral transistor It can be arranged to that there is the channel region longer than the first peripheral transistor, and this makes it possible to suppress and/or prevented the Break-through (punch-through) phenomenon occurs in two peripheral transistors.For example, the second periphery gate electrode 116b the second width W2 The first periphery gate electrode 116a the first width W1 can be more than.In addition, the gate dielectric of the second peripheral transistor can be with shape As thicker than the first peripheral transistor, and this can allow the second peripheral transistor has the breakdown voltage of increase.Example Such as, or even when big electrical potential difference is applied between the second periphery gate electrode 116b and the second periphery regions and source/drain 120b, the Puncturing for the gate dielectric of two peripheral transistors can be suppressed and/or prevent.In other words, for example, the second periphery gates Dielectric layer 114b second thickness t2 can be more than the first periphery gates dielectric layer 114a first thickness t1.

Each of first and second periphery gates dielectric layer 114a and 114b by silicon oxide layer and can include metal At least one formation in the high k dielectric layer of oxide (for example, hafnium oxide or aluminum oxide), or including silicon oxide layer and At least one in high k dielectric layer comprising metal oxide (for example, hafnium oxide or aluminum oxide).In at least some examples In embodiment, the first periphery gates dielectric layer 114a can be formed by the silicon oxide layer of relative thin, and the second periphery gates Dielectric layer 114b can be formed by the silicon oxide layer of relative thick.In at least some example embodiments, the first periphery gates Dielectric layer 114a can be single high k dielectric layer, and the second periphery gate dielectric 114b can be include silicon oxide layer and The bilayer of high k dielectric layer.First and second periphery gate electrode 116a and 116b can be formed by least one of following material Or including at least one of following material：For example, the semi-conducting material (for example, silicon of doping) of doping, metal material (example Such as, tungsten, aluminium, titanium and/or tantalum), conductive metal nitride (for example, titanium nitride, tantalum nitride and/or tungsten nitride) and gold Category-semiconducting compound (for example, metal silicide).First and second peripheral cover pattern 118a and 118b can be aoxidized by silicon At least one of thing, silicon nitride and silicon nitrogen oxides are formed or including in Si oxide, silicon nitride and silicon nitrogen oxides At least one.First and second periphery gates sept 122a and 122b can be by Si oxide, silicon nitride and silicon nitrogen oxygen At least one of compound is formed or including at least one of Si oxide, silicon nitride and silicon nitrogen oxides.

Impedance pattern 124 can be arranged on the second peripheral circuit area PR2 device isolation pattern 102.Impedance pattern 124 can include semi-conducting material.For example, impedance pattern 124 can include silicon, germanium or SiGe.Implement at least some examples In mode, impedance pattern 124 can include polycrystalline semiconductor material.Impedance pattern 124 can doped with n-type or p-type dopant, And the resistivity of impedance pattern 124 can be controlled by changing the doping concentration of impedance pattern 124.Impedance pattern 124 Whole part can be homogeneously doped with dopant.Alternatively, impedance pattern 124 can be partly doped with dopant.Insulation Sept 126 can be arranged on the side wall of impedance pattern 124, and protects insulating pattern 128 to be arranged on impedance pattern On 124 top surface.Each in insulation spacer 126 and protection insulating pattern 128 can be by Si oxide, silicon nitride Formed with least one of silicon nitrogen oxides or including at least one of Si oxide, silicon nitride and silicon nitrogen oxides. Impedance pattern 124 can correspond to the control resistor Rct of reference picture 7A and 7B description.

First interlayer dielectric layer 130 can be arranged on cell array region CR and peripheral circuit area PR substrate 100. First peripheral circuit area PR1 the first interlayer dielectric layer 130 can cover the first peripheral transistor, and the second periphery circuit region Domain PR2 the first interlayer dielectric layer 130 can cover the second peripheral transistor and impedance pattern 124.First interlayer dielectric layer 130 Can be formed by least one of Si oxide, silicon nitride and silicon nitrogen oxides or including Si oxide, silicon nitride and At least one of silicon nitrogen oxides.Source electrode line SL can be disposed through the first and second cell array region CR1's and CR2 First interlayer dielectric layer 130 is simultaneously contacted with substrate 100.Source electrode line SL can extend in the first direction dl.Each source electrode line SL The first extrinsic region 111 can be electrically coupled to, D1 extends first extrinsic region 111 along a first direction.Source electrode line SL can be with With top surface, the top table of the top surface and the first and second cell array region CR1 and CR2 the first interlayer dielectric layer 130 Face is coplanar or substantially coplanar.Source electrode line SL can include at least one of following material：For example, the semi-conducting material of doping The silicon of doping (for example), metal material (for example, tungsten, aluminium, titanium and/or tantalum), conductive metal nitride (for example, titanium nitride, Tantalum nitride and/or tungsten nitride) and metal-semiconductor compound (for example, metal silicide).

Second interlayer insulating film 140 can be arranged on the first interlayer dielectric layer 130.Second interlayer insulating film 140 can be with Including at least one of Si oxide, silicon nitride and silicon nitrogen oxides.On first module array region CR1, first connects Both the second and first interlayer dielectric layers 140 and 130 can be disposed through by touching connector 142.First contact plunger 142 can divide First module array region CR1 the second extrinsic region 112 is not electrically coupled to.On second unit array region CR2, second connects The two of the second and first interlayer dielectric layer 140 and 130 can be disposed through by touching connector 144.Second contact plunger 144 can be with Second unit array region CR2 the second extrinsic region 112 is electrically coupled to respectively.In at least some example embodiments, the One and second contact plunger 142 and 144 can be formed by the conductive material identical or essentially identical with source electrode line SL, but this hair Bright design should not be limited to this.First and second contact plungers 142 and 144 can have the top with the second interlayer insulating film 140 Surface co-planar or substantially coplanar top surface.

First memory element ME1 can be arranged on first module array region CR1 the second interlayer insulating film 140. When being seen in plan, the first memory element ME1 can be overlapping with the first contact plunger 142 respectively.In other words, for example, first Memory element ME1 can be respectively coupled to the first contact plunger 142.First memory element ME1 can pass through the first contact plunger 142 are electrically connected to first module array region CR1 the second extrinsic region 112.When observing in plan view, the first storage member Part ME1 can be with two-dimensional arrangement on D1 in a first direction and second direction D2.First memory element ME1 can correspond to reference picture 2, 3rd, the first memory element ME1 of 4A, 4B and 7A description.In other words, for example, each in the first memory element ME1 can be with Including the first magnetic tunnel-junction MTJ1.First magnetic tunnel-junction MTJ1 can be configured to have and same as described above or basic phase Same feature, therefore its detailed description will be omitted.Some first memory element ME1 may be constructed the first memory cell MC1, and its His the first memory element ME1 may be constructed the first reference cell RC1.In addition, each first memory element ME1 can enter one Step includes the first bottom electrode BE1 and the first top electrodes TE1.First magnetic tunnel-junction MTJ1 can be arranged on the first bottom electrode Between BE1 and the first top electrodes TE1.In other words, for example, the first bottom electrode BE1 can be arranged on the first contact plunger 142 and first between magnetic tunnel-junction MTJ1, and the first top electrodes TE1 can be arranged on the first magnetic tunnel-junction MTJ1.First In bottom electrode BE1 and the first top electrodes TE1 each can include conductive metal nitride (for example, titanium nitride or Tantalum nitride), at least one in transition metal (for example, titanium or tantalum) and rare earth metal (such as ruthenium or platinum).

Second memory element ME2 can be arranged on second unit array region CR2 the second interlayer insulating film 140.When When observing in plan view, the second memory element ME2 can be overlapping with the second contact plunger 144 respectively.In other words, for example, Second memory element ME2 is respectively coupled to the second contact plunger 144.Second memory element ME2 can pass through the second contact plunger 144 are electrically connected to second unit array region CR2 the second extrinsic region 112.When observing in plan view, the second storage member Part ME2 can be with D1 along a first direction and second direction D2 two-dimensional arrangements.Second memory element ME2 can correspond to reference picture 2, Second memory element ME2 of 5A, 5B and 7A description.In other words, for example, some second memory element ME2 can include second Magnetic tunnel-junction MTJ2, and other second memory element ME2 can include the 3rd magnetic tunnel-junction MTJ3.Second and the 3rd magnetic channel Knot MTJ2 and MTJ3 can be configured to have with same as described above or substantially the same feature, and therefore will omit it Detailed description.Some second memory element ME2 may be constructed the second memory cell MC2, and other second memory elements ME2 may be constructed the second reference cell RC2.In addition, each second memory element ME2 may further include the second bottom electrode BE2 and the second top electrodes TE2.Second and the 3rd each in magnetic tunnel-junction MTJ2 and MTJ3 can be arranged on the second bottom Between electrode B E2 and the second top electrodes TE2.Second bottom electrode BE2 and the second top electrodes TE2 can be included respectively with the Material identical or substantially the same with the first top electrodes TE1 one bottom electrode BE1.

Insulating barrier 150 can be arranged on the second interlayer insulating film 140 between third layer.First and second cell array regions Insulating barrier 150 can be contacted with the first and second memory element ME1 and ME2 side wall between CR1 and CR2 third layer.In addition, the One and second unit array region CR1 and CR2 third layer between insulating barrier 150 can be arranged to exposure first and second storage member Part ME1 and ME2 top surface.Insulating barrier 150 can be in Si oxide, silicon nitride and silicon nitrogen oxides extremely between third layer Few one kind is formed or including at least one of Si oxide, silicon nitride and silicon nitrogen oxides.

On the first peripheral circuit area RP1, the first periphery connector 152 can be disposed through first and be situated between third layer Electric layer 130,140 and 150 is simultaneously contacted with substrate 100.First periphery connector 152 can be electrically coupled to the first periphery source/drain Region 120a.On the second peripheral circuit area PR2, the second periphery connector 154 can be disposed through first between third layer Dielectric layer 130,140 and 150, and contacted with substrate 100.Second periphery connector 154 can be electrically coupled to the second periphery source/drain Polar region domain 120b.3rd periphery connector 156 can be disposed through the first of the second peripheral circuit area PR2 and be situated between third layer Electric layer 130,140 and 150 and protection insulating pattern 128, it is possible to be electrically connected to impedance pattern 124.Insert on the first to the 3rd periphery Plug 152,154,156 can consist essentially of the conductive material identical or substantially the same with source electrode line SL.

First bit line BL1 can be arranged between first module array region CR1 third layer on insulating barrier 150.First Line BL1 can extend in a second direction d 2.Each first bit line BL1 can be commonly connected to many of the arrangement of D2 in a second direction On individual first memory element ME1.Second bit line BL2 can be arranged on insulating barrier between second unit array region CR2 third layer On 150.Second bit line BL2 can extend in a second direction d 2.Each second bit line BL2 can be commonly connected to along second On multiple second memory element ME2 of direction D2 arrangements.First and second bit line BL1 and BL2 can by metal material (for example, Copper or aluminium) formed or including the metal material.

First conductor wire L1 can be arranged between the first peripheral circuit area PR1 third layer on insulating barrier 150.First leads Electric wire L1 can be electrically coupled to the first periphery connector 152 respectively.Second conductor wire L2 can be arranged on the second peripheral circuit area Between PR2 third layer on insulating barrier 150.Second conductor wire L2 can be electrically coupled to the second periphery connector 154 respectively.3rd is conductive Line L3 can be arranged between the second peripheral circuit area PR2 third layer on insulating barrier 150.3rd conductor wire L3 can be electrically connected To the 3rd periphery connector 156.First to the 3rd conductor wire L1, L2 and L3 can include and the first and second bit line BL1 and BL2 phases Same or substantially the same material.

First module array region CR1 cell transistor and the first memory element ME1 can by the first bit line BL1 and First conductor wire L1 is electrically connected to the first periphery regions and source/drain 120a of the first peripheral transistor.Second unit array area Domain CR2 cell transistor and the second memory element ME2 can be electrically connected to by the second bit line BL2 and the second conductor wire L2 Second periphery regions and source/drain 120b of two peripheral transistors.In addition, constituting the second reference cell RC2 second unit battle array Column region CR2 cell transistor and the second memory element ME2 can be electrically connected by the second bit line BL2 and the 3rd conductor wire L3 To impedance pattern 124.

Fig. 9 A are the planes of the example for the magnetic memory device for showing some example embodiments according to present inventive concept Figure.Fig. 9 B are the profiles along Fig. 9 A line A-A ' and B-B ' interception.Fig. 9 C are line C-C ', D-D ' and the E-E ' along Fig. 9 A The profile of interception.Fig. 9 A to 9C magnetic memory device can be configured to the magnetic memory device class with Fig. 8 A to 8C Like or substantially the same feature, except some second memory element ME2 are substituted with the 3rd contact plunger 146.In order to describe letter Clean, previously described element can be identified by similar or same reference numerals, without repeating their overlapping descriptions.

Reference picture 9A to 9C, the 3rd contact plunger 146 can be disposed through first to insulating barrier between third layer 130,140 It can be connected with some in 150, and second unit array region CR2 the second extrinsic region 112 by the 3rd contact plunger 146 It is connected to the second bit line BL2.In other words, for example, second unit array region CR2 some cell transistors may be electrically connected to Second bit line BL2, without second unit element ME2.The second bit line BL2 list is electrically connected to by the 3rd contact plunger 146 First transistor can correspond to the second reference cell RC2 of reference picture 7B descriptions.It is multiple at least some example embodiments Second reference cell RC2 can be arranged along second direction D2 and can be shared a corresponding second bit line BL2.

According at least some example embodiments of present inventive concept, because a part of memory cell array is used to realize OTP unit array, it may not be necessary to form the additional areas for otp memory part.It is higher that this can make it possible to realization The integrated magnetic memory device of degree.In addition, by forming short circuit in the magnetic tunnel-junction as the memory element of memory cell Method, OTP memory cell can be realized more easily.In addition, by be provided separately for OTP memory cell reference cell and Peripheral circuit, it is possible to improve and/or optimize the read/write operations in OTP memory cell.This can make it possible to reality Existing more highly reliable magnetic memory device.

Although being specifically illustrating and having described some example embodiments of present inventive concept, people in the art Member on the premise of the spirit and scope without departing substantially from appended claims it will be appreciated that can make form and details wherein On change.

This application claims the korean patent application 10- submitted in Korean Intellectual Property Office on October 15th, 2015 No. 2015-0144117 and the priority for the korean patent application the 10-2015-0160551st submitted on November 16th, 2015, The full content of the earlier application is incorporated herein by reference.

Claims (25)

1. a kind of semiconductor devices, including：

Multiple wordline；

Through multiple bit lines of the multiple wordline, the multiple bit line includes the first bit line and the second bit line, the second Line is opened on the direction that the multiple wordline extends with first bit line spacer；

Multiple first memory cell, the multiple first memory cell be connected to the multiple wordline and first bit line it Between, each in multiple first memory cell includes the first memory element and first choice element, first memory element It is connected to each other with first choice element；And

Multiple second memory cell, the multiple second memory cell be connected to the multiple wordline and second bit line it Between, each in the multiple memory cell includes the second memory element and the second selection element, second memory element It is connected to each other with second selection element；

Wherein, first memory element includes the first magnetic tunnel-junction, and second memory element includes the second magnetic tunnel-junction, Each in first and second magnetic tunnel-junction include nailed layer, free layer and the nailed layer and free layer it Between tunneling barrier layer；And

The tunneling barrier layer of the Part I of wherein described second magnetic tunnel-junction has irreversible impedance state.

2. device as claimed in claim 1, wherein：

The multiple first memory cell be it is re-writable enter memory cell；

The multiple second memory cell is one-time programmable memory.

3. device as claimed in claim 1, wherein：

First magnetic tunnel-junction have it is re-writable enter structure, and be configured to (i) correspond to the first data first resistance Anti- and (ii) is corresponding to one in the second impedance of the second data；

At least one second magnetic tunnel-junction in the Part I of second magnetic tunnel-junction, which has, corresponds to described the 3rd impedance of one data, and at least one described second magnetic tunnel-junction is programmed by the first single programming operation；

At least one other second magnetic tunnel-junction in the Part I of second magnetic tunnel-junction, which has, corresponds to institute The 4th impedance of the second data is stated, at least one other second tunnel knot is compiled by the second single programming operation Journey；And

First to fourth impedance is different from each other.

4. device as claimed in claim 3, wherein：

First impedance is less than second impedance；

3rd impedance is less than first impedance；And

4th impedance is between first and second impedance.

5. device as claimed in claim 3, wherein：

One or more of the multiple first memory cell is configured in the multiple first memory cell One or more first reference cells of read operation；And

One or more of the multiple second memory cell is configured in the multiple second memory cell One or more second reference cells of read operation.

6. device as claimed in claim 5, wherein：

One or more of the multiple first memory cell includes one or more pairs of first memory cell；And

A pair of first memory cell in the pair of or multipair first memory cell are parallel to one of them described first Line.

7. device as claimed in claim 6, wherein：

First magnetic tunnel-junction of the first memory cell in the pair of first memory cell is programmed with the first impedance； And

First magnetic tunnel-junction of another the first memory cell in the pair of first memory cell is programmed with Two impedances.

8. device as claimed in claim 5, wherein, one or more of second reference cells are to include the second magnetic tunnel Second memory cell of road knot.

9. device as claimed in claim 8, in addition to：

It is electrically connected to the control resistor of one or more of second reference cells；Wherein

Reference impedance for the read operation in the multiple second memory cell is the 3rd impedance and the control 5th impedance sum of resistor.

10. device as claimed in claim 9, wherein, the 3rd and the 5th impedance sum is in the 3rd impedance and described Between 4th impedance.

11. device as claimed in claim 1, in addition to：

The first peripheral circuit of the multiple first memory cell is electrically connected to by first bit line；And

The second peripheral circuit of the multiple second memory cell is electrically connected to by second bit line,

Wherein, second peripheral circuit includes at least one second peripheral transistor, at least one described peripheral transistor quilt It is configured to according to the voltage operation higher than the first peripheral transistor of first peripheral circuit.

12. device as claimed in claim 11, wherein：

First peripheral transistor includes the first periphery gates dielectric layer and the first periphery gate electrode；

At least one described second peripheral transistor includes the second periphery gate dielectric and the second periphery gate electrode；And

Second periphery gate dielectric has the thickness of the thickness more than the first periphery gates dielectric layer.

13. device as claimed in claim 12, wherein, second periphery gate electrode, which has, is more than first periphery grid electricity The width of the width of pole.

14. a kind of semiconductor devices, including：

Memory cell array, the memory cell array includes Reprogrammable cellular array and single programmable (OTP) unit Array；

The first peripheral circuit of the Reprogrammable cellular array is electrically connected to by the first bit line；

The second peripheral circuit of the single programmable cellular array is electrically connected to by the second bit line；Wherein：

The Reprogrammable cellular array includes each in multiple first memory cell, the multiple first memory cell Including the first magnetic tunnel-junction and first choice transistor, first magnetic tunnel-junction and the first choice transistor connect each other Connect；

The single programmable cellular array includes each in multiple second memory cell, the multiple second memory cell It is individual to connect each other including the second magnetic tunnel-junction and the second selection transistor, second magnetic tunnel-junction and second selection transistor Connect；And

The Part I of second magnetic tunnel-junction has irreversible impedance state.

15. device as claimed in claim 14, wherein：

First magnetic tunnel-junction have it is re-writable enter structure, and (i) correspond to the first data first impedance and (ii) it is right Should be in one in the second impedance of the second data；

At least one second magnetic tunnel-junction in the Part I of second magnetic tunnel-junction, which has, corresponds to described the At least one described second magnetic tunnel-junction in 3rd impedance of one data, the Part I of second magnetic tunnel-junction leads to Cross the first single programming operation programmed；

At least one second magnetic tunnel-junction in the Part II of second magnetic tunnel-junction has the corresponding to second data At least one described second magnetic tunnel-junction in four impedances, the Part II of second magnetic tunnel-junction passes through the second single Programming operation is programmed；

First impedance is less than second impedance；

3rd impedance is less than first impedance；And

4th impedance is between first and second impedance.

16. device as claimed in claim 15, wherein

One or more of the multiple first memory cell the first memory cell is configured to the multiple first One or more first reference cells of read operation in memory cell；And

One or more of the multiple second memory cell the second memory cell is configured to the multiple second One or more second reference cells of read operation in memory cell.

17. device as claimed in claim 16, wherein

Second peripheral circuit includes the control resistor for being electrically connected to one or more of second reference cells；And

Reference impedance for the read operation in the multiple second memory cell is the 3rd impedance and the control The impedance sum of resistor.

18. device as claimed in claim 15, wherein：

One or more of the multiple first memory cell is configured on the multiple first reference cell One or more reference cells of read operation；

The single programmable cellular array also includes being used for the of read operation in the multiple second memory cell Two reference cells；And

Second reference cell include the 3rd selection transistor, the 3rd selection transistor be connected to one of them described second Bit line, and the variable impedance do not arranged between the 3rd selection transistor and second bit line of one of them Device.

19. device as claimed in claim 18, wherein：

Second peripheral circuit includes the control resistor for being electrically connected to second reference cell；And

Reference impedance for the read operation in the multiple second memory cell is the impedance of the control resistor.

20. device as claimed in claim 14, wherein

First peripheral circuit includes at least one first peripheral transistor；

Second peripheral circuit includes at least one second peripheral transistor；And

At least one described second peripheral transistor is configured in response to higher than at least one described first peripheral transistor Voltage is operated.

21. a kind of semiconductor devices, including：

Memory cell array, the memory cell array includes the array and the second magnetic memory cell of the first magnetic memory cell Array, each in first magnetic memory cell includes the first magnetic tunnel junction structure with reversible impedance state, And each in second magnetic memory cell includes the second magnetic tunnel-junction with single programmable (OTP) impedance state Structure.

22. device as claimed in claim 21, wherein：

First magnetic tunnel junction structure and second magnetic tunnel junction structure have identical Rotating fields；And

The Rotating fields include pinned magnetosphere, free magnetic layer and in the pinned magnetosphere and the free magnetic layer Between tunneling barrier layer.

23. device as claimed in claim 21, wherein, second magnetic tunnel junction structure is configured to be set to irreversible Dielectric breakdown state.

24. device as claimed in claim 23, wherein：

First magnetic tunnel junction structure includes：

The first nailed layer with the first pinned direction of magnetization；

The first tunneling barrier layer on first nailed layer；And

The first free layer on first tunneling barrier layer, first free layer has the first changeable magnetization direction；And

Second magnetic tunnel junction structure includes：

The second nailed layer with the second pinned direction of magnetization；

The second tunneling barrier layer on second nailed layer, the second tunneling barrier layer is set to irreversible dielectric Breakdown conditions；And

The second free layer on second tunneling barrier layer, second free layer has the second changeable magnetization direction.

25. device as claimed in claim 21, in addition to：

First peripheral circuit, first peripheral circuit includes multiple the first transistors, and first peripheral circuit is configured to Apply first voltage to first magnetic memory cell；And

Second peripheral circuit, second peripheral circuit includes multiple second transistors, and second peripheral circuit is configured to Apply second voltage to second magnetic memory cell；Wherein

The multiple second transistor has the threshold voltage of the threshold voltage more than the multiple the first transistor；And

The second voltage is more than the first voltage.