KR101077380B1 - 인쇄회로기판 및 그 제조방법 - Google Patents
인쇄회로기판 및 그 제조방법 Download PDFInfo
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- KR101077380B1 KR101077380B1 KR1020090070634A KR20090070634A KR101077380B1 KR 101077380 B1 KR101077380 B1 KR 101077380B1 KR 1020090070634 A KR1020090070634 A KR 1020090070634A KR 20090070634 A KR20090070634 A KR 20090070634A KR 101077380 B1 KR101077380 B1 KR 101077380B1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0108—Male die used for patterning, punching or transferring
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (17)
- 절연부재의 일면에 함침된 회로패턴;상기 절연부재의 일면에 적층된 빌드업 절연층에 상기 회로패턴과 연결되는 비아를 포함하는 회로층이 형성된 빌드업층; 및상기 빌드업층에 적층된 솔더 레지스트층을 포함하고, 상기 절연부재에는 상기 회로패턴 중 제2패드부를 노출시키는 제2오픈부가 형성되고, 상기 노출된 제2패드부에는 외부접속단자가 형성된 것을 특징으로 하는 인쇄회로기판.
- 청구항 1에 있어서,상기 절연부재의 일면에는 임프린팅 공법에 의해 패턴용 트렌치가 형성되고, 상기 회로패턴은 상기 패턴용 트렌치의 내부에 형성되는 것을 특징으로 하는 인쇄회로기판.
- 절연부재의 일면에 함침된 회로패턴;상기 절연부재의 일면에 적층된 빌드업 절연층에 상기 회로패턴과 연결되는 비아를 포함하는 회로층이 형성된 빌드업층;상기 빌드업층에 적층된 솔더 레지스트층; 및상기 회로패턴과 연결되되, 상기 절연부재의 타면에 노출되도록 형성된 범프패드를 구비하고, 상기 범프패드에는 외부접속단자가 형성된 것을 특징으로 하는 인쇄회로기판.
- 청구항 3에 있어서,상기 범프패드의 노출면에는 표면처리층이 형성되어 있는 것을 특징으로 하는 인쇄회로기판.
- 청구항 3에 있어서,상기 절연부재에는 패턴용 트렌치와 상기 절연부재를 관통하도록 가공된 범프패드용 트렌치가 형성되고, 상기 회로패턴은 상기 패턴용 트렌치의 내부에 형성되고, 상기 범프패드는 상기 범프패드용 트렌치의 내부에 형성되는 것을 특징으로 하는 인쇄회로기판.
- 절연부재의 일면에 함침된 회로패턴;상기 절연부재의 일면에 적층된 빌드업 절연층에 상기 회로패턴과 연결되는 비아를 포함하는 회로층이 형성된 빌드업층;상기 빌드업층에 적층된 솔더 레지스트층; 및상기 회로패턴과 연결되는 범프패드, 및 상기 범프패드와 연결되되 상기 절연부재의 타면에 노출되도록 형성되며, 상기 범프패드보다 큰 직경을 갖는 보조패드를 구비하고, 상기 보조패드에는 외부접속단자가 형성된 것을 특징으로 하는 인쇄회로기판.
- 청구항 6에 있어서,상기 보조패드의 노출면에는 표면처리층이 형성되어 있는 것을 특징으로 하는 인쇄회로기판.
- 청구항 1에 있어서,상기 솔더 레지스트층에는 상기 회로층 중에 제1 패드부를 노출시키는 제1 오픈부가 형성되어 있는 것을 특징으로 하는 인쇄회로기판.
- (A) 캐리어에 절연부재를 도포하고, 상기 절연부재에 임프린팅 공법에 의해 패턴용 트렌치를 가공하는 단계;(B) 상기 패턴용 트렌치 내부에 도금공정을 수행하여 회로패턴을 형성하는 단계;(C) 상기 절연부재에 빌드업 절연층을 적층하고, 층간연결을 위한 비아를 포함하는 회로층을 형성하는 단계; 및(D) 상기 빌드업 절연층에 솔더 레지스트층을 형성하고, 상기 캐리어를 제거하는 단계를 포함하는 인쇄회로기판의 제조방법.
- 청구항 9에 있어서,상기 (D) 단계에서,상기 솔더 레지스트층에 상기 회로층 중에 제1 패드부를 노출시키는 제1 오픈부를 가공하는 단계가 수행되는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- 청구항 9에 있어서,상기 (D) 단계 이후에,(E) 상기 절연부재에 상기 회로패턴 중에 제2 패드부를 노출시키는 제2 오픈부를 가공하는 단계를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- 청구항 11에 있어서,상기 (E) 단계 이후에,(F) 상기 패드부에 표면처리층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- (A) 캐리어에 절연부재를 도포하고, 상기 절연부재에 임프린팅 공법에 의해 패턴용 트렌치와 상기 절연부재를 관통하는 범프패드용 트렌치를 가공하는 단계;(B) 상기 패턴용 트렌치와 상기 범프패드용 트렌치의 내부에 도금공정을 수행하여 회로패턴 및 범프패드를 형성하는 단계;(C) 상기 절연부재에 빌드업 절연층을 적층하고, 층간연결을 위한 비아를 포함하는 회로층을 형성하는 단계; 및(D) 상기 빌드업 절연층에 솔더 레지스트층을 형성하고, 상기 캐리어를 제거하는 단계를 포함하는 인쇄회로기판의 제조방법.
- 청구항 13에 있어서,상기 (D) 단계에서,상기 솔더 레지스트층에 상기 회로층 중에 제1 패드부를 노출시키는 제1 오 픈부를 가공하는 단계가 수행되는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- 청구항 13에 있어서,상기 (D) 단계 이후에,(E) 상기 범프패드의 노출면에 표면처리층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- 청구항 13에 있어서,상기 (D) 단계 이후에,(E1) 상기 범프패드와 그 측면의 상기 절연부재에 두께방향으로 오픈부를 가공하는 단계; 및(E2) 상기 오픈부에 도금공정을 수행하여 보조패드를 형성하는 단계를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
- 청구항 16에 있어서,상기 (E2) 단계 이후에,(E3) 상기 보조패드에 표면처리층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090070634A KR101077380B1 (ko) | 2009-07-31 | 2009-07-31 | 인쇄회로기판 및 그 제조방법 |
US12/559,443 US8234781B2 (en) | 2009-07-31 | 2009-09-14 | Printed circuit board and method of fabricating the same |
JP2009213185A JP2011035358A (ja) | 2009-07-31 | 2009-09-15 | プリント基板及びその製造方法 |
US13/541,619 US20120267157A1 (en) | 2009-07-31 | 2012-07-03 | Printed circuit board and method of fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020090070634A KR101077380B1 (ko) | 2009-07-31 | 2009-07-31 | 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20110012771A KR20110012771A (ko) | 2011-02-09 |
KR101077380B1 true KR101077380B1 (ko) | 2011-10-26 |
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Application Number | Title | Priority Date | Filing Date |
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KR1020090070634A Expired - Fee Related KR101077380B1 (ko) | 2009-07-31 | 2009-07-31 | 인쇄회로기판 및 그 제조방법 |
Country Status (3)
Country | Link |
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US (2) | US8234781B2 (ko) |
JP (1) | JP2011035358A (ko) |
KR (1) | KR101077380B1 (ko) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI392405B (zh) * | 2009-10-26 | 2013-04-01 | Unimicron Technology Corp | 線路結構 |
JP5406241B2 (ja) * | 2011-04-19 | 2014-02-05 | 株式会社フジクラ | 配線板の製造方法 |
JP5232893B2 (ja) * | 2011-04-19 | 2013-07-10 | 株式会社フジクラ | 配線板の製造方法 |
TWI473551B (zh) * | 2011-07-08 | 2015-02-11 | Unimicron Technology Corp | 封裝基板及其製法 |
TWI613177B (zh) * | 2011-11-16 | 2018-02-01 | 製陶技術股份有限公司 | 製造一基材的方法 |
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US20120267157A1 (en) | 2012-10-25 |
JP2011035358A (ja) | 2011-02-17 |
KR20110012771A (ko) | 2011-02-09 |
US8234781B2 (en) | 2012-08-07 |
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