KR100811420B1 - Clock generator in RFID including nonvolatile ferroelectric memory - Google Patents

Abstract

The present invention relates to a clock generator in a radio frequency identification (RFID) including a nonvolatile ferroelectric memory, and discloses a technique for minimizing the configuration of the clock generator circuit in RFID and reducing power consumption. The present invention includes a clock adjusting unit for sensing the level of the power supply voltage and outputs a voltage control signal having a different current level in accordance with the level change of the power supply voltage; A clock oscillator for generating a differential output clock by adjusting the oscillation frequency of the clock according to the voltage control signal; A clock signal coupling unit coupling a differential output clock to output a plurality of reference voltages corresponding to the differential output clocks; And a clock amplifier unit configured to compare and amplify a plurality of reference voltages to limit a frequency change of the clock to a specific frequency range and output the same.

Description

Device for generating clock in RFID with non-volatile ferroelectric memory

1 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention.

2 is a block diagram of a clock generator in RFID including a nonvolatile ferroelectric memory according to the present invention;

FIG. 3 is a detailed circuit diagram of the clock adjuster of FIG. 2. FIG.

4 is a detailed circuit diagram related to the clock oscillator of FIG.

FIG. 5 is a detailed circuit diagram of the clock amplifier unit of FIG. 2. FIG.

6 and 7 are operation waveform diagrams of a clock generator according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator in a radio frequency identification (RFID) including a nonvolatile ferroelectric memory, and is a technique for minimizing the configuration of the clock generator circuit in RFID and reducing power consumption.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure similar to that of a DRAM, and uses a ferroelectric material as a capacitor material, and uses a high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

On the other hand, a general radio frequency identification (RFID) device includes an analog block, a digital block, and a memory block. Here, a clock generator is provided inside the analog block to generate a clock CLK in the digital block according to a power supply voltage applied from a voltage multiplier.

Here, designing a clock generator having a stable frequency characteristic has a great influence on the operation characteristics and power consumption characteristics of the RFID. In particular, in order to reduce the cost of the RFID tag in the RFID circuit design, a simple optimized circuit configuration is required. In addition, in order to improve the operation performance of the RFID, a configuration of a circuit capable of minimizing power consumption is required.

However, there is a problem that the conventional clock generator is designed to have a relatively complicated configuration to increase the cost of the RFID tag. In addition, the conventional clock generator does not have a stable frequency characteristics, there is a problem that the operating performance is lowered and the power consumption is increased.

The present invention has been made to solve the above problems, the present invention is to limit the change in frequency according to the voltage to maintain a stable frequency characteristics at a wide operating voltage.

In addition, an object of the present invention is to reduce the cost of the RFID tag and improve the operation performance by optimizing the configuration of the clock generation circuit relatively simply.

In addition, an object of the present invention is to reduce the power consumption of the RFID by reducing the current consumed by using a current limiting resistor element in the clock generation circuit.

Clock generation device in the RFID including the nonvolatile ferroelectric memory of the present invention for achieving the above object, by detecting the level of the power supply voltage and outputs a voltage control signal having a different current level in accordance with the level change of the power supply voltage A clock adjusting unit; A clock oscillator for generating a differential output clock by adjusting the oscillation frequency of the clock according to the voltage control signal; A clock signal coupling unit coupling a differential output clock to output a plurality of reference voltages corresponding to the differential output clocks; And a clock amplifier unit for comparing and amplifying the plurality of reference voltages to limit the frequency change of the clock to a specific frequency range and output the same.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention. The radio frequency identification (RFID) device of the present invention includes an analog block 100, a digital block 200, and a non-volatile ferroelectric random access memory (FeRAM) 300.

Here, the analog block 100 may include a voltage multiplier 110, a voltage limiter 120, a modulator 130, a demodulator 140, and a power on reset; 150 and a clock generator 160.

And, the antenna 10 of the analog block 100 is a configuration for transmitting and receiving radio frequency signal RF between the external reader or writer and RFID. The voltage multiplier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio frequency signal RF applied from the antenna 10. The voltage limiter 120 limits the magnitude of the transmission voltage of the radio frequency signal RF applied from the antenna 10 and outputs it to the demodulator 140 and the clock generator 160.

In addition, the modulator 130 modulates the response signal RP applied from the digital block 200 and transmits it to the antenna 10. The demodulator 140 detects an operation command signal from a radio frequency signal RF applied from the antenna 10 according to the output voltages of the voltage multiplier 110 and the voltage limiter 120 and transmits the command signal DEMOD to the digital block 200. Output

The power-on reset unit 150 detects the output voltage VDD of the voltage multiplier 110 and outputs a power-on reset signal POR for controlling the reset operation to the digital block 200. The clock generator 160 supplies the clock CLK to the digital block 200 for controlling the operation of the digital block 200 according to the output voltage VDD of the voltage multiplier 110.

In addition, the above-described digital block 200 receives a power supply voltage VDD, a power-on reset signal POR, a clock CLK, and a command signal DEMOD from the analog block 100 to interpret a command signal and generate control signals and processing signals to generate an analog block. The response signal RP corresponding to 100 is output. The digital block 200 outputs an address ADD, input / output data I / O, a control signal CTR, and a clock CLK to the FeRAM 300. The FeRAM 300 is a memory block that reads / writes data using a nonvolatile ferroelectric capacitor device.

2 is a detailed circuit diagram illustrating the clock generator 160 of FIG. 1.

The clock generator 160 includes a clock adjuster 161, a clock oscillator 162, a clock signal coupling unit 163, a reference bias unit 164 and 165, and a clock amplifier ( Clock Amplifier unit 166.

Here, the clock adjusting unit 161 adjusts the frequency characteristic of the input clock to output the voltage control signal VC1. The clock oscillator 162 adjusts the oscillation frequency of the clock according to the voltage control signal VC1 and outputs the clocks CLK1 and CLK2 which are frequency adjusted.

In addition, the clock signal coupling unit 163 couples the clocks CLK1 and CLK2 to output the coupling adjusted reference voltages vref1 and vref2. Here, the clock signal coupling unit 163 includes ferroelectric capacitors FC1 and FC2 connected between the application terminals of the clocks CLK1 and CLK2 and the output terminals of the reference voltages vref1 and vref2, respectively.

The reference bias unit 164 applies a constant bias voltage, which is a DC input voltage, to the reference voltage vref1 terminal. Here, the reference bias unit 164 includes reference resistors Rref1 and Rref2 connected between the power supply voltage VDD supply terminal and the ground voltage terminal.

In addition, the reference bias unit 165 applies a constant bias voltage, which is a DC input voltage, to the reference voltage vref2 terminal. Here, the reference bias unit 165 includes reference resistors Rref3 and Rref4 connected between the power supply voltage VDD supply terminal and the ground voltage terminal.

The clock amplifier unit 166 compares and amplifies the reference voltage vref1 applied through the positive terminal and the reference voltage vref2 applied through the negative terminal and outputs the clock CLK.

3 is a detailed circuit diagram illustrating the clock adjuster 161 of FIG. 2.

The clock adjuster 161 includes a power supply voltage detector 170 and a clock controller 171. Here, the power supply voltage detector 170 includes PMOS transistors P1 and P2, NMOS transistors N1 and N2, and resistors R1 and R2.

In the PMOS transistors P1 and P2, the common source terminal is connected to the power supply voltage terminal, and the common gate terminal is connected to the drain terminal of the PMOS transistor P1 to apply the detection signal dec3.

In the NMOS transistors N1 and N2, a common gate terminal is connected to the drain terminal of the NMOS transistor N2, and a control signal feed1 is applied thereto. Here, the NMOS transistor N1 is connected between the resistor R1 and the PMOS transistor P1, and the NMOS transistor N2 is connected between the resistor R2 and the ground voltage terminal.

The resistor R1 is connected between the source terminal of the NMOS transistor N1 and the ground voltage terminal to control the current of the detection signal dec1. The resistor R2 is connected between the drain terminal of the PMOS transistor P2 and the drain terminal of the NMOS transistor N2 to control the current flowing in the control signal feed1 and the detection signal dec2.

In addition, the clock control unit 171 includes a resistor R3 and an NMOS transistor N3. Here, the NMOS transistor N3 is connected between the resistor R3 and the ground voltage terminal, and the control signal feed1 is applied through the gate terminal. The resistor R3 is connected between the output terminal of the voltage control signal VC1 and the NMOS transistor N3.

4 is a detailed circuit diagram illustrating the clock oscillator 162 of FIG. 2.

The clock oscillator 162 includes an inverter chain having an odd number of inverters IV1 to IV5 and current control resistors RCLK1 and RCLK2 for adjusting the frequency of the clock CLK.

Here, each inverter IV1 to IV5 is a PMOS transistor and an NMOS transistor pair (P3, N4) (P4, N5) (P5, N6) (P6) connected in series between an application terminal of the voltage control signal VC1 and an application terminal of the voltage control signal VC0. , N7) (P7, N8).

Inverter IV1 of the first stage is supplied with the clock CLK1 through the gate terminal, and the outputs of the previous stage inverter are applied to the input of the next stage inverter in the other stages IV2 ~ IV5. In addition, the clock CLK1 output from the inverter IV5 of the last stage is fed back to the inverter IV1 of the first stage. The clock CLK2, which is the output of the inverter IV4, is a differential signal output having a phase opposite to that of the clock CLK1, which is the output of the inverter IV5.

In addition, the current control resistor RCLK1 is connected between the power supply voltage terminal and the application terminal of the voltage control signal VC1. The current control resistor RCLK2 is connected between the ground voltage terminal and the application terminal of the voltage control signal VC0.

FIG. 5 is a detailed circuit diagram of the clock amplifier unit 166 of FIG. 2.

The clock amplifier unit 166 includes an amplifier 180 and a buffer unit 181.

Here, the amplifier 180 includes a current limiting resistor elements R4 and R5, PMOS transistors P8 and P9, and NMOS transistors N9 and N10. Here, the current limiting resistor elements R4 and R5 are current limiting elements for limiting the drive current of the circuit.

The current limiting resistor R4 is connected between the supply voltage terminal and the common source terminal of the PMOS transistors P8 and P9. The current limiting resistor R5 is connected between the common source terminal of the NMOS transistors N9 and N10 and the ground voltage terminal.

The PMOS transistors P8 and P9 are connected between the current limiting resistor element R4 and the NMOS transistors N9 and N10 so that the common gate terminal is connected to the drain terminal of the PMOS transistor P8. The NMOS transistors N9 and N10 are connected between the PMOS transistors P8 and P9 and the current limiting resistor R5 to apply the differential inputs of the reference voltage vref2 and the reference voltage vref1 through their respective gate terminals.

In addition, the buffer unit 181 includes current limiting resistor elements R6 and R7 connected in series between a power supply voltage terminal and a ground voltage terminal, a PMOS transistor P10, and an NMOS transistor N11. Here, the output of the amplifier 180 is applied to the PMOS transistor P10 and the NMOS transistor N11 through the common gate terminal, and outputs the clock CLK through the common drain terminal. The current limiting resistors R4 and R5 are current limiting elements for limiting the drive current of the circuit.

An operation process of the present invention having such a configuration will be described below with reference to the operation waveform diagrams of FIGS. 6 and 7.

First, the clock adjusting unit 161 adjusts the frequency characteristic of the input clock to output the voltage control signal VC1. That is, the power supply voltage detector 170 senses the level of the power supply voltage VDD and outputs a control signal feed1 having different current levels according to the change of the power supply voltage.

Here, the control signal feed1 is input to the gate terminal of the NMOS transistor N3 of the clock control unit 171 to control the current flowing through the resistor R3. Therefore, when the level of the power supply voltage is increased, the current level of the control signal feed1 is increased to increase the amount of current of the voltage control signal VC1 flowing through the NMOS transistor N3.

Thereafter, the clock oscillator 162 adjusts the oscillation frequency of the clock according to the voltage levels of the voltage control signals VC1 and VC0, and outputs the frequency adjusted clocks CLK1 and CLK2. That is, when the voltage level of the voltage control signal VC1 increases, the operating frequencies of the clocks CLK1 and CLK2 are raised and output. Here, the voltage level of the voltage control signal VC1 is preferably set to be greater than the voltage control signal VC0 by a certain level.

Next, the clocks CLK1 and CLK2 output from the clock oscillator 162 are coupled by ferroelectric capacitors FC1 and FC2 and output to the reference voltage vref1 and vref2 stages. The reference bias unit 164 supplies a bias voltage corresponding to the divided values of the reference resistors Rref1 and Rref2 to the reference voltage vref1 stage. In addition, the reference bias unit 165 supplies a bias voltage corresponding to the divided values of the reference resistors Rref3 and Rref4 to the reference voltage vref2 stage.

Subsequently, the amplifier 180 of the clock amplifier unit 166 compares, amplifies, and outputs the reference voltages vref1 and vref2 that are differential inputs. The buffer unit 181 buffers the output of the amplifier 180 and outputs a clock adjusted frequency CLK.

At this time, the current limiting resistors R4 to R7 included in the above-described clock amplifier unit 166 drive a circuit by allowing a small current of 1 mA or less to flow in the clock amplifier unit 166 by using a resistor having a large resistance value. Limit the current.

As described above, FIG. 6 illustrates an operation waveform of the clock generator 160 when the power supply voltage VDD is 2V. That is, the clocks CLK1 and CLK2 are coupled by the ferroelectric capacitors FC1 and FC2 connected between the clocks CLK1 and CLK2 and the reference voltage vref1 and vref2 stages, and the reference voltages vref1 and vref2 are amplified by the clock amplifier 166 so that the clock CLK is increased. Will occur.

7 illustrates an operation waveform of the clock generator 160 when the power supply voltage VDD rises to 3V. That is, even if the level of the power supply voltage changes, it can be seen that the voltage level of the voltage control signal VC1 is adjusted by the control signal feed1, so that the frequency change of the clock CLK is adjusted accordingly.

As described above, designing a clock generator that outputs a clock having stable frequency characteristics has a great influence on the operation characteristics and power consumption characteristics of the RFID. In order to reduce the cost of the RFID tag in the design of the RFID circuit, a simple optimized circuit configuration is required. In addition, in order to improve the operation performance of the RFID, a configuration of a circuit capable of minimizing power consumption is required.

Accordingly, the clock generator 160 of the present invention is implemented to minimize power consumption with an optimized circuit configuration, thereby satisfying both of the above requirements.

As described above, the present invention provides the following effects.

First, the present invention is to limit the change of the frequency according to the power supply voltage to maintain a stable frequency characteristics at a wide range of operating voltage.

Secondly, the present invention can relatively simply optimize the configuration of the clock generation circuit to reduce the cost of the RFID tag and improve the operation performance.

Third, the present invention provides the effect of reducing the power consumption of the RFID by reducing the current consumed by using a current limiting resistor element in the clock generation circuit.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

Claims (15)

A clock adjuster 161 for detecting a level of a power supply voltage and outputting a first voltage control signal VC1 having a different current level according to a change in the power supply voltage level; A clock oscillator 162 for generating a differential output clock by adjusting an oscillation frequency of a clock according to the first voltage control signal; A clock signal coupling unit 163 coupling the differential output clock to output a plurality of reference voltages corresponding to the differential output clocks; And And a clock amplifier unit (166) for comparing and amplifying the plurality of reference voltages to limit the frequency change of the clock to a specific frequency range. The method of claim 1, wherein the clock adjusting unit 161 is A power supply voltage sensing unit 170 for sensing the level of the power supply voltage and outputting the first voltage control signal VC1 having a different current level according to a change in the power supply voltage; And And a clock controller (171) for controlling the amount of current of the voltage control signal according to the first voltage control signal (VC1). The method of claim 2, wherein the power supply voltage sensing unit 170 The first PMOS transistor and the second PMOS transistor having a common source terminal connected to the supply terminal of the power supply voltage and a common gate terminal connected to the first node. A first resistor coupled between the second PMOS transistor and an output terminal of the control signal; A second resistor connected to the ground voltage terminal; A first NMOS transistor connected between the first node and the second resistor to receive the control signal through a gate terminal; And And a second NMOS transistor connected between an output terminal of the control signal and a ground voltage terminal to which the control signal is applied through a gate terminal. The method of claim 2, wherein the clock control unit 171 is A third resistor connected to an output terminal of the voltage control signal; And And a third NMOS transistor connected between the third resistor and a ground voltage terminal to which the control signal is applied through a gate terminal. The method of claim 1, wherein the clock oscillator 162 An inverter chain configured to generate the differential output clock according to the first voltage control signal VC1 and the second voltage control signal VC0; And And a current control resistor for adjusting and outputting the oscillation frequency of the differential output clock. 6. The clock generator of claim 5, wherein the voltage level of the first voltage control signal VC1 is higher than the voltage level of the second voltage control signal VC0. . The method of claim 5, wherein the current control resistor unit A first current control resistor connected between the power supply voltage supply terminal and the first voltage control signal VC1; And And a second current control resistor connected between the second voltage control signal (VC0) applied terminal and a ground voltage terminal. The method of claim 1, wherein the clock signal coupling unit 163 And a plurality of ferroelectric capacitors coupling the differential output clocks to output the plurality of reference voltages. The clock generation apparatus of claim 1, further comprising a reference bias unit configured to apply a predetermined bias voltage to the plurality of reference voltages. 10. The method of claim 9, wherein the plurality of reference voltages comprise a first reference voltage and a second reference voltage, The reference bias unit A first reference bias unit 164 for supplying a bias voltage divided by resistance to the first reference voltage; And And a second reference bias unit (165) for supplying a bias voltage divided by the resistance to the second reference voltage (165). 12. The RFID of claim 10, wherein the first reference bias unit 164 includes first and second reference resistors connected between the supply terminal of the power supply voltage and the ground voltage terminal. Clock generation device in. 12. The RFID of claim 10, wherein the second reference bias unit 165 includes third and fourth reference resistors connected between the supply terminal of the power supply voltage and the ground voltage terminal. Clock generation device in. The method of claim 1, wherein the clock amplifier unit 166 is An amplifier for comparing and amplifying the plurality of reference voltages; And And a buffer unit configured to generate the clock by buffering the output of the amplifier. The method of claim 13, wherein the amplification unit A differential amplifier for comparing the plurality of reference voltages; A first current limiting resistor element connected between the differential amplifier and a power supply voltage terminal; And And a second current limiting resistor element coupled between the differential amplifier and a ground voltage terminal. The method of claim 13, wherein the buffer unit A third current limiting resistor element connected to the power supply voltage terminal; A fourth current limiting resistor element connected to the ground voltage terminal; And A third PMOS transistor and a fourth NMOS transistor connected between the third current limiting resistor element and the fourth current limiting resistor element to receive an output of the amplifier through a common gate terminal and to output the clock through a common drain terminal. A clock generating device in an RFID comprising a nonvolatile ferroelectric memory.

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