KR100702306B1 - Clock generator in RFID including nonvolatile ferroelectric memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator in an RFID including a nonvolatile ferroelectric memory, and to stabilize the clock and minimize current consumption by outputting the high and low edges of the clock in synchronization with the output signal of the demodulator. Discuss the technique. The present invention generates a high level clock by synchronizing the operation signal to the high level edge of the operation signal during the high level pulse width section of the output signal of the demodulator, the operation signal of the RFID chip, and during the low level pulse width section of the output signal. A low level clock is generated by synchronizing the operation signal to a low level edge of the operation signal, and a clock is generated by combining the high level clock and the low level clock.

Description

Device for generating clock in RFID with non-volatile ferroelectric memory

1A and 1B are diagrams for explaining a data encoding method of a data processing apparatus according to the prior art.

2 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention;

3 is a block diagram of a clock generator in RFID including a nonvolatile ferroelectric memory according to the present invention;

4 is an operation timing diagram of a clock generator in RFID including a nonvolatile ferroelectric memory according to the present invention;

FIG. 5 is a detailed circuit diagram of the clock generator of FIG. 3. FIG.

FIG. 6 is a detailed circuit diagram of the amplifying driver and synthesis unit of FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator in an RFID including a nonvolatile ferroelectric memory, and to output the high and low edges of the clock in synchronization with the output signal of the demodulator, thereby stabilizing the clock and minimizing current consumption. It is a technique to do.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

1A and 1B are diagrams for describing a data encoding method of a general data processing apparatus.

1A shows a Pulse Interval Encoding (PIE) symbol in Interrogator-to-Tag Communication. That is, data '0' is applied for a time of 1Tari to maintain the low pulse width PW for 0.5Tari time, and data '1' is applied for 2Tari time to maintain the low pulse width PW for 0.5Tari time. . After the delimiter command is applied, a frame synchronization signal or a preamble signal is applied.

When the radio frequency signal RF is applied from the outside through the antenna, the operation signal DEMOD of the RFID chip is generated at the output of the demodulator by the rectifying action of the Schottky diode and the charge pump operation of the capacitor.

It is necessary to match the operation signal DEMOD with the frequency characteristic of the clock generator. However, in the general data processing apparatus as shown in FIGS. 1A and 1B, since an external command signal and an operating frequency of data are applied differently, an oscillator corresponding to each operating frequency cannot be implemented. Accordingly, there is a problem that it is difficult to synchronize the output signal of demodulators having different operating frequencies with the clock of the clock generator.

The present invention was created to solve the above problems, and separates the high level clock and the low level clock by synchronizing the operation signal and the clock signal at the high edge and the low edge of the operation signal which is the output of the demodulator in the clock generator of the RFID. The goal is to allow the clock to stabilize and minimize current consumption.

A clock generation device in an RFID including a nonvolatile ferroelectric memory of the present invention for achieving the above object, by synchronizing the operation signal to the high level edge of the operation signal during the high level pulse width section of the operation signal of the RFID chip. A high level active oscillator for outputting a high level control signal; And an amplifying driver for amplifying and buffering the high level control signal to generate a high level clock.

The present invention also provides a low level active oscillator for outputting a low level control signal by synchronizing an operation signal to a low level edge of an operation signal during a low level pulse width section of an operation signal of an RFID chip; And an amplifying driver for amplifying and buffering the low level control signal to generate a low level clock.

In addition, the present invention includes a high level active oscillator means for generating a high level clock by synchronizing the operation signal to the high level edge of the operation signal during the high level pulse width section of the operation signal of the RFID chip; Low level active oscillator means for generating a low level clock by synchronizing the operation signal to a low level edge of the operation signal during the low level pulse width period of the operation signal; And a clock synthesizing unit configured to synthesize the high level clock and the low level clock to generate a clock.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention. The radio frequency identification (RFID) device of the present invention includes an analog block 100, a digital block 200, and a non-volatile ferroelectric random access memory (FeRAM) 300.

The analog block 100 may include a voltage multiplier 110, a voltage limiter 120, a modulator 130, a demodulator 140, and a power on reset unit. 150 and a clock generator 160.

And, the antenna 10 of the analog block 100 is a configuration for transmitting and receiving radio frequency signal RF between the external reader or writer and RFID. The voltage multiplier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio frequency signal RF applied from the antenna 10. The voltage limiter 120 limits the magnitude of the transmission voltage of the radio frequency signal RF applied from the antenna 10 and outputs it to the demodulator 140 and the clock generator 160.

In addition, the modulator 130 modulates the response signal RP applied from the digital block 200 and transmits it to the antenna 10. The demodulator 140 detects an operation command signal from a radio frequency signal RF applied from the antenna 10 according to the output voltages of the voltage multiplier 110 and the voltage limiter 120 and transmits the operation signal DEMOD to the digital block 200. Output

The power-on reset unit 150 detects the output voltage VDD of the voltage multiplier 110 and outputs a power-on reset signal POR for controlling the reset operation to the digital block 200. The clock generator 160 supplies the clock CLK to the digital block 200 for controlling the operation of the digital block 200 according to the output voltage VDD of the voltage multiplier 110.

In addition, the above-described digital block 200 receives a power supply voltage VDD, a power-on reset signal POR, a clock CLK, and an operation signal DEMOD from the analog block 100 to interpret a command signal and generate control signals and processing signals to generate an analog block. Output the response signal RP corresponding to (100). The digital block 200 outputs an address ADD, input / output data I / O, a control signal CTR, and a clock CLK to the FeRAM 300. The FeRAM 300 is a memory block that reads / writes data using a nonvolatile ferroelectric capacitor element.

3 is a detailed block diagram illustrating the clock generator 160 of FIG. 2.

The clock generator 160 includes an oscillator 161, a temperature voltage characteristic adjusting unit 164, and a clock synthesizing unit 165. Here, the oscillator unit 161 includes a high level active oscillator 162, a low level active oscillator 163, and amplification drivers A1 and A2.

The high level active oscillator 162 outputs the high level control signals / high_s and high_s by synchronizing the operation signal DEMOD during the high level period of the operation signal DEMOD applied from the demodulator 140. The amplification driver A2 amplifies and buffers the high level control signals / high_s and high_s to output the high level clock CLK_H.

The low level active oscillator 163 outputs the low level control signals low_s and / low_s by synchronizing the operation signal DEMOD during the low level period of the operation signal DEMOD applied from the demodulator 140. The amplifying driver A1 amplifies and buffers the low level control signals low_s and / low_s to output the low level clock CLK_L.

The temperature voltage characteristic adjusting unit 164 limits the current of the high level active oscillator 162 and the low level active oscillator 163 to stabilize the temperature compensation. The clock synthesizing unit 165 synthesizes the high level clock CLK_H and the low level clock CLK_L to output the clock CLK.

4 illustrates a waveform diagram of a clock output from the clock generator 160 of FIG. 3.

The high level active oscillator 162 outputs the high level clock CLK_H in synchronization with a low to high edge of the operation signal DEMOD applied from the demodulator 140. The low level active oscillator 163 outputs the low level clock CLK_L in synchronization with the high to low edge of the operation signal DEMOD applied from the demodulator 140.

In addition, the clock synthesizing unit 165 combines the high level clock CLK_H applied from the high level active oscillator 162 and the low level clock CLK_L applied from the low level active oscillator 163 to output the clock CLK.

5 is a detailed circuit diagram of the clock generator 160 of FIG. 3.

The high level active oscillator 162 includes a plurality of PMOS transistors P7 to P11 and a plurality of NMOS transistors N8 to N13 to perform an oscillation operation. In the high level active oscillator 162 having the above configuration, when the operation signal DEMOD is activated, the NMOS transistor N12 is activated to output the high level control signals / high_s and high_s.

The low level active oscillator 163 includes a plurality of PMOS transistors P1 to P6 and a plurality of NMOS transistors N1 to N7 to perform an oscillation operation. The low level active oscillator 163 having such a configuration deactivates the operation signal / DEMOD by the PMOS transistor P1 and the NMOS transistor N1 when the operation signal DEMOD is activated. When the operation signal DEMOD is inactivated, the operation signal / DEMOD is activated by the PMOS transistor P1 and the NMOS transistor N1. Accordingly, the NMOS transistor N6 is activated to output the low level control signals / low_s and low_s.

In addition, the amplifying driver A1 inputs the low level control signal / low_s to the negative (-) terminal and the low level control signal low_s to the positive (+) terminal to output the low level clock CLK_L. The amplification driver A2 inputs the high level control signal / high_s to the negative (-) terminal and the high level control signal high_s to the positive (+) terminal to output the high level clock CLK_H.

The temperature voltage characteristic adjusting unit 164 includes resistors R1 to R3, nonvolatile ferroelectric capacitors FC1 to FC4, and NMOS transistors N14 to N17.

Here, the resistor R1 and the NMOS transistor N14 are connected in series between the power supply voltage terminal and the ground voltage terminal, and the gate terminal and the drain terminal are commonly connected to the NMOS transistor N14. The NMOS transistor N15 is connected between the NMOS transistor N8 and the resistor R2 so that the gate terminal is connected to the resistor R1. The NMOS transistor N16 is connected between the NMOS transistor N16 and the NMOS transistor N17 so that the gate terminal is commonly connected with the NMOS transistor N15.

In addition, the nonvolatile ferroelectric capacitor FC4 is connected between the NMOS transistor N13 and the ground voltage terminal. Resistor R2 is connected between NMOS transistor N15 and NMOS transistor N17. The nonvolatile ferroelectric capacitor FC2 is connected in parallel with the resistor R2. NMOS transistor N17 is connected between resistor R2 and resistor R3 and its gate terminal is connected to nonvolatile ferroelectric capacitor FC1. The nonvolatile ferroelectric capacitor FC3 is connected in parallel with the resistor R3. The combiner 165 combines the low level clock CLK_L and the high level clock CLK_H to output the clock CLK.

FIG. 6 is a detailed circuit diagram of the amplifier drivers A1 and A2 and the combiner 165 of FIG. 5.

The amplification driver A1 includes a low level amplifier including resistors R4, R5, PMOS transistors P12, P13, and NMOS transistors N18, N19, resistors R6-R8, PMOS transistors P14, P15, and NMOS transistors N20, N21. And a low level buffer portion.

The amplification driver A2 includes a high level amplifier including resistors R9 and R10, PMOS transistors P16, P17 and NMOS transistors N22 and N23, resistors R11 to R13, PMOS transistors P18, P19 and NMOS transistors N24 and N25. It includes a high level buffer unit.

In addition, the combiner 165 includes an AND gate AND that performs an AND operation on the low level clock CLK_L and the high level clock CLK_H to output the clock CLK.

Referring to the operation of the present invention having such a configuration as follows.

First, when the operation signal DEMOD is applied through the demodulator 140 of the RFID, the NMOS transistor N12 is turned on to activate the high level active oscillator 162 at the high level edge of the operation signal DEMOD. At this time, the low level active oscillator 163 is turned off by the NMOS transistor N6 by an inverter composed of a PMOS transistor P1 and an NMOS transistor N1. Accordingly, the high level control signals / high_s and high_s are activated to operate the high level amplifier.

Here, the resistors R9 and R10 of the high level amplifier section limit the current flowing through the amplification driver A2 as a current limiting resistor element. The high level buffer unit buffers the output of the high level amplifier unit to generate the high level clock CLK_H. At this time, the high level active oscillator 162 consumes a lot of current when the oscillator operates. Accordingly, the resistors R9 to R13 allow a small current of 1 mA or less to flow through the amplification driver A2 using a resistance element having a large resistance value.

On the other hand, when the operation signal DEMOD is applied through the demodulator 140 of the RFID, the NMOS transistor N6 is turned on to activate the low level active oscillator 163 at the low level edge of the operation signal DEMOD. At this time, the NMOS transistor N12 is turned off because the operation signal DEMOD becomes low level and the high level active oscillator 162 does not operate. Accordingly, the low level control signals / low_s and low_s are activated to operate the low level amplifier.

Here, the resistors R4 and R5 of the low level amplifier unit limit the current flowing through the amplification driver A1 as a current limiting resistor. The low level buffer unit buffers the output of the low level amplifier to generate the low level clock CLK_L. In this case, the low level active oscillator 163 consumes a lot of current when the oscillator operates. Accordingly, the resistors R9 to R13 allow a small current of 1 mA or less to flow through the amplification driver A2 using a resistance element having a large resistance value.

In this case, the temperature voltage characteristic adjusting unit 164 maintains the turn-on state at all times and limits the current flowing through the high level active oscillator 162 and the low level active oscillator 163 through the current limiting resistor elements R1 to R3. Accordingly, the resistors R1 to R3 allow a small current of 1 mA or less to flow in the temperature voltage characteristic adjusting unit 164 by using a resistor having a large resistance value. In addition, the nonvolatile ferroelectric capacitors FC1 to FC4 stabilize the temperature and voltage characteristics when adjusting them.

Next, the synthesis unit 165 performs an AND operation on the low level clock CLK_L and the high level clock CLK_H to generate the synthesized clock CLK.

As described above, the present invention includes a separate oscillator operating at a high level and an oscillator operating at a low level of an operation signal that is an output of a demodulator, so that each clock can be reset when the operation signal is changed. As a result, the phase difference of the clock can be minimized, a stable clock can be generated, and the current consumption can be minimized.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (20)

A high level active oscillator outputting a high level control signal by synchronizing the operation signal to a high level edge of the operation signal during a high level pulse width section of an operation signal of an RFID chip; And And an amplifying driver for amplifying and buffering the high level control signal to generate a high level clock. The apparatus of claim 1, further comprising a temperature voltage characteristic adjusting unit configured to limit a current flowing through the high level active oscillator and stabilize the current when temperature compensation. . The method of claim 2, wherein the temperature voltage characteristic adjusting unit A plurality of current limiting resistor elements for limiting a current flowing through the high level active oscillator; And And a nonvolatile ferroelectric capacitor for stabilizing the current upon temperature compensation of the high level active oscillator. According to claim 1, wherein the amplification driving unit A high level amplifier for amplifying the high level control signal; And And a high level buffer unit configured to buffer the output of the high level amplifier to generate the high level clock. 5. The clock generator of claim 4, wherein the high level amplifier and the high level buffer unit include a current limiting resistor for limiting a current flowing in the amplification driver. . A low level active oscillator outputting a low level control signal by synchronizing the operation signal to a low level edge of the operation signal during a low level pulse width period of an operation signal of an RFID chip; And And an amplifying driver for amplifying and buffering the low level control signal to generate a low level clock. 7. The clock generator of claim 6, further comprising a temperature voltage characteristic adjusting unit configured to limit a current flowing through the low-level active oscillator and stabilize the current during temperature compensation. . The method of claim 7, wherein the temperature voltage characteristic adjusting unit A plurality of current limiting resistor elements for limiting a current flowing through the low level active oscillator; And And a nonvolatile ferroelectric capacitor for stabilizing the current during temperature compensation of the low level active oscillator. The method of claim 6, wherein the amplification driving unit A low level amplifier for amplifying the low level control signal; And And a low level buffer unit configured to buffer the output of the low level amplifier to generate the low level clock. 10. The clock generation apparatus of claim 9, wherein the low level amplifier and the low level buffer include a current limiting resistor for limiting a current flowing through the amplification driver. . High level active oscillator means for generating a high level clock by synchronizing the operation signal to a high level edge of the operation signal during a high level pulse width period of an operation signal of an RFID chip; Low level active oscillator means for generating a low level clock by synchronizing the operation signal to a low level edge of the operation signal during a low level pulse width period of the operation signal; And And a clock synthesizer for synthesizing the high level clock and the low level clock to generate a clock. 12. The nonvolatile ferroelectric memory of claim 11, further comprising a temperature voltage characteristic adjusting unit for limiting current flowing through the low level active oscillator means and the high level active oscillator means and stabilizing the current upon temperature compensation. Clock generating device in RFID. The method of claim 12, wherein the temperature voltage characteristic adjusting unit A plurality of current limiting resistor elements for limiting a current flowing through the low level active oscillator means and the high level active oscillator means; And And a nonvolatile ferroelectric capacitor comprising a plurality of nonvolatile ferroelectric capacitors for stabilizing the low level active oscillator means and the temperature compensation of the high level active oscillator means. 12. The apparatus of claim 11, wherein the high level active oscillator means A high level active oscillator outputting a high level control signal by performing an oscillation operation when the operation signal is activated; And And a first amplification driver for amplifying and buffering the high level control signal to generate the high level clock. 15. The method of claim 14, wherein the first amplifier driving unit A high level amplifier for amplifying the high level control signal; And And a high level buffer unit configured to buffer the output of the high level amplifier to generate the high level clock. 16. The clock of claim 15, wherein the high level amplifying section and the high level buffer section include a current limiting resistor for limiting a current flowing in the first amplifying driving section. Generating device. 12. The apparatus of claim 11, wherein the low level active oscillator means A low level active oscillator outputting a low level control signal by performing an oscillation operation when the operation signal is inactivated; And And a second amplifying driver for amplifying and buffering the low level control signal to generate the low level clock. 18. The method of claim 17, wherein the second amplification driving unit A low level amplifier for amplifying the low level control signal; And And a low level buffer unit configured to buffer the output of the low level amplifier to generate the low level clock. 19. The clock of claim 18, wherein the low level amplifying unit and the low level buffer unit include a current limiting resistor for limiting a current flowing in the second amplifying driver. Generating device. 12. The clock generation apparatus of claim 11, wherein the clock synthesizing unit comprises an AND gate for generating the clock by AND-operating the high level clock and the low level clock. .

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