KR101010097B1 - RFID tag with power supply voltage adjustment function - Google Patents

Abstract

The present invention relates to an RFID tag which maintains a power supply voltage at a constant level and minimizes power consumption by operating only when a power supply voltage is supplied or when a command signal is received.

Specifically, the present invention provides a voltage amplifying unit for generating a power supply voltage by amplifying a radio signal received from an RFID reader, a power on reset unit for generating a power on reset signal when the power supply voltage is amplified to a power supply voltage level, and a power supply voltage. An RFID tag comprising a voltage adjuster that maintains a constant power supply voltage level, wherein the voltage adjuster discloses an RFID tag that is activated by a power-on reset signal.

Additionally, the present invention discloses an RFID tag including a voltage amplifier for amplifying a radio signal received from an RFID reader to generate a power supply voltage, and a voltage adjuster for maintaining the power supply voltage at a power supply voltage level.

RFID, power, power, reset, command, NMOS, transistor, enable

Description

RDF tag with power supply voltage adjustment {RFID TAG WITH POWER VOLTAGE REGULATING FUNCTION}

The present invention relates to an RFID tag which maintains a power supply voltage at a constant level and minimizes power consumption by operating only when a power supply voltage is supplied or when a command signal is received. More specifically, the voltage regulator in the RFID tag is related to the RFID tag that maintains the power supply voltage at a constant level by lowering it when the power supply voltage is increased and increasing it when the power supply voltage is decreased.

RFID is a technology that provides a contactless automatic identification method in which an RFID tag is attached to an object to be identified to automatically identify the object using a wireless signal and communicates with an RFID reader through transmission and reception using a wireless signal. It is a technology that can compensate for the shortcomings of barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

In general, a nonvolatile ferroelectric memory may be used for an RFID tag.

Nonvolatile ferroelectric memories, or ferroelectric random access memories (FeRAMs), have a data processing speed of about DRAM (DRAM) and are attracting attention as next-generation memory devices because of their characteristics that data is preserved even when the power is turned off.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is an overall configuration diagram of an RFID tag according to the prior art.

Referring to FIG. 1, the RFID tag according to the related art largely includes an antenna unit 10, an analog unit 100, a digital unit 200, and a memory unit 300.

The antenna unit 10 serves to receive a radio signal transmitted from the RFID reader. The received radio signal is input to the analog unit 100 through the antenna pads 11 and 12.

The analog unit 100 amplifies the input wireless signal to generate a power supply voltage that is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 200. In addition, the analog unit 100 senses the output voltage VDD and outputs a power-on reset signal POR and a clock signal CLK for controlling the reset operation to the digital unit 200.

The digital unit 200 receives a power supply voltage, a power-on reset signal POR, a clock signal CLK, and a command signal CMD from the analog unit 100 to obtain an address ADD, input / output data I / O, control signal CTR, and clock CLK. Output to the memory 300.

The memory 300 reads / writes data using a memory device and stores data.

Since the RFID tag according to the related art does not include a separate component for maintaining a constant power supply voltage, there is a problem that the RFID tag malfunctions when the power supply voltage becomes unstable.

In order to solve the above problems, the present invention maintains the power supply voltage at a constant level and minimizes power consumption by operating only when the power supply voltage is supplied or when a command signal is received.

The present invention provides a voltage amplification unit for amplifying a wireless signal received from an RFID reader to generate a power supply voltage, a power-on reset unit for generating a power-on reset signal when the power supply voltage is amplified to a power supply voltage level, and supplying the power supply voltage to a power supply voltage level. An RFID tag comprising a voltage adjusting unit for maintaining a constant voltage, the voltage adjusting unit being activated by a power-on reset signal, the voltage adjusting unit comprising: a power supply voltage terminal to which a power supply voltage is input; A driving unit selectively connecting the power supply voltage terminal with the ground voltage terminal to maintain the power supply voltage at a power supply voltage level; And an offset amplifier unit generating an adjustment signal for controlling the connection operation of the driving unit.

Additionally, the present invention includes a voltage amplifier for amplifying a wireless signal received from the RFID reader to generate a power supply voltage, and a voltage adjustor for maintaining the power supply voltage at a constant power supply voltage level. Power supply voltage terminals; A driving unit selectively connecting the power supply voltage terminal with the ground voltage terminal to maintain the power supply voltage at a power supply voltage level; And an offset amplifier unit generating an adjustment signal for controlling the connection operation of the driving unit.

First, since the RFID tag of the present invention has a power supply voltage adjusting function, the power supply voltage is kept constant. In other words, when the power supply voltage becomes high, the voltage is lowered, and when the power supply voltage becomes low, the voltage is increased.

Second, the RFID tag of the present invention has the advantage that power consumption can be minimized by enabling the power supply voltage adjustment function only when the power supply voltage is supplied at the power supply voltage level by the power on reset signal.

Third, the RFID tag of the present invention has an advantage of minimizing power consumption by enabling the power supply voltage adjustment function only when a command signal is received.

Preferred embodiments of the present invention are for purposes of illustration, and those skilled in the art can make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is an overall configuration diagram of an RFID tag according to the present invention.

Referring to FIG. 2, the RFID tag of the present invention includes an antenna unit 10, an analog unit 100, a digital unit 200, and a memory unit 300.

The antenna unit 10 serves to receive a radio signal transmitted from the RFID reader. The received radio signal is input to the analog unit 100 through the antenna pads 11 and 12.

The analog unit 100 includes a voltage amplifier 110, a demodulator 120, a clock generator 130, a power-on reset unit 140, a voltage adjuster 150, and a modulator 160.

The voltage amplifying unit 110 rectifies and boosts a radio signal applied from the antenna unit 10 to generate a power supply voltage which is a driving voltage of the RFID tag.

The demodulator 120 detects an operation command signal from a wireless signal input from the antenna unit 10 according to the output voltage of the voltage amplifying unit 110 to generate a command signal CMD, and generates the command signal CMD using the voltage adjusting unit. Output to the 150 and the digital unit 200.

The clock generator 130 supplies the clock CLK for controlling the operation of the digital unit 200 according to the power voltage generated by the voltage amplifier 110 to the digital unit 200.

The power on reset unit 140 detects a power supply voltage generated by the voltage amplifier 110 and outputs a power on reset signal POR for controlling the reset operation to the voltage adjusting unit 120 and the digital unit 200.

The power-on reset signal POR means a signal set to a low level when the power supply voltage is supplied to the power supply voltage level VDD and the RFID tag starts to operate. Therefore, when the power supply voltage is not supplied or when a low voltage below the power supply voltage level VDD is supplied, the power-on reset signal POR is set to a high level.

The voltage adjuster 150 adjusts the voltage so that the power supply voltage generated by the voltage amplifier 110 is maintained at a constant level. When the supply voltage rises above a certain level, the voltage is lowered. When the supply voltage goes below a certain level, the voltage is increased.

The modulator 160 modulates the response signal RP input from the digital unit 200 and transmits the modulated response signal RP to the antenna unit 10.

The digital unit 200 receives a power supply voltage, a power-on reset signal POR, a clock CLK, and a command signal CMD from the analog unit 100 to interpret the command signal CMD and generate control signals and processing signals. The response signal RP corresponding to the control signal and the processing signal is output to the analog unit 100.

The digital unit 200 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 300. The memory unit 300 writes data to the storage device and reads data stored in the storage device.

As the memory 300, a nonvolatile ferroelectric memory (FeRAM) may be used. FeRAM has a data processing speed of about DRAM (DRAM). In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

3 shows a circuit diagram of the voltage adjusting unit 150 according to the first embodiment of the present invention.

Referring to FIG. 3, the voltage adjusting unit 150 according to the first embodiment of the present invention may include an activator 151, a voltage detector 152, a voltage drop unit 153, an offset amplifier unit 154, and a driver ( 155).

The activation unit 151 is activated or deactivated by the power on reset signal POR.

The activation unit 151 includes an inverter INV and an NMOS transistor NA. The activation unit 151 is deactivated when the power on reset signal POR is at a high level, and the activation unit 151 is activated when the power on reset signal POR is at a low level.

The power-on reset signal POR is applied to the high level when the power supply voltage is not supplied or when a low voltage below the power supply voltage level VDD is supplied. The inverter INV inverts the power-on reset signal POR and outputs it at a low level. Since the low level signal is input to the gate of the NMOS transistor NA, the NMOS transistor NA is turned off. When the NMOS transistor NA is turned off, the activator 151 is inactivated.

When the power supply voltage is supplied to the power supply voltage level VDD, the power-on reset signal POR is applied to the low level. The inverter INV inverts the power-on reset signal POR and outputs it at a high level. Since the high level signal is input to the gate of the NMOS transistor NA, the NMOS transistor NA is turned on. When the NMOS transistor NA is turned on, the activator 151 is activated. When the activator 151 is activated, the voltage detector 152 and the voltage drop unit 153 start to operate.

The voltage sensing unit 152 includes voltage sensing resistors R1 and R2. The voltage Vmax is set by the voltage sensing resistor R1 and the NMOS transistors N11 to N1N, and the voltage Vmin is set by the voltage sensing resistor R2 and the NMOS transistors N21 to N2M.

Specifically, when the power supply voltage is supplied at the power supply voltage level VDD, the voltage VR1 is induced to the voltage sensing resistor R1, and the voltage Vmax is set by VDD-VR1 = Vmax. Similarly, voltage VR2 is induced to voltage sensing resistor R2, and voltage Vmin is set by VDD-VR2 = Vmin.

The voltage drop unit 153 includes a plurality of NMOS transistors N11 to N1N and N21 to N2M. The number of NMOS transistors connected in series to node a is N, and the number of NMOS transistors connected in series to node b is M. It is preferable that the number of NMOS transistors is set to N> M, and M = N-1.

When the activation unit 151 is activated by the power-on reset signal POR, voltages are supplied to the gates of the NMOS transistors N11 to N1N and N21 to N2M, and the NMOS transistors N11 to N1N and N21 to N2M are sequentially turned on. Therefore, the voltages of nodes a and b can be dropped.

The offset amplifier section 154 includes an OP amplifier OA having a positive (+) terminal and a negative (-) terminal. The positive (+) terminal of the op amp OA is connected to node a, and the negative (-) terminal is connected to node b. The op amp OA outputs the adjustment signal CON_R to the output terminal.

The offset amplifier unit 154 outputs the adjustment signal CON_R to the driver 155 according to a voltage applied to the positive (+) terminal and the negative (-) terminal and a preset offset voltage value.

The driver 155 includes an NMOS transistor ND. The gate of the NMOS transistor is connected to the output terminal of the offset amplifier unit 154, and the source / drain is connected to the power supply voltage terminal or the ground voltage terminal.

When the adjustment signal CON_R is output at a high level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned on to discharge the power supply voltage applied to the power supply voltage terminal to the ground voltage terminal. When the adjustment signal CON_R is output at the low level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned off to maintain the voltage level of the power supply voltage terminal.

Hereinafter, a process of controlling the adjustment signal CON_R by the voltage adjusting unit 150 will be described in detail with reference to a timing diagram of the voltage adjusting unit 150.

4 is an operation timing diagram of the voltage adjusting unit 150 according to the first embodiment of the present invention.

Referring to FIG. 4, the t1 section represents a section from when the wireless signal is input to the RFID tag until the voltage amplifier 110 amplifies the power supply voltage to the power supply voltage level VDD. The voltage amplifier 110 supplies a power supply voltage to the power on reset unit 140 and the voltage adjuster 150.

In the period t1, since the voltage amplifier 110 does not amplify the power supply voltage to the power supply voltage level VDD, the power on reset unit 140 does not initialize the power on reset signal POR to a low level. Therefore, the power-on reset signal POR is output at a high level so that the activation unit 151 maintains an inactive state. In addition, since the activation unit 151 is in an inactive state, the voltage sensing unit 152 and the voltage drop unit 153 do not operate, thereby reducing power consumption.

Since the active part 151 is inactive in the node a and the node b, no current flows to the voltage dropping part 153, and the amount of current input to the OP amplifier OA is negligible, so that the current is also applied to the voltage sensing resistors R1 and R2. Does not flow. Therefore, node a and node b are subjected to the same voltage as the power supply voltage terminal.

When the voltages of the positive (+) terminal and the negative (-) terminal of the OP amplifier OA are the same, the OP amplifier OA outputs the adjustment signal CON_R at a low level according to the preset offset characteristic (the adjustment signal according to the preset offset characteristic). The process of controlling the CON_R will be described later with reference to FIGS. 9 to 10. When the adjustment signal CON_R is output at a low level, that is, when a low level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned off. Therefore, since the power supply voltage terminal is not connected to the ground voltage terminal, the voltage level of the power supply voltage terminal is maintained, and the potential of the power supply voltage terminal rises to the power supply voltage level VDD.

From the period t2, the power supply voltage supplied to the power on reset unit 140 and the voltage adjusting unit 150 maintains the power supply voltage level VDD. Therefore, the power on reset unit 140 initializes the power on reset signal POR. In other words, the power-on reset signal POR transitions from the high level to the low level. When the power on reset signal POR becomes low, the activator 151 is activated. When the activator 151 is activated, the voltage detector 152 and the voltage drop unit 153 start to operate.

As described above, when the power supply voltage is supplied to the power supply voltage terminal at the power supply voltage level VDD, the voltage Vmax with VDD-VR1 = Vmax is set at the node a, and the voltage Vmin with VDD-VR2 = Vmin is set at the node b. Node a is connected to the positive (+) terminal of the OP amplifier OA and node b is connected to the negative (-) terminal of the OP amplifier OA. Accordingly, the OP amplifier OA outputs the adjustment signal CON_R at a high level according to the voltage difference between the input terminal and the preset offset characteristic. (The process of controlling the adjustment signal CON_R according to the preset offset characteristic is described in FIGS. 9 to 10. To be described later). When the adjustment signal CON_R is output at a high level, that is, when a high level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned on. Therefore, a current flows from the power supply voltage terminal to the ground voltage terminal, and is adjusted to an appropriate level so that the potential of the power supply voltage terminal is not excessively increased.

5 shows a circuit diagram of the voltage adjusting unit 150 according to the second embodiment of the present invention.

Referring to FIG. 5, the voltage adjusting unit 150 according to the second embodiment of the present invention includes a voltage sensing unit 152, a voltage dropping unit 153, an offset amplifier unit 154, and a driving unit 155. The difference from the first embodiment is that the second embodiment does not include the activator 151.

In the second embodiment of the present invention, since the voltage adjusting unit 150 does not include the activating unit 151, the voltage sensing unit 152 and the voltage dropping unit 153 even though the power supply voltage has a value smaller than the power supply voltage level VDD. ) Works.

The voltage sensing unit 152 includes voltage sensing resistors R1 and R2.

The voltage drop unit 153 includes a plurality of NMOS transistors N11 to N1N and N21 to N2M. The number of NMOS transistors connected in series to node a is N, and the number of NMOS transistors connected in series to node b is M. It is preferable that the number of NMOS transistors is set to N> M, and M = N-1.

In the voltage drop unit 153, the number of NMOS transistors N21 to N2M connected to the node b is smaller than the number of NMOS transistors N11 to N1N connected to the node a. Therefore, when a voltage enough to turn on the NMOS transistors N21 to N2M is applied to the node b, the voltage drop unit 153 operates. That is, the voltage capable of operating the NMOS transistors N21 to N2M is set to the voltage Vmin. The voltage capable of operating the NMOS transistors N11 to N1N is set to the voltage Vmax.

When the power supply voltage of the power supply voltage level VDD is supplied to the power supply voltage terminal, a voltage is supplied to each of the gates of the NMOS transistors N11 to N1N and N21 to N2M, and the NMOS transistors N11 to N1N and N21 to N2M are sequentially turned on. Therefore, the voltages of nodes a and b can be dropped.

The offset amplifier section 154 includes an OP amplifier OA having a positive (+) terminal and a negative (-) terminal. The positive (+) terminal of the op amp OA is connected to node a, and the negative (-) terminal is connected to node b. The op amp OA outputs the adjustment signal CON_R to the output terminal.

The offset amplifier unit 154 outputs the adjustment signal CON_R to the driver 155 according to a voltage applied to the positive (+) terminal and the negative (-) terminal and a preset offset voltage value.

The driver 155 includes an NMOS transistor ND. The gate of the NMOS transistor ND is connected to the output terminal of the offset amplifier unit 154, and the source / drain is connected to the power supply voltage terminal or the ground voltage terminal.

When the adjustment signal CON_R is output at a high level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned on so that current flows from the power supply voltage terminal to the ground voltage terminal so as not to overload the power supply voltage terminal. When the adjustment signal CON_R is output at the low level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned off to maintain the voltage level of the power supply voltage terminal.

Hereinafter, a process of controlling the adjustment signal CON_R by the voltage adjusting unit 150 will be described in detail with reference to a timing diagram of the voltage adjusting unit 150.

6 is an operation timing diagram of the voltage adjusting unit 150 according to the second embodiment of the present invention.

Referring to FIG. 6, the t1 section represents a section from when a wireless signal is input to the RFID tag until the voltage amplifier 110 amplifies the power supply voltage to the power supply voltage level VDD. The voltage amplifier 110 supplies a power supply voltage to the power on reset unit 140 and the voltage adjuster 150.

In the period t1, since the voltage amplifier 110 does not amplify the power supply voltage to the power supply voltage level VDD, the power on reset unit 140 does not initialize the power on reset signal POR to a low level.

As described above, when the power supply voltage is supplied such that the potential of the node b is equal to or lower than the voltage Vmin, the NMOS transistors N11 to N2N and N21 to N2M included in the voltage drop unit 153 are not turned on. Therefore, when the power supply voltage is supplied at a low voltage, the voltage drop unit 153 does not operate, thereby reducing power consumption.

Since no current flows from the node a and the node b to the voltage drop unit 153, and the amount of current input to the OP amplifier OA is negligible, no current flows through the voltage sensing resistors R1 and R2. Therefore, node a and node b are subjected to the same voltage as the power supply voltage terminal.

When the voltages of the positive (+) terminal and the negative (-) terminal of the OP amplifier OA are the same, the OP amplifier OA outputs the adjustment signal CON_R at a low level according to the preset offset characteristic (the adjustment signal according to the preset offset characteristic). The process of controlling the CON_R will be described later with reference to FIGS. 9 to 10. When the adjustment signal CON_R is output at a low level, that is, when a low level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned off. Therefore, since the power supply voltage terminal is not connected to the ground voltage terminal, the voltage level of the power supply voltage terminal is maintained, and the potential of the power supply voltage terminal rises to the power supply voltage level VDD.

When the power supply voltage is supplied such that the potential of the node b is equal to or higher than the voltage Vmin, the voltage drop unit 153 starts to operate while the NMOS transistors N21 to N2M are turned on. When the voltage drop unit 153 operates, voltages induced at the nodes a and b are applied to the positive and negative terminals of the OP amplifier OA, respectively. Accordingly, the OP amplifier OA of the offset voltage unit 154 outputs the adjustment signal CON_R to a high level according to the voltage difference of the input terminal and the preset offset characteristic (the control signal CON_R is controlled according to the preset offset characteristic). The process will be described later with reference to FIGS. 9 to 10). That is, in the second embodiment of the present invention, the adjustment signal CON_R is output at a high level before the period t2.

When the adjustment signal CON_R is output at a high level, that is, when a high level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned on. Therefore, a current flows from the power supply voltage terminal to the ground voltage terminal, and is adjusted to an appropriate level so that the potential of the power supply voltage terminal is not excessively increased.

From the period t2, the power supply voltage supplied to the power on reset unit 140 and the voltage adjusting unit 150 maintains the power supply voltage level VDD. Therefore, the power on reset unit 140 initializes the power on reset signal POR. In other words, the power-on reset signal POR transitions from the high level to the low level.

Since the power supply voltage maintains the power supply voltage level VDD in the period after t2, the voltage drop unit 153 continues to operate. Accordingly, the OP amplifier OA of the offset voltage unit 154 outputs the adjustment signal CON_R to a high level according to the voltage difference of the input terminal and the preset offset characteristic, and the NMOS transistor ND of the driver 155 is turned on according to the adjustment signal CON_R. Thus, the potential of the power supply voltage terminal is adjusted to an appropriate level so as not to be excessively high.

7 shows a circuit diagram of the voltage adjusting unit 150 according to the third embodiment of the present invention.

Referring to FIG. 7, the voltage adjusting unit 150 according to the third embodiment of the present invention may include an activating unit 151, a voltage sensing unit 152, a voltage dropping unit 153, an offset amplifier unit 154, and a driving unit ( 155).

The activation unit 151 is activated or deactivated by the power-on reset signal POR and the command signal CMD.

The activation unit 151 includes inverters INV and NMOS transistors NA and NB. When the power-on reset signal POR is low level and the command signal CMD is high level, the activator 151 is activated. Otherwise, the activator 151 is deactivated.

The power-on reset signal POR is applied to the high level when the power supply voltage is not supplied or when a low voltage below the power supply voltage level VDD is supplied. The inverter INV inverts the power-on reset signal POR and outputs it at a low level. Since the low level signal is input to the gate of the NMOS transistor NA, the NMOS transistor NA is turned off.

When the power supply voltage is supplied to the power supply voltage level VDD, the power-on reset signal POR is applied to the low level. The inverter INV inverts the power-on reset signal POR and outputs it at a high level. Since the high level signal is input to the gate of the NMOS transistor NA, the NMOS transistor NA is turned on.

The demodulator 120 detects an operation command signal from a wireless signal input from the antenna unit 10 according to a power supply voltage supplied from the voltage amplifier 110 to generate a command signal CMD. The generated command signal CMD is input to the gate of the NMOS transistor NB of the activator 151. When the command signal CMD is applied at a high level, the NMOS transistor NB is turned on. When the command signal CMD is applied at a low level, the NMOS transistor NB is turned off.

In the above, when the NMOS transistors NA and NB are both turned on, the activator 151 is activated, and in other cases, the activator 151 is deactivated. When the activator 151 is deactivated, power consumption may be reduced because the voltage detector 152 and the voltage dropper 153 do not operate.

The voltage sensing unit 152 includes voltage sensing resistors R1 and R2. The voltage Vmax is set by the voltage sensing resistor R1 and the NMOS transistors N11 to N1N, and the voltage Vmin is set by the voltage sensing resistor R2 and the NMOS transistors N21 to N2M.

Specifically, when the power supply voltage is supplied at the power supply voltage level VDD, the voltage VR1 is induced to the voltage sensing resistor R1, and the voltage Vmax is set by VDD-VR1 = Vmax. Similarly, voltage VR2 is induced to voltage sensing resistor R2, and voltage Vmin is set by VDD-VR2 = Vmin.

The voltage drop unit 153 includes a plurality of NMOS transistors N11 to N1N and N21 to N2M. The number of NMOS transistors connected in series to node a is N, and the number of NMOS transistors connected in series to node b is M. It is preferable that the number of NMOS transistors is set to N> M, and M = N-1.

When the activation unit 151 is activated by the power-on reset signal POR, voltages are supplied to the gates of the NMOS transistors N11 to N1N and N21 to N2M, and the NMOS transistors N11 to N1N and N21 to N2M are sequentially turned on. Therefore, the voltages of nodes a and b can be dropped.

The offset amplifier section 154 includes an OP amplifier OA having a positive (+) terminal and a negative (-) terminal. The positive (+) terminal of the op amp OA is connected to node a, and the negative (-) terminal is connected to node b. The op amp OA outputs the adjustment signal CON_R to the output terminal.

The offset amplifier unit 154 outputs the adjustment signal CON_R to the driver 155 according to a voltage applied to the positive (+) terminal and the negative (-) terminal and a preset offset voltage value.

The driver 155 includes an NMOS transistor ND. The gate of the NMOS transistor ND is connected to the output terminal of the offset amplifier unit 154, and the source / drain is connected to the power supply voltage terminal or the ground voltage terminal.

When the adjustment signal CON_R is output at a high level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned on so that current flows from the power supply voltage terminal to the ground voltage terminal so as not to overload the power supply voltage terminal. When the adjustment signal CON_R is output at the low level and applied to the gate of the NMOS transistor ND, the NMOS transistor ND is turned off to maintain the voltage level of the power supply voltage terminal.

Hereinafter, a process of controlling the adjustment signal CON_R by the voltage adjusting unit 150 will be described in detail with reference to a timing diagram of the voltage adjusting unit 150.

8 is an operation timing diagram of the voltage adjusting unit 150 according to the third embodiment of the present invention.

Referring to FIG. 8, the t1 section represents a section from when a wireless signal is input to the RFID tag until the voltage amplifier 110 amplifies the power supply voltage to the power supply voltage level VDD. The voltage amplifier 110 supplies a power supply voltage to the power on reset unit 140 and the voltage adjuster 150.

In the period t1, since the voltage amplifier 110 does not amplify the power supply voltage to the power supply voltage level VDD, the power on reset unit 140 does not initialize the power on reset signal POR to a low level.

Since the activator 151 is inactive at the node a and the node b, no current flows to the voltage drop unit 153, and the amount of current input to the OP amplifier OA is negligible. No current flows Therefore, node a and node b are subjected to the same voltage as the power supply voltage terminal.

When the voltages of the positive (+) terminal and the negative (-) terminal of the OP amplifier OA are the same, the OP amplifier OA outputs the adjustment signal CON_R at a low level according to the preset offset characteristic (the adjustment signal according to the preset offset characteristic). The process of controlling the CON_R will be described later with reference to FIGS. 9 to 10. When the adjustment signal CON_R is output at a low level, that is, when a low level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned off. Therefore, since the power supply voltage terminal is not connected to the ground voltage terminal, the voltage level of the power supply voltage terminal is maintained, and the potential of the power supply voltage terminal rises to the power supply voltage level VDD.

From the period t2, the power supply voltage supplied to the power on reset unit 140 and the voltage adjusting unit 150 maintains the power supply voltage level VDD. Therefore, the power on reset unit 140 initializes the power on reset signal POR. In other words, the power-on reset signal POR transitions from the high level to the low level. When the power on reset signal POR becomes low, the activator 151 is activated. When the activator 151 is activated, the voltage detector 152 and the voltage drop unit 153 start to operate.

As described above, when the power supply voltage is supplied to the power supply voltage terminal at the power supply voltage level VDD, a voltage Vmax of VDD-VR1 = Vmax is induced to the node a, and a voltage Vmin of VDD-VR2 = Vmin is induced to the node b. Node a is connected to the positive (+) terminal of the OP amplifier OA and node b is connected to the negative (-) terminal of the OP amplifier OA. Accordingly, the OP amplifier OA outputs the adjustment signal CON_R at a high level according to the voltage difference between the input terminal and the preset offset characteristic. (The process of controlling the adjustment signal CON_R according to the preset offset characteristic is described with reference to FIGS. 9 to 10. As described below). When the adjustment signal CON_R is output at a high level, that is, when a high level signal is input to the gate of the NMOS transistor ND included in the driver 155, the NMOS transistor ND is turned on. Therefore, a current flows from the power supply voltage terminal to the ground voltage terminal, and is adjusted to an appropriate level so that the potential of the power supply voltage terminal is not excessively increased.

The t4 section represents a section in which the command signal CMD is input at a low level. The command signal CMD may be input at a low level to stop the operation of the RFID tag even when the power supply voltage is supplied to the power supply voltage level VDD. In this case, since a low level signal is applied to the gate of the NMOS transistor NB included in the activation unit 151, the NMOS transistor NB is turned off. Therefore, the activation unit 151 is deactivated.

When the activator 151 is deactivated, since the voltage detector 152 and the voltage drop unit 153 do not operate as described above, the input voltages of the positive (+) terminal and the negative (-) terminal of the OP amplifier OA are the same. Become. The op amp OA therefore outputs the adjustment signal CON_R at a low level.

9 shows a circuit diagram of an offset amplifier unit 154 according to the present invention.

Referring to FIG. 9, the offset amplifier unit 154 according to the present invention is set such that the current driving capability of the positive (+) terminal connected to the node a is lower than the current driving capability of the negative (-) terminal connected to the node b. . Therefore, the data voltage level input to the positive (+) terminal of the op amp OA and the reference voltage level input to the negative (-) terminal are different.

The value of the offset voltage Voffset between the positive and negative terminals of the op amp OA is set to "kV". That is, the OP amplifier OA outputs the adjustment signal CON_R to the low level when the voltage of the node a is equal to the voltage of the node b, and when the difference between the voltage level of the node a and the voltage level of the node b is equal to or greater than the offset voltage Voffset, Output at high level.

10 shows a circuit diagram of an OP amplifier OA according to the present invention.

Referring to FIG. 10, the OP amplifier OA includes current limiting resistors R3 and R4, PMOS transistors P1 and P2, and NMOS transistors MN1 and MN2.

The current limiting resistors R3 and R4 control the magnitude of the current flowing through the OP amplifier OA by supplying a voltage between the supply voltage and the ground voltage VSS to the OP amplifier OA.

The PMOS transistors P1, P2 and the NMOS transistors MN1, MN2 are current driving means for driving a current input from the node a and the node b to the OP amplifier OA.

The PMOS transistors P1 and P2 are connected between the current limiting resistor R3 and the NMOS transistors MN1 and MN2. The gates of the PMOS transistors P1 and P2 are interconnected to form a common gate, and the common gates of the PMOS transistors P1 and P2 are connected to the drain of the PMOS transistor P1.

NMOS transistors MN1 and MN2 are connected between PMOS transistors P1 and P2 and current limiting resistor R4. The gate of NMOS transistor MN1 is connected to node a, the source of NMOS transistor MN1 is connected to the drain of PMOS transistor P1, and the drain of NMOS transistor MN1 is connected to current limiting resistor R4. Similarly, the gate of NMOS transistor MN2 is connected to node b, the source of NMOS transistor MN2 is connected to the drain of PMOS transistor P2, and the drain of NMOS transistor MN2 is connected to current limiting resistor R4.

That is, the PMOS transistors P1 and P2 and the NMOS transistors MN1 and MN2 operate as current mirrors.

The OP amplifier OA according to the present invention is set such that the current characteristic of the NMOS transistor MN2 is k times larger than that of the NMOS transistor MN1 (where k is a constant greater than 1). Therefore, a current having a magnitude of Id flows in the drain-source direction of the NMOS transistor MN1, and a current having a magnitude of Id × k flows in the drain-source direction of the NMOS transistor MN2.

Therefore, the offset voltage Voffset between the positive and negative terminals of the op amp OA is set to "kV". In this case, if the voltage level of the node a is equal to the voltage level of the node b, the voltage difference becomes zero, so the OP amplifier OA outputs the adjustment signal CON_R at a low level. When the voltage difference between the voltage level of the node a and the voltage level of the node b is equal to or greater than the offset voltage Voffset, the adjustment signal CON_R is output at a high level.

The op amp OA may include a buffer buffer after the output terminal Vout.

The OP amplifier OA according to the present invention can set the characteristic variable of the offset voltage Voffset through the NMOS transistors MN1 and MN2. The method is shown in Table 1 below. In Table 1, k represents a constant greater than one.

Offset property variable NMOS transistor MN1
NMOS transistor MN2 Justice Method 1 Width W kW Channel width Method 2 Length kL L  Channel length Method 3 Vt kVtn Vtn Threshold voltage Method 4 Id Id kId  drain-source current

Hereinafter, the method 1 to 4 will be described in detail with reference to [Table 1].

Method 1 sets different channel widths of the NMOS transistors N4 and N5 to set the characteristic variable of the offset voltage Voffset in the OP amplifier OA. The channel width of the NMOS transistor MN1 is set to W, the channel width of the NMOS transistor MN2 is set to kW, and the current driving capability of the negative (-) terminal is set high.

Method 2 sets the channel lengths of the NMOS transistors MN1 and MN2 differently to set the characteristic variable of the offset voltage Voffset in the OP amplifier OA. The channel length of the NMOS transistor MN1 is set to kL, and the channel length of the NMOS transistor MN2 is set to L, so that the current driving capability of the negative (-) terminal is set high.

Method 3 sets the threshold voltages of the NMOS transistors MN1 and MN2 differently to set the characteristic variable of the offset voltage Voffset in the OP amplifier OA. The threshold voltage of the NMOS transistor MN1 is set to kVtn, and the threshold voltage of the NMOS transistor MN2 is set to Vtn, thereby setting the current driving capability of the negative (-) terminal high.

Method 4 sets the drain-source current of the NMOS transistors N4 and N5 differently to set the characteristic variable of the offset voltage Voffset in the OP amplifier OA. The drain-source current of the NMOS transistor MN1 is set to Id, and the drain-source current of the NMOS transistor MN2 is set to kId, so that the current driving capability of the negative (-) terminal is set high.

1 is an overall configuration diagram of an RFID tag according to the prior art.

2 is an overall configuration diagram of an RFID tag according to the present invention.

3 is a circuit diagram of a voltage adjusting unit according to a first embodiment of the present invention.

4 is an operation timing diagram of the voltage adjusting unit 150 according to the first embodiment of the present invention.

5 is a circuit diagram of a voltage adjusting unit according to a second embodiment of the present invention.

6 is an operation timing diagram of the voltage adjusting unit according to the second embodiment of the present invention.

7 is a circuit diagram of a voltage adjusting unit according to a third embodiment of the present invention.

8 is an operation timing diagram of a voltage adjusting unit according to a third embodiment of the present invention.

9 is a circuit diagram of an offset amplifier unit according to the present invention.

10 shows a circuit diagram of an OP amplifier according to the present invention.

Claims (26)

A voltage amplifier configured to generate a power supply voltage by amplifying a wireless signal received from the RFID reader; A power on reset unit generating a power on reset signal when the power supply voltage is amplified to a power supply voltage level; And An RFID tag comprising a voltage adjusting unit that maintains the power supply voltage at a power supply voltage level. The voltage regulator is activated by the power on reset signal, The voltage adjusting unit A power supply voltage terminal to which the power supply voltage is input; A driver configured to selectively connect the power supply voltage terminal with a ground voltage terminal to maintain the power supply voltage at a power supply voltage level; And And an offset amplifier unit generating an adjustment signal for controlling a connection operation of the driver. The method according to claim 1, An RFID tag further comprising a demodulator for demodulating the radio signal to generate a command signal. And the voltage adjuster is activated by the power on reset signal and the command signal. delete delete The method according to claim 1, The driving unit is an RFID tag, characterized in that consisting of the NMOS transistor. The method according to claim 1, The voltage adjusting unit And a voltage drop unit configured to control a magnitude of a voltage input to an input terminal of the offset amplifier unit when the voltage adjuster is activated by the power on reset signal. The method according to claim 6, The voltage drop unit is an RFID tag, characterized in that composed of a plurality of NMOS transistors. The method according to claim 1, The voltage adjusting unit And a voltage sensing unit configured to detect a power supply voltage having a power supply voltage level to the power supply voltage terminal and to induce a voltage to an input terminal of the offset amplifier unit. The method according to claim 1, And the offset amplifier unit outputs the adjustment signal at a low level according to a preset offset characteristic when the same voltage is applied to an input terminal. The method according to claim 1, And the offset amplifier unit outputs the adjustment signal at a high level according to a preset offset characteristic and a voltage input to an input terminal when a power voltage having a power voltage level is supplied through the power voltage terminal. The method according to claim 2, And a digital unit configured to receive and interpret the command signal to generate a control signal and to generate a response signal corresponding to the control signal. The method of claim 11, RFID tag further comprising a memory unit for storing the control signal. The method according to claim 12, And the memory unit comprises a ferroelectric memory element. A voltage amplifier configured to generate a power supply voltage by amplifying a wireless signal received from the RFID reader; And A voltage adjusting unit which maintains the power supply voltage at a power supply voltage level, The voltage adjusting unit A power supply voltage terminal to which the power supply voltage is input; A driver configured to selectively connect the power supply voltage terminal with a ground voltage terminal to maintain the power supply voltage at a power supply voltage level; And And an offset amplifier unit generating an adjustment signal for controlling a connection operation of the driver. delete delete The method according to claim 14, The driving unit is an RFID tag, characterized in that consisting of the NMOS transistor. The method according to claim 14, The voltage adjusting unit The RFID tag further comprises a voltage drop for controlling the magnitude of the voltage input to the input terminal of the offset amplifier. 19. The method of claim 18, The voltage drop unit is an RFID tag, characterized in that composed of a plurality of NMOS transistors. The method according to claim 14, The voltage adjusting unit And a voltage sensing unit configured to detect a power supply voltage having a power supply voltage level to the power supply voltage terminal and to induce a voltage to an input terminal of the offset amplifier unit. The method according to claim 14, And the offset amplifier unit outputs the adjustment signal at a low level according to a preset offset characteristic when the same voltage is applied to an input terminal. The method according to claim 14, And the offset amplifier unit outputs the adjustment signal at a high level according to a preset offset characteristic and a voltage input to an input terminal when a power voltage having a power voltage level is supplied through the power voltage terminal. The method according to claim 14, And a demodulator configured to demodulate the radio signal to generate a command signal. The method according to claim 23, And a digital unit which receives and interprets the command signal to generate a control signal, and generates a response signal corresponding to the control signal. 27. The method of claim 24, RFID tag further comprising a memory unit for storing the control signal. The method according to claim 25, And the memory unit comprises a ferroelectric memory element.

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