KR101037536B1 - RFID device - Google Patents

Abstract

The present invention relates to an RFID device, and discloses a technique for improving memory efficiency by implementing a nonvolatile memory region and a ROM region in an RFID tag chip in the same cell structure. The present invention relates to an RFID device in which a read / write operation of data is performed according to a radio frequency signal applied from an antenna, wherein a memory unit for storing data stores a nonvolatile memory area for storing data nonvolatilely and tag information. It includes all ROM regions.

Description

RFID device {RFID device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RFID device, and to a RFID tag chip including a nonvolatile memory cell.

RFID (Radio Frequency IDentification Tag Chip) is a contactless automatic identification method that communicates with an RFID reader by attaching an RFID tag to an object to be identified and automatically transmitting and receiving it by using a wireless signal. To provide technology. As RFID is used, it is possible to compensate for the disadvantages of the conventional automatic identification technology, barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

Meanwhile, a nonvolatile ferroelectric memory may be used as a memory used for an RFID tag.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is an overall configuration diagram of a general RFID device.

The RFID device according to the related art includes an antenna unit 1, an analog unit 10, a digital unit 20, and a memory unit 30.

Here, the antenna unit 1 serves to receive a radio signal transmitted from an external RFID reader. The wireless signal received through the antenna unit 1 is input to the analog unit 10 through the antenna pads 11 and 12.

The analog unit 10 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 20. In addition, the analog unit 10 senses the output voltage VDD and outputs a power-on reset signal POR and a clock CLK to the digital unit 20 for controlling the reset operation.

The digital unit 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 10, and outputs a response signal RP to the analog unit 10. The digital unit 20 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 30.

In addition, the memory unit 30 reads / writes data using a memory element and stores the data.

Here, the RFID device uses a frequency of several bands, the characteristics of which vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the RFID device operates in a short distance, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

The present invention has been made to solve the above problems, and has the following object.

First, an object of the present invention is to provide a memory structure in which a nonvolatile memory region and a ROM region are mixed in an RFID tag chip.

Second, the purpose of the non-volatile memory region and the ROM (ROM) region in the RFID tag chip to implement the same cell structure.

In the RFID device of the present invention for achieving the above object, in the RFID device in which the data read / write operation is performed according to the radio frequency signal applied from the antenna, the memory unit in which the data is stored is changed corresponding to the radio frequency signal It includes both a non-volatile memory area for storing non-volatile data and a ROM area for storing tag information set at the manufacturing stage and for which data is not changed.The cell array of the ROM area has a physical connection with a bit line. It characterized in that it comprises at least one unit cell blocked.

The present invention provides an effect of improving the memory efficiency of RFID by implementing a nonvolatile memory region and a ROM region in the same cell structure in an RFID tag chip.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such configuration changes, etc. It should be seen as belonging to a range.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an overall configuration diagram of a radio frequency identification (RFID) device according to the present invention.

The RFID device of the present invention largely includes an analog unit 100, a digital unit 200, and a memory unit 300.

Here, the analog unit 100 includes a voltage amplifier 110, a modulator 120, a demodulator 130, a power on reset unit 140, and a clock generator 150).

And, the antenna ANT of the analog unit 100 is a configuration for transmitting and receiving data between the external reader or writer and RFID. Antenna ANT is connected through RFID tag and antenna pad PAD (+), PAD (-).

The voltage amplifier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio frequency signal RF applied from the antenna ANT.

In addition, the modulator 120 modulates the response signal RP applied from the digital unit 200 and transmits the modulated response signal RP to the antenna ANT. The demodulator 130 detects an operation command signal from the radio frequency signal RF applied from the antenna ANT according to the output voltage of the voltage amplifier 110 and outputs the command signal CMD to the digital unit 200.

The power on reset unit 140 detects the output voltage VDD of the voltage amplifying unit 110 and outputs a power on reset signal POR for controlling the reset operation to the digital unit 200. The clock generator 150 supplies the clock CLK for controlling the operation of the digital unit 200 to the digital unit 200 according to the output voltage VDD of the voltage amplifying unit 110.

In addition, the above-described digital unit 200 receives a power supply voltage VDD, a power-on reset signal POR, a clock CLK, and a command signal CMD from the analog unit 100 to interpret the command signal CMD, generate control signals, and process signals to generate analog signals. The response signal RP corresponding to the unit 200 is output. The digital unit 200 outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 300.

In addition, the memory unit 300 includes a plurality of memory cells, each of which serves to write data to the storage device and to read data stored in the storage device.

The memory unit 300 includes both a nonvolatile memory region and a ROM region. A nonvolatile ferroelectric memory (FeRAM) may be used as the nonvolatile memory region. FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

3 is a detailed block diagram illustrating the memory unit 300 of FIG. 2.

The memory unit 300 includes a word line decoder 310, a signal controller 320, a cell array 330, a sense amplifier, and an input / output buffer 340.

Here, the word line decoder 310 decodes the word line WL according to the address ADD applied from the digital unit 200 and outputs the word line WL to the cell array 330. The signal controller 320 is a word line for driving the cell array 330 according to a chip enable signal CE applied from the digital unit 200 and control signals CTR such as an output enable signal OE and a write enable signal WE. (WL) and plate line PL.

The signal controller 320 controls the operation of the sense amplifier 340 according to the chip enable signal CE applied from the digital unit 200 and control signals CTR such as the output enable signal OE and the write enable signal WE. do.

That is, the signal controller 320 may include a sense amplifier enable signal for controlling whether the sense amplifier 340 is activated, and an output enable signal and data for outputting the data sensed by the sense amplifier 340 to the data bus M_DATA. A write enable signal for writing data applied from the bus M_DATA to the cell array 330 is output.

The cell array 330 includes both a nonvolatile memory cell region and a ROM cell region. The nonvolatile memory cell region includes a plurality of unit cells including a nonvolatile ferroelectric capacitor element and a switching element to store data in the nonvolatile ferroelectric capacitor element and read the stored data.

In addition, the operation of the sense amplifier and the input / output buffer 340 is controlled according to the sense amplifier enable signal, the output enable signal OE, and the write enable signal WE applied from the signal controller 320 based on the reference voltage. .

The sense amplifier and the input / output buffer 340 sense and amplify data applied from the cell array 330, output the data to the data bus M_DATA, and transfer data applied from the data bus M_DATA to the cell array 330.

Looking at the function of each control signal in the memory unit 300 having such a configuration as shown in Table 1 below.

Control signal I / O Description ADD input Address applied from digital part CE input Chip enable signal applied from digital part WE input Light enable signal applied from digital part OE input Output Enable Signal Applied from Digital Section M_DATA Input / output I / O data bus

4 is a detailed circuit diagram illustrating a nonvolatile memory cell region and a ROM cell region in the cell array 330 of FIG. 3. In FIG. 4, a case in which the unit cells RC1 and RC2 of the ROM cell region have a 2T2C structure will be described as an example.

The nonvolatile memory cell area of the cell array 330 includes a plurality of unit cells C in an area where the word line WL and the plate line PL intersect with the bit line BL and the bit line bar / BL.

Here, the unit cell C includes a bit line BL (or bit line bar / BL), a switching element T1 and a ferroelectric capacitor FC1 connected in series between the plate line PL. The switching element T1 is controlled by the word line WL.

Meanwhile, the ROM cell area of the cell array 330 includes a plurality of unit cells RC1 and RC2 in an area where word line WL and plate line PL intersect with bit line BL and bit line bar / BL. Here, the unit cell RC1 of the 1T1C structure includes a ferroelectric capacitor RFC1 having one end connected to the plate line PL, and a switching element RT1 connected to the other end of the ferroelectric capacitor RFC1 and controlled by the word line WL.

The unit cell RC2 having the 1T1C structure includes a ferroelectric capacitor RFC2 connected in series between the plate line PL and the bit line bar / BL, and the switching element RT2. The switching element RT2 is controlled by the word line WL for switching operation. Here, it is preferable that the switching elements RT1 and RT2 consist of NMOS transistor elements.

In the unit cell RC1 connected to the word line WL1 in the unit cell of the ROM cell region having the above configuration, the switching element RT1 has a physical structure separated from the bit line BL, and the unit cell RC2 connected to the word line WL1 has a It is physically connected to the linebar / BL. Here, the switching element RT1 is implemented such that the connection with the bit line BL is blocked from forming the switching element on the mask.

On the contrary, in the unit cell RC1 connected to the word line WLn among the unit cells in the ROM cell region, the switching element RT1 is physically connected to the bit line BL, and the unit cell RC2 connected to the word line WLn is the bit line bar. It is separated into / BL and physical structure. Here, the switching element RT2 is implemented so that the connection with the bit line bar / BL is blocked from forming the switching element on the mask.

The sense amplifier 340 is activated according to the sense amplifier enable signal SEN applied from the signal controller 320 to sense and amplify data carried on the bit line BL and the bit line bar / BL. In the embodiment of FIG. 4, a pair of bit lines BL and bit line bars / BL share one sense amplifier 340.

An operation process of the nonvolatile memory cell region of the cell array 330 having such a configuration will be described with reference to the operation timing diagram of FIG. 5.

First, in the t0 period, the bit line equalizing signal BLEQ becomes high to activate the bit line equalizing unit (not shown). As a result, the bit line pairs BL and / BL are both precharged while maintaining the ground voltage level.

At this time, the word line WL, the plate line PL, and the sense amplifier enable signal SEN maintain a low level.

Thereafter, the bit line equalizing signal BLEQ transitions to low when the t1 period is entered, thereby stopping the equalizing operation. When the word line WL and the plate line PL transition high, charge distribution is performed according to the cell data, and the data is read / written to the unit cell C of the cell array 330.

Subsequently, when the sense amplifier enable signal SEN is enabled when the t2 period is entered, the sense amplifier 340 is activated to sense and amplify data carried on the bit line pair BL // BL. Accordingly, data '0' is restored in the t2 section.

When the plate line PL transitions low when the t3 period is entered, the data '1' is restored.

Next, the word line WL transitions low when the t4 period is entered. In addition, the sensing amplifier enable signal SEN transitions low in the period t4 so that the sensing operation of the sense amplifier 340 is stopped. At this time, the bit line equalizing signal BLEQ transitions to high again, and the bit line pairs BL and / BL are again precharged to the ground voltage level.

FIG. 6 is a diagram for describing a bit line sensing voltage in a ROM cell area of the cell array 330 of FIG. 4.

In the present invention, one unit cell of one 1T1C structure among the unit cells of the 2T2C structure is not connected to the bit line BL or the bit line bar / BL. Accordingly, the sensing voltage of the unit cell RC not connected to the bit line BL or the bit line bar / BL maintains the precharge voltage.

For example, assume that the structure of the unit cell RC1 is connected to the bit line BL, and the structure of the unit cell RC2 is separated from the bit line bar / BL. Then, the bit line bar / BL which is not connected to the unit cell RC2 before the sense amplifier 340 is activated maintains the precharge voltage level without changing the voltage level.

On the other hand, before the sense amplifier 340 is activated, the bit line BL connected to the unit cell RC1 is raised to a high sensing voltage level higher than the precharge voltage by the storage charge of the ferroelectric capacitor RFC1.

Thereafter, after the sense amplifier 340 is activated, the bit line bar / BL which is not connected to the unit cell RC2 may increase a little voltage due to the operation of the sense amplifier 340, but still maintain the precharge voltage level. Done.

On the other hand, after the sense amplifier 340 is activated, the bit line BL connected to the unit cell RC1 is further increased due to the amplification operation of the sense amplifier 340. Accordingly, the characteristic of the ROM that ensures that 'high data' is always output by the unit cell RC1 of the 1T1C structure connected to the bit line BL is guaranteed.

FIG. 7 is a detailed circuit diagram illustrating only a ROM cell area of a cell array 330 according to another exemplary embodiment of the present invention. In FIG. 7, a case where the unit cell RC3 of the ROM cell region has a 1T1C structure will be described as an embodiment.

The ROM cell area of the cell array 330 includes a plurality of unit cells RC3 in an area where the word line WL and the plate line PL intersect with the bit line BL. Here, the unit cell RC3 of the 1T1C structure includes a ferroelectric capacitor RFC3 having one end connected to the plate line PL, and a switching element RT3 connected with the other end of the ferroelectric capacitor RFC3 and controlled by the word line WL.

The unit cell RC4 having a 1T1C structure formed in an area adjacent to the unit cell RC3 and controlled by the same word line WL includes a ferroelectric capacitor RFC4 connected in series between the plate line PL and the bit line BL1 and the switching element RT4. The switching operation RT4 is controlled by the word line WL0. Here, it is preferable that it consists of switching elements RT3 and RT4 NMOS transistor elements.

In the unit cell RC3 connected to the word line WL1 in the unit cell of the ROM cell region having the above configuration, the switching element RT3 is separated from the bit line BL0 in a physical structure, and the unit cell RC4 connected to the word line WL1 has the bit switching element RT4 It is physically connected to the line BL1. Here, the switching element RT3 is implemented such that the connection with the bit line BL0 is blocked from forming the switching element on the mask.

On the contrary, in the unit cell RC3 connected to the word line WLn in the unit cell of the ROM cell region, the switching element RT3 is physically connected to the bit line BL0, and the unit cell RC4 connected to the word line WLn has the switching element RT4 connected to the bit line BL1. It is separated into physical structure. Herein, the switching element RT4 is implemented such that the connection with the bit line BL1 is blocked from forming the switching element on the mask.

The sense amplifier 340 controls its activation state according to the sense amplifier enable signal SEN applied from the signal controller 320 to sense and amplify data carried on the bit line BL. In the embodiment of FIG. 7, each bit line BL is connected to one corresponding sense amplifier 340 to form a one-to-one correspondence structure. The sense amplifier 340 senses data applied from the bit line BL based on the reference voltage REF.

FIG. 8 is a diagram for describing bit line sensing voltages in a ROM cell area of the cell array 330 of FIG. 7.

In the present invention, one unit cell RC of the unit cells of the 1T1C structure is not connected to the bit line BL or to the bit line BL. Accordingly, the sensing voltage of the unit cell RC not connected to the bit line BL maintains the precharge voltage.

For example, assume that the structure of the unit cell RC3 is not connected to the bit line BL0 and the structure of the unit cell RC4 is connected to the bit line BL. Then, before the sense amplifier 340 is activated, the output of the bit line BL1 connected to the unit cell RC4 is higher than 'low data' and lower than 'high data'.

Accordingly, in accordance with this characteristic, the reference voltage R_REF of the ROM cell region is set to a voltage level slightly smaller than the reference voltage M_REF of the main cell region (nonvolatile memory cell region) so that the sensing operation can be normally performed.

Subsequently, after the sense amplifier 340 is activated, the voltage of the bit line BL connected to the unit cell RC4 is further increased due to the amplification operation of the sense amplifier 340. Accordingly, the characteristic of the ROM that ensures that 'high data' is always output by the unit cell RC4 of the 1T1C structure connected to the bit line BL is guaranteed.

9 is a detailed circuit diagram of the reference voltage generator 350 to supply the reference voltage REF to the sense amplifier 340.

The reference voltage generator 350 includes switching elements SW1 and SW2. Here, the switching element SW1 is connected between the reference voltage REF output terminal and the reference voltage R_REF applying terminal to control the switching operation by the ROM reference control signal R_REF_CON. The switching element SW2 is connected between the reference voltage REF output terminal and the reference voltage M_REF applying terminal to control the switching operation by the main reference control signal M_REF_CON.

Here, it is preferable that the switching elements SW1 and SW2 consist of NMOS transistors.

That is, when sensing data stored in the nonvolatile memory cell area in the cell array 330, the main reference control signal M_REF_CON is activated to a high level. Then, the switching element SW2 is turned on and the reference voltage M_REF is output as the reference voltage REF. Accordingly, the sense amplifier 340 senses the voltage of the bit line BL based on the reference voltage M_REF.

On the other hand, when sensing data stored in the ROM cell area in the cell array 330, the ROM reference control signal R_REF_CON is activated to a high level. Then, the switching element SW1 is turned on and the reference voltage R_REF is output as the reference voltage REF. Accordingly, the sense amplifier 340 senses the voltage of the bit line BL based on the reference voltage R_REF.

FIG. 10 is a detailed circuit diagram illustrating the sense amplifier 340 of FIGS. 4 and 7. In FIG. 10, the sense amplifier 340 of FIG. 7 will be described as an embodiment.

The sense amplifier 340 includes PMOS transistors P1 to P3 and NMOS transistors N1 to N3. Here, the PMOS transistors P2 and P3, which are the amplification units, and the NMOS transistors N1 and N2 are connected in a cross coupled structure.

The PMOS transistor P1, which is a pull-up means, is connected between the power supply voltage VDD applying terminal and the common source terminal of the PMOS transistors P2 and P3 to apply the sense amplifier enable signal / SEN through the gate terminal. Here, the sense amplifier enable signal / SEN is an inverted signal of the sense amplifier enable signal SEN.

In addition, the NMOS transistor N3, which is a pull-down means, is connected between the ground voltage VSS applying terminal and the common source terminal of the NMOS transistors N1 and N2 so that the sense amplifier enable signal SEN is applied through the gate terminal.

In the sense amplifier 340 having such a configuration, when the sense amplifier enable signal SEN is activated to a high level, the PMOS transistor P1 and the NMOS transistor N3 are turned on. Then, the data applied to the bit line BL is amplified by the cross-coupled PMOS transistors P2 and P3 and the NMOS transistors N1 and N2.

The memory unit 300 of the RFID device may be divided into various areas according to a function of stored data. For example, it is divided into a RESERVED area, an EPC (Electronic Product Code) area, a TID (Tag ID) area, and a user (USER) area.

Here, the spare area includes a kill password and an access password, and the EPC is device information of an RFID tag for identification. The TID represents a code for a circuit for identifying a tag ID. In addition, the user area corresponds to an area for storing information required by a user in a tag.

These data areas should ensure that no data changes are made after setting the desired data in the initial stage. In this case, after the desired data is written to the ROM cell area of the memory unit 300, the necessary information can be read without changing the data.

As such, in order to set desired data in the ROM cell region, the memory unit 300 must be designed such that a predetermined initial setting value is stored at the manufacturing stage. Accordingly, in the present invention, the unit cell of the 2T2C structure or the unit cell of the 1T1C structure is designed to be physically connected to or disconnected from the bit line.

1 is a block diagram of a conventional RFID device.

2 is a block diagram of an RFID device according to the present invention.

FIG. 3 is a detailed configuration diagram of the memory unit of FIG. 2. FIG.

4 is a detailed circuit diagram of the cell array of FIG.

5 is an operation timing diagram relating to the cell array of FIG.

6 is a view for explaining the operation of the ROM cell region of FIG.

7 is another embodiment of the cell array of FIG.

8 is a view for explaining the operation of the ROM cell region of FIG.

9 is a detailed circuit diagram of a reference voltage generator.

FIG. 10 is a detailed circuit diagram of the sense amplifier of FIG. 3. FIG.

Claims (21)

An RFID device in which a read / write operation of data is performed according to a radio frequency signal applied from an antenna, The memory unit in which the data is stored includes both a nonvolatile memory region for nonvolatile storage of data changed in response to the radio frequency signal, and a ROM region for storing tag information set in a manufacturing step and for which data is not changed. , And the cell array of the ROM region includes at least one or more unit cells that are physically disconnected from the bit line. The RFID device of claim 1, wherein the nonvolatile memory region and the ROM region have a ferroelectric memory cell structure. delete The method of claim 1, wherein the memory unit A wordline decoder for decoding the wordline according to the address; A signal controller which controls driving of the word line and the plate line according to the control signal; A cell array including a nonvolatile memory cell region storing the data nonvolatilely and a ROM cell region in which the data is read; And And a sense amplifier for sensing and amplifying data read from the cell array. 5. The RFID device of claim 4 wherein the nonvolatile memory cell region comprises a ferroelectric capacitor element. The RFID device of claim 4, further comprising an input / output buffer for exchanging data between the sense amplifier and the data bus. The RFID device according to claim 1 or 4, wherein the ROM region shares a sense amplifier with a unit cell having a 2T2C structure including two capacitor elements and two switching elements. 8. The RFID device of claim 7, wherein one of the two switching elements is physically disconnected from the bit line. The RFID device according to claim 1 or 4, wherein the ROM region has a unit cell of a 1T1C structure including one capacitor element and one switching element connected to one sense amplifier. The RFID device of claim 9, wherein the switching element is physically disconnected from the bit line. The method of claim 4, wherein the ROM cell region is The word line and the plate line arranged in a row direction; The bit lines arranged in a column direction; And a unit cell formed in an area where the word line, the plate line, and the bit line cross each other. 12. The RFID device of claim 11, wherein the unit cell is a unit cell of a 2T2C structure consisting of two capacitor elements and two switching elements sharing one sense amplifier. The RFID device of claim 12, wherein one of the two switching elements is physically disconnected from the bit line. The RFID device of claim 13, wherein the unit cell disconnected from the bit line maintains a precharge voltage level. 12. The RFID device according to claim 11, wherein the unit cell is connected to one sense amplifier by a unit cell having a 1T1C structure including one capacitor element and one switching element. The RFID device of claim 15, wherein the switching element is physically disconnected from the bit line. 17. The RFID device of claim 16, wherein the unit cell disconnected from the bit line maintains a precharge voltage level. The RFID device according to claim 4 or 15, further comprising a reference voltage generator for supplying a reference voltage to the sense amplifier. 19. The method of claim 18, wherein the reference voltage generator is configured to supply a first reference voltage when the nonvolatile memory cell region is selected and to supply a second reference voltage lower than the first reference voltage when the ROM cell region is selected. An RFID device. 19. The apparatus of claim 18, wherein the reference voltage generator First switching means for supplying a first reference voltage to the reference voltage when the main reference control signal is activated; And And second switching means for supplying a second reference voltage having a level lower than the first reference voltage to the reference voltage when the ROM reference control signal is activated. The method of claim 4, wherein the sense amplifier Pull-down means for supplying a ground voltage according to the sense amplifier enable signal; Pull-up means for supplying a power supply voltage according to the inverted signal of the sense amplifier enable signal; And And an amplifier configured to amplify the sensing voltage of the bit line during the operation of the pull-down means and the pull-up means.

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