KR101076725B1 - Voltage regulator and rfid apparatus using the same - Google Patents

Abstract

One side of the present invention, by detecting the voltage level of the power supply terminal to detect the power supply voltage to amplify and output a voltage difference between the reference voltage according to the voltage level of the power supply and a predetermined sensing voltage according to the voltage level of the power supply terminal And a pull-down controller for buffering the signal output from the power supply voltage sensing unit to a CMOS level, and an output signal of the pull-down control unit from the power supply terminal to the ground terminal. A voltage regulator including a pull-down driver for controlling the flow of a pull-down current and an RFID device using the same can be provided.

Voltage regulator, reference voltage, pull-down

Description

VOLTAGE REGULATOR AND RFID APPARATUS USING THE SAME

The present invention relates to a voltage regulator and an RFID device using the same, and more particularly, to a voltage regulator capable of providing a stable voltage and an RFID device using the same.

The voltage regulator is a circuit that limits the output signal level to a predetermined range in a specific electric circuit. In recent years, with the miniaturization and integration of devices in large scale integration (LSI), the number of circuits operating at low voltage is increasing. In addition, several circuits with different operating power sources can often be mounted in one LSI. In this case, if an overvoltage above a certain operating voltage is applied to a circuit operating at a low voltage, the circuit may be destroyed because an overcurrent flows through the circuit. Therefore, in the case of outputting a signal from a circuit operating at a high voltage to a circuit operating at a low voltage, the voltage level of the output voltage needs to be limited by a voltage regulator.

RFID (Radio Frequency Identification), also called a smart tag, is a non-contact recognition system that transmits and processes information of objects and surrounding environment information at a radio frequency by attaching a small chip to various items. As an element constituting the RFID system, a circuit inside the RFID tag may operate by receiving energy from a radio signal of a reader without an internal power source. The RFID tag also uses a voltage regulator to prevent excessive voltage from being provided to the circuitry. In the case of a circuit element mounted on an RFID tag, even a small voltage difference may be sensitively reacted or damaged, and thus a voltage regulator capable of supplying a stable voltage is needed. It is also necessary to minimize the power dissipated in the voltage regulator itself.

In order to solve the above problems, an object of the present invention is to provide a voltage regulator that can provide a more stable voltage, minimize the power consumption and an RFID device using the same.

One side of the present invention, by detecting the voltage level of the power supply terminal to detect the power supply voltage to amplify and output a voltage difference between the reference voltage according to the voltage level of the power supply and a predetermined sensing voltage according to the voltage level of the power supply terminal And a pull-down controller for buffering the signal output from the power supply voltage sensing unit to a CMOS level, and an output signal of the pull-down control unit from the power supply terminal to the ground terminal. A voltage regulator can be provided that includes a pull-down driver that controls the flow of pull-down current.

The power supply voltage detection unit may include a reference voltage generation unit formed between a power supply terminal and a ground terminal to output a reference voltage, a sensing unit that outputs a sensing voltage differently set according to the voltage of the power supply terminal, and the reference voltage and the sensing voltage. Each input unit may include an amplifier for amplifying and outputting the difference.

The reference voltage generator includes a pull-up resistor having one end connected to a power supply terminal, a source connected to the other end of the pull-up resistor, a drain connected to a ground terminal, and a drain connected to a gate of the first transistor. And a second transistor having a gate connected to the power supply terminal, a source connected to the other end of the pullup resistor, and the other end of the pullup resistor connected to the amplifier.

The sensing unit is connected between a power supply terminal and a ground terminal in series, n divided voltage resistors having the same resistance value (n is a positive integer), and n-1 voltage sources connected between each of the n divided voltage resistors. A first power connected to a sensing transistor and a gate of each of the n-1 sensing transistors to turn on between a source and a drain of at least two sensing transistors of the n-1 sensing transistors according to a voltage of the power terminal; An on device and a drain of each of the n-1 sensing transistors, and selecting two of the sensing transistors turned on by the first power-on device to output a preset sensing voltage according to the voltage of the power terminal; It may include a sensing voltage output unit.

The sensing unit may be connected in series between a power supply terminal and a ground terminal, and may have 2n voltage divider resistors having the same resistance value (n is a positive integer), and nth voltage divider resistors and n + 1th voltages among the 2n voltage divider resistors. 2n-1 sensing transistors including a plurality of sensing transistors having a source coupled between the divided resistors and a plurality of sensing transistors connected to each other based on the central sensing transistors; A first power-on device connected to a gate of each of the 2n-1 sensing transistors and turning on a source and a drain of the central sensing transistor and at least one sensing transistor according to a voltage of the power supply terminal, and the 2n− A center sense of the sensing transistors connected to the drain of each of the sensing transistors and turned on by the first power-on device; It may comprise a transistor and a select transistor to sense the power supply output voltage sensing stage for outputting a sensing voltage in accordance with a predetermined portion of a voltage.

The sensing transistor may have the same threshold voltage or different threshold voltages.

The amplifier includes a differential amplifier receiving the reference voltage and the sensing voltage as an input, a first resistor formed between the differential amplifier and the power supply terminal, and a second resistor formed between the differential amplifier and the ground terminal. can do.

The pull-down control unit may include a CMOS inverter configured to receive an output signal of the power voltage detection unit, a drain connected to the CMOS inverter, a first transistor for pull-down control connected to a power source, and a source of the A second transistor for pull-down control connected to a CMOS inverter and having a drain connected to a ground terminal, and a gate of the first transistor for pull-down control and a gate of the second transistor for pull-down control connected to the power supply; And a second power-on device for turning on the pull-down control first and second transistors according to the voltage of the stage.

The pull-down driving unit may include a pull-down driving transistor having a gate connected to the pull-down controller, a source connected to a power supply terminal, and a drain connected to a ground terminal.

The voltage regulator may further include at least one inverter connected between the pull-down controller and the pull-down driver.

Another aspect of the present invention, the voltage multiplier (Voltage Multiplier) for receiving the RF signal and outputs the power supply voltage, and detects the power supply voltage magnitude according to the reference voltage and the power supply voltage magnitude according to the power supply voltage magnitude. A power supply voltage detector for amplifying and outputting a voltage difference between the set sensing voltages, a pull-down controller for buffering a signal output from the power supply voltage detector to a CMOS level, and the pull-down controller A voltage regulator including a pull-down driver for controlling the flow of a pull-down current flowing from the power supply terminal to the ground terminal by an output signal of the -down controller, and a power supply voltage regulated by the voltage regulator It is possible to provide an RFID device including a clock generator that receives and generates a clock signal for controlling the digital block.

According to the present invention, it is possible to obtain a voltage regulator and RFID that can provide a more stable voltage and minimize power consumption.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a circuit diagram of a voltage regulator according to an embodiment of the present invention.

Referring to FIG. 1, the voltage regulator 10 according to the present embodiment may include a power supply voltage detector 100, a pull-down controller 200, and a pull-down driver 300.

The power supply voltage detecting unit 100 may detect the magnitude of the input power supply voltage to amplify and output a voltage difference between the reference voltage and the preset sensing voltage.

In the present embodiment, the power supply voltage detector 100 is formed between the power supply terminal VDD and the ground terminal GND to output a reference voltage, and outputs a preset sensing voltage. The sensing unit 120 and the amplifying unit 130 for receiving the reference voltage and the sensing voltage, respectively, amplifies the difference and outputs.

The reference voltage generator 110 may include a pull-up resistor 111 having one end connected to a power supply terminal, a first transistor 112 having a source connected to the other end of the pull-up resistor, and a drain connected to a ground terminal; A drain may be connected to a gate of the transistor 112, a gate may be connected to a power supply terminal, and a source may include a second transistor 113 at the other end of the pull-up resistor 111. The other end of the pull-up resistor 111 may be connected to the amplifier 130. In the present embodiment, the first and second transistors 112 and 113 may be NMOS transistors. A predetermined threshold voltage Vth may be generated between the gate and the source of the first and second transistors 112 and 113. In the present embodiment, when the power supply voltage of the power supply terminal VDD is smaller than the threshold voltages of the first and second transistors, between the source and the drain of each of the first and second transistors 112 and 113. In the off state, the voltage of the power supply terminal VDD may be a reference voltage output from the reference voltage generator. In addition, when the power supply voltage is greater than the threshold voltage, the source and the drain of each of the first and second transistors 112 and 113 are turned on to turn on the second transistor 113. The threshold voltage may be the reference voltage. In the present embodiment, when the voltage applied to the pull-up resistor 111 is greater than the threshold voltage of the first transistor 112, the voltage drop at the pull-up resistor 111 is increased, so that the reference voltage is equal to the second transistor ( 113 may be the threshold voltage. In the present embodiment, the first and second transistors 112 and 113 are described in the form of NMOS, but the first and second transistors may be replaced with the PMOS form.

The sensing unit 120 is connected in series between a power supply terminal and a ground terminal, and has 2n voltage divider resistors 121a to 121n having the same resistance value as each other and nth of the 2n voltage divider resistors. A plurality of sensing transistors having a source coupled between the voltage divider and the n + 1th voltage divider to be paired with each other based on the center sensing transistor N1 and the center sensing transistor; 2n-1 sensing transistors 122a to 122n including (N2 and N2 ', Nn and Nn'), and the gates of the 2n-1 sensing transistors, respectively, and are connected to the center of the power terminal according to the voltage of the power supply terminal. A first power-on device (123) for turning on a sensing transistor and a source and a drain of at least one sensing transistor, and a drain of each of the 2n-1 sensing transistors; 1 power May include sensing the voltage output section 124 for outputting the sensing voltage on the sensing of the preset transistor according to a voltage of said power stage by selecting the central sensing transistor and a sensing transistor by a device.

In the present embodiment, the voltage between the power supply terminal and the ground terminal may be divided into a plurality of voltages having the same magnitude by the voltage divider 121a to 121n.

The first power-on device 123 may turn on the center sensing transistor and at least one source and the drain of the plurality of sensing transistors.

The 2n-1 sensing transistors may have different threshold voltages. In this case, the sensing transistor turned on according to the voltage level of the power supply terminal may vary. In this case, the sensing voltage output unit 124 may select two of the sensing transistors turned on by the first power-on device to output a preset sensing voltage. The preset sensing voltage may be a voltage preset according to the voltage of the power supply terminal.

In addition, the 2n-1 sensing transistors may have the same threshold voltage. In this case, when the voltage level of the power supply terminal reaches a constant size, all of the 2n-1 sensing transistors may be turned on. In this case, the sensing voltage output unit 124 may select two of the sensing transistors turned on by the first power-on device to output a preset sensing voltage according to a preset sensing voltage. . In the present exemplary embodiment, another sensing transistor may be selected by using the voltage of the central sensing transistor N1 as a reference voltage to output a preset sensing voltage.

The amplifier 130 includes a differential amplifier 131 receiving the reference voltage and the sensing voltage as an input, a first resistor 132 formed between the differential amplifier and the power supply terminal, and the differential amplifier and the ground. It may include a second resistor 133 formed between the stages.

The differential amplifier 131 receives a reference voltage output from the reference voltage generator 110 through a positive input terminal (+), and inputs a sensing voltage output from the sensing unit 120 to a negative input terminal (-). In response, the difference between the reference voltage and the sensing voltage may be amplified and output. In the present embodiment, the differential amplifier may be implemented in a form in which two transistors are connected.

The first and second resistors 132 and 133 are formed between the differential amplifier 131 and the power supply terminal VDD and the differential amplifier 131 and the ground terminal GND, respectively. It can be implemented with a high resistance component to reduce current consumption. In the present embodiment, the first resistor and the second resistor may be respectively connected to two transistors forming the differential amplifier. The first and second resistors 132 and 133 serve to stabilize voltage levels, respectively, to reduce current consumption in the amplifier 130.

The pull-down controller 200 may buffer the signal output from the power supply voltage detector 100 to change the CMOS level.

In the present embodiment, the pull-down control unit 200 includes a CMOS inverter 210 that receives an output signal of the power voltage detection unit, a pull-down in which a drain is connected to the CMOS inverter and a source is connected to a power supply terminal. A control first transistor 231, a pull-down control second transistor 232 having a source connected to the CMOS inverter and a drain connected to a ground terminal, and gates and pull-downs of the pull-down control first transistor. And a second power-on device 220 connected to the gate of the second control transistor for turning on the pull-down control first and second transistors according to the voltage of the power supply terminal.

The CMOS inverter 210 may include an NMOS transistor and a PMOS transistor. In the present embodiment, the CMOS inverter 210 may operate the NMOS transistor or the PMOS transistor according to a signal output from the differential amplifier 131 of the power supply voltage sensing unit 100. That is, when the signal output from the differential amplifier 131 is low, the PMOS transistor is turned on so that the output signal of the CMOS inverter 210 may be high. When the signal output from the differential amplifier 131 is high, the NMOS transistor is turned on so that the output signal of the CMOS inverter 210 may be low.

In the present embodiment, the pull-down control first transistor 231 and the pull-down control second transistor 232 connected to the CMOS inverter 210 may be NMOS transistors. Gates of the first and second transistors 231 and 232 for the pull-down control may be connected to the second power-on device 220. By the operation of the second power-on device 220, the on-off operation between the source and the drain of each of the pull-down control first and second transistors 231 and 232 may be controlled. The second power-on device 220 may operate when a stable voltage is input from the power supply terminal VDD to turn on the source and the drain of each of the first and second transistors for the pull-down control. The first and second transistors 231 and 232 for pull-down control may be high resistance components. The pull-down control first and second transistors 231 and 232 stabilize the level when the CMOS inverter 210 is turned on high or low, thereby controlling the pull-down control unit 200. This reduces the current consumption at. The first and second transistors for pull-down control may be replaced with PMOS transistors.

The pull-down driving unit 300 may control the flow of the pull-down current flowing from the power supply terminal VDD to the ground terminal GND by the output signal of the pull-down control unit 200. In the present embodiment, the pull-down driving unit 300 includes a pull-gate having a gate connected to the pull-down control unit 200, a source connected to a power supply terminal VDD, and a drain connected to a ground terminal GND. The down driving transistor 310 may be included. In this embodiment, the pull-down driving transistor may be an NMOS transistor. However, the pull-down driving transistor may be implemented in the form of a PMOS.

When the output signal of the CMOS inverter 210 is input to the gate of the pull-down driving transistor 310 in a high state, the source and drain of the pull-down driving transistor 310 are turned on. The control current may flow from the power supply terminal VDD to the ground terminal GND. Therefore, the voltage between the power supply terminal VDD and the ground terminal GND can be kept constant.

The voltage regulator 10 according to the present embodiment may further include at least one inverter 400 connected between the pull-down control unit 200 and the pull-down driving unit 300. In the present exemplary embodiment, the first inverter 410 and the second inverter 420 connected in series delay the signal output from the pull-down controller 200 for a predetermined time and input the same to the pull-down driving unit 300. You can.

2 shows the voltage detected at each node of the voltage regulator according to one embodiment of the present invention.

Referring to FIG. 2, the voltage (a) of the power supply terminal, the sensing voltage (c) output from the sensing unit, the reference voltage (d) output from the reference voltage generator, and the pull-down signal (b) input to the pull-down driving unit ).

Until the voltage (a) of the power supply terminal is equal to or greater than a predetermined voltage, the reference voltage (d) is greater than the sensing voltage (c) so that the pull-down signal may maintain a low state. In this case, in FIG. 1, the transistor 310 of the pull-down driving unit is turned off so that the voltage of the power terminal may be a voltage output from the voltage regulator.

After the voltage (a) of the power supply terminal reaches a predetermined voltage or more, the sensing voltage (c) becomes larger than the reference voltage (d). At this time, the pull-down signal may be in a high state. In this case, the transistor 310 of the pull-down driving unit is turned on in FIG. 1 to maintain a constant voltage between the power supply terminal and the ground terminal even when the voltage of the power supply terminal is greater than the predetermined voltage. Therefore, the voltage output from the voltage regulator can maintain a constant voltage.

3 is a configuration diagram of an RFID tag in which a voltage regulator according to an embodiment of the present invention is used.

The RFID tag 500 according to the present embodiment may include an antenna 501, an analog block 510, a digital block 520, and a FeRAM block 530.

The antenna 501 may exchange data with an external reader / writer.

When the antenna 501 receives the RF signal, a voltage multiplier 511 may generate a power supply voltage VDD which is a driving voltage of the RFID by the RF signal in the analog block 510. have. A power on reset 515 senses the output voltage VDD of the voltage multiplier 511 and outputs a power-on reset signal to the digital block 520 for controlling a reset operation. can do. The clock generator 516 may generate a clock signal for controlling the digital block 520 according to the output voltage of the voltage multiplier 511. The demodulator 514 detects an operation command signal from a radio frequency signal applied from an antenna according to the output voltages of the voltage multiplier 511 and the voltage regulator 512 and outputs the command signal to the digital block 520. Can be. The modulator 513 may modulate the response signal applied from the digital block 520 and transmit the modulated response signal to the antenna 501.

The voltage regulator 512 limits the magnitude of the power voltage output from the voltage multiplier 511 by the radio frequency signal applied from the antenna 501 to the demodulator 514 and the clock generator 516. You can print In the present embodiment, the voltage regulator 512 may use the voltage regulator described in FIG. 1.

The digital block 520 processes the VDD, the response, the POR, the CLK, the command, etc., which are signals for power and data transmission with the analog block 510, and the address signal ADD, which communicates with the FeRAM block 530, I / O, a data bus signal, CTR, a control signal, and CLK, a clock signal, can be input and output. The FeRAM block 530 may be a memory block that reads / writes data using a nonvolatile ferroelectric capacitor.

It is intended that the invention not be limited by the foregoing embodiments and the accompanying drawings, but rather by the claims appended hereto. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

1 is a circuit diagram of a voltage regulator according to an embodiment of the present invention.

2 is a graph showing the voltage at each node of the voltage regulator according to the embodiment of the present invention.

3 is a configuration diagram of an RFID tag using a voltage regulator according to another embodiment of the present invention.

<Code Description of Main Parts of Drawing>

100: power supply voltage detection unit 200: pull-down control unit

300: pull-down drive unit

Claims (22)

Detects the voltage level of the power supply terminal, generates a reference voltage determined according to the voltage level of the power supply terminal and a preset sensing voltage according to the voltage level of the power supply terminal, and amplifies the voltage difference between the reference voltage and the sensing voltage. A power supply voltage detector for outputting the power supply; A pull-down controller configured to buffer the signal output from the power supply voltage detector and change the signal to a CMOS level; And Pull-down driving unit for controlling the flow of the pull-down current flowing from the power supply terminal to the ground terminal by the output signal of the pull-down controller Voltage regulator comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The power supply voltage detector, A reference voltage generator formed between a power supply terminal and a ground terminal to output a reference voltage; A sensing unit configured to output a sensing voltage differently set according to the voltage of the power terminal; And An amplifier which receives the reference voltage and the sensing voltage and amplifies the difference and outputs the difference; Voltage regulator comprising a. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, The reference voltage generator, A pull-up resistor, one end of which is connected to a power supply terminal; A first transistor having a source connected to the other end of the pull-up resistor and a drain connected to a ground end; And A second transistor having a drain connected to a gate of the first transistor, a gate connected to the power supply terminal, and a source connected to the other end of the pull-up resistor The voltage regulator of claim 1, wherein the other end of the pull-up resistor is connected to the amplifier. Claim 4 was abandoned when the registration fee was paid. 3. The method of claim 2, The sensing unit, N voltage divider resistors connected in series between the power supply terminal and the ground terminal and having the same resistance value as each other (n is an integer of 3 or more); N-1 sensing transistors having a source connected between each of the n voltage divider resistors; A first power-on device connected to a gate of each of the n-1 sensing transistors to turn on between a source and a drain of at least two sensing transistors of the n-1 sensing transistors according to a voltage of the power terminal; And A sensing voltage output connected to a drain of each of the n-1 sensing transistors, and outputting a sensing voltage preset according to a voltage of the power supply terminal by selecting two of the sensing transistors turned on by the first power-on device part Voltage regulator comprising a. Claim 5 was abandoned upon payment of a set-up fee. 3. The method of claim 2, The sensing unit, 2n voltage divider resistors connected in series between the power supply terminal and the ground terminal and having the same resistance value as each other (n is an integer of 2 or more); A center sensing transistor having a source connected between an nth voltage divider resistor and an n + 1th voltage divider resistor among the 2n voltage divider resistors is disposed to be paired with each other based on the center sensing transistor, and a source is connected between each of the voltage divider resistors. 2n-1 sensing transistors including a plurality of sensing transistors; A first power-on device connected to a gate of each of the 2n-1 sensing transistors and turning on a source and a drain of the central sensing transistor and at least one sensing transistor according to a voltage of the power terminal; And The central sensing transistor and one sensing transistor selected from the sensing transistors turned on by the first power-on device, and are preset according to a voltage of the power supply terminal. Sensing voltage output unit for outputting voltage Voltage regulator comprising a. Claim 6 was abandoned when the registration fee was paid. The method according to claim 4 or 5, The sensing transistor, And a voltage regulator having the same threshold voltage. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 4 or 5, The sensing transistor, A voltage regulator comprising different threshold voltages. Claim 8 was abandoned when the registration fee was paid. 3. The method of claim 2, The amplification unit, A differential amplifier receiving the reference voltage and the sensing voltage as inputs; A first resistor formed between the differential amplifier and the power supply terminal; And A second resistor formed between the differential amplifier and the ground terminal Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The pull-down control unit, A CMOS inverter receiving the output signal of the power supply voltage detector; A pull-down control first transistor connected to a drain of the CMOS inverter and a source connected to a power supply terminal; A second transistor for pull-down control, a source connected to the CMOS inverter, and a drain connected to a ground terminal; And A first transistor connected to a gate of the first transistor for pull-down control and a gate of the second transistor for pull-down control to turn on the first and second transistors for pull-down control according to a voltage of the power supply terminal; 2 power-on unit Voltage regulator comprising a. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The pull-down drive unit, A pull-down driving transistor having a gate connected to the pull-down controller, a source connected to a power supply terminal, and a drain connected to a ground terminal Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, At least one inverter connected between the pull-down control unit and the pull-down driving unit The voltage regulator further comprises. A voltage multiplier for receiving an RF signal and outputting a power supply voltage; Detects the magnitude of the power voltage output from the voltage multiplier to generate a reference voltage determined according to the power voltage magnitude and a preset sensing voltage according to the power voltage magnitude, and calculates a voltage difference between the reference voltage and the sensing voltage. A power supply voltage detector for amplifying and outputting a pull-down controller for buffering the signal output from the power supply voltage detector to a CMOS level, and an output signal of the pull-down controller A voltage regulator including a pull-down driver for controlling the flow of pull-down current flowing from the power stage to the ground stage; And A clock generator that receives the power supply voltage regulated by the voltage regulator and generates a clock signal for controlling the digital block. RFID device comprising a. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12, The power supply voltage detector, A reference voltage generator formed between a power supply terminal and a ground terminal to output a reference voltage; A sensing unit configured to output a sensing voltage differently set according to the voltage of the power terminal; And An amplifier which receives the reference voltage and the sensing voltage and amplifies the difference and outputs the difference; RFID device comprising a. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, The reference voltage generator, A pull-up resistor, one end of which is connected to a power supply terminal; A first transistor having a source connected to the other end of the pull-up resistor and a drain connected to a ground end; And A second transistor having a drain connected to a gate of the first transistor, a gate connected to the power supply terminal, and a source connected to the other end of the pull-up resistor And the other end of the pull-up resistor is connected to the amplifier. Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, The sensing unit, N voltage divider resistors connected in series between the power supply terminal and the ground terminal and having the same resistance value as each other (n is an integer of 3 or more); N-1 sensing transistors having a source connected between each of the n voltage divider resistors; A first power-on device connected to a gate of each of the n-1 sensing transistors to turn on between a source and a drain of at least two sensing transistors of the n-1 sensing transistors according to a voltage of the power terminal; And A sensing voltage output connected to a drain of each of the n-1 sensing transistors, and outputting a sensing voltage preset according to a voltage of the power supply terminal by selecting two of the sensing transistors turned on by the first power-on device part RFID device comprising a. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 13, The sensing unit, 2n voltage divider resistors connected in series between the power supply terminal and the ground terminal and having the same resistance value as each other (n is an integer of 2 or more); A center sensing transistor having a source connected between an nth voltage divider resistor and an n + 1th voltage divider resistor among the 2n voltage divider resistors is disposed to be paired with each other based on the center sensing transistor, and a source is connected between each of the voltage divider resistors. 2n-1 sensing transistors including a plurality of sensing transistors; A first power-on device connected to a gate of each of the 2n-1 sensing transistors and turning on a source and a drain of the central sensing transistor and at least one sensing transistor according to a voltage of the power terminal; And The central sensing transistor and one sensing transistor selected from the sensing transistors turned on by the first power-on device, and are preset according to a voltage of the power supply terminal. Sensing voltage output unit for outputting voltage RFID device comprising a. Claim 17 has been abandoned due to the setting registration fee. The method according to claim 15 or 16, The sensing transistor, RFID device having the same threshold voltage. Claim 18 was abandoned upon payment of a set-up fee. The method according to claim 15 or 16, The sensing transistor, RFID device having different threshold voltages. Claim 19 was abandoned upon payment of a registration fee. The method of claim 13, The amplification unit, A differential amplifier receiving the reference voltage and the sensing voltage as inputs; A first resistor formed between the differential amplifier and the power supply terminal; And A second resistor formed between the differential amplifier and the ground terminal RFID device comprising a. Claim 20 was abandoned upon payment of a registration fee. The method of claim 12, The pull-down control unit, A CMOS inverter receiving the output signal of the power supply voltage detector; A pull-down control first transistor connected to a drain of the CMOS inverter and a source connected to a power supply terminal; A second transistor for pull-down control, a source connected to the CMOS inverter, and a drain connected to a ground terminal; And A first transistor connected to a gate of the first transistor for pull-down control and a gate of the second transistor for pull-down control to turn on the first and second transistors for pull-down control according to a voltage of the power supply terminal; 2 power-on unit RFID device comprising a. Claim 21 has been abandoned due to the setting registration fee. The method of claim 12, The pull-down drive unit, A pull-down driving transistor having a gate connected to the pull-down controller, a source connected to a power supply terminal, and a drain connected to a ground terminal RFID device comprising a. Claim 22 is abandoned in setting registration fee. The method of claim 12, At least one inverter connected between the pull-down control unit and the pull-down driving unit RFID device further comprising.

Images