KR0172234B1 - 셀프 리프레쉬 주기 조절장치 - Google Patents
셀프 리프레쉬 주기 조절장치 Download PDFInfo
- Publication number
- KR0172234B1 KR0172234B1 KR1019950006320A KR19950006320A KR0172234B1 KR 0172234 B1 KR0172234 B1 KR 0172234B1 KR 1019950006320 A KR1019950006320 A KR 1019950006320A KR 19950006320 A KR19950006320 A KR 19950006320A KR 0172234 B1 KR0172234 B1 KR 0172234B1
- Authority
- KR
- South Korea
- Prior art keywords
- leakage current
- temperature
- node
- type
- output
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (4)
- 셀프 리프레쉬 동작을 위해 일정한 주기를 갖는 펄스신호를 출력하는 링 발진기와, 셀에 저장된 전하가 방전되어 셀 데이타가 파괴될때 생기는 누설전류를 감지한 신호를 출력하기 위한 누설전류 감지 수단과, 상기 누설전류 감지 수단으로부터의 출력과 온도에 따라 각각 저항성분이 다른 두 저항소자로부터 분주된 기준전압을 비교·증폭하여 칩의 온도 변화를 감지하는 온도 검출수단과, 상기 온도 검출수단으로부터 출력된 신호에 의해 상기 링 발진기의 출력을 적정 비율로 분주하여 리프레쉬 주기를 변화시키는 주파수 드라이버 수단을 구비하는 것을 특징으로 하는 셀프 리프레쉬 주기 조절장치.
- 제1항에 있어서, 상기 온도 검출수단 및 주파수 드라이버 수단은 두개 이상으로 구성되어 칩의 온도 변화에 따라 각기 다른 주기의 펄스신호를 출력하는 것을 특징으로 하는 셀프 리프레쉬 주기 조절장치.
- 제1항에 있어서, 상기 누설전류 감지 수단은 셀에서의 누설전류에 비례하는 값을 얻도록 P형 기판에 N-웰로 구성되며, 상기 P형 기판 및 N-웰 상에 도우핑된 P+형 불순물 확산 영역에 기판전위가 인가되고 상기 N-웰 상에 도우핑된 N+형 불순물 확산 영역으로는 저항을 통하여 전원전위가 인가되는 것을 특징으로 하는 셀프 리프레쉬 주기 조절장치.
- 제1항에 있어서, 상기 누설전류 감지 수단은 P형 기판위에 N-웰을 도우핑하고, 상기 N-웰상에 다시 P-웰을 도우핑한 다음, 상기 P-웰 상에 N+형 불순물 확산 영역과 P+형 불순물 확산 영역을 도우핑하고 상기 N+형 불순물 확산 영역으로 전원전압이 인가되고 상기 P+형 불순물 확산 영역으로는 저항을 통하여 기판전위가 인가되는 것을 특징으로 하는 셀프 리프레쉬 주기 조절장치.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950006320A KR0172234B1 (ko) | 1995-03-24 | 1995-03-24 | 셀프 리프레쉬 주기 조절장치 |
US08/619,221 US5680359A (en) | 1995-03-24 | 1996-03-21 | Self-refresh period adjustment circuit for semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950006320A KR0172234B1 (ko) | 1995-03-24 | 1995-03-24 | 셀프 리프레쉬 주기 조절장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960035634A KR960035634A (ko) | 1996-10-24 |
KR0172234B1 true KR0172234B1 (ko) | 1999-03-30 |
Family
ID=19410483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950006320A KR0172234B1 (ko) | 1995-03-24 | 1995-03-24 | 셀프 리프레쉬 주기 조절장치 |
Country Status (2)
Country | Link |
---|---|
US (1) | US5680359A (ko) |
KR (1) | KR0172234B1 (ko) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100520580B1 (ko) * | 2002-07-16 | 2005-10-10 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100803352B1 (ko) * | 2006-06-12 | 2008-02-14 | 주식회사 하이닉스반도체 | 반도체 메모리의 리프레쉬 제어장치 및 방법 |
KR100834404B1 (ko) * | 2007-01-03 | 2008-06-04 | 주식회사 하이닉스반도체 | 리프레쉬신호 생성수단을 포함하는 반도체메모리소자와그의 구동방법 |
US11868153B2 (en) | 2021-09-07 | 2024-01-09 | SK Hynix Inc. | Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956289A (en) * | 1997-06-17 | 1999-09-21 | Micron Technology, Inc. | Clock signal from an adjustable oscillator for an integrated circuit |
US6075744A (en) * | 1997-10-10 | 2000-06-13 | Rambus Inc. | Dram core refresh with reduced spike current |
KR100490297B1 (ko) * | 1997-12-29 | 2005-08-18 | 주식회사 하이닉스반도체 | 기준전압발생회로 |
US6134167A (en) * | 1998-06-04 | 2000-10-17 | Compaq Computer Corporation | Reducing power consumption in computer memory |
KR100363105B1 (ko) * | 1998-12-23 | 2003-02-19 | 주식회사 하이닉스반도체 | 셀 리키지 커런트 보상용 셀프 리프레쉬 장치 |
KR100546102B1 (ko) * | 1999-06-30 | 2006-01-24 | 주식회사 하이닉스반도체 | 셀 누설전류 감시 회로 |
KR100631935B1 (ko) * | 2000-06-30 | 2006-10-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 셀프 리프레시 회로 |
US6483764B2 (en) * | 2001-01-16 | 2002-11-19 | International Business Machines Corporation | Dynamic DRAM refresh rate adjustment based on cell leakage monitoring |
JP2003132676A (ja) * | 2001-10-29 | 2003-05-09 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4021643B2 (ja) * | 2001-10-29 | 2007-12-12 | 富士通株式会社 | 温度検出機能を備えた半導体装置 |
US6714473B1 (en) | 2001-11-30 | 2004-03-30 | Cypress Semiconductor Corp. | Method and architecture for refreshing a 1T memory proportional to temperature |
DE10214103A1 (de) * | 2002-03-28 | 2003-10-23 | Infineon Technologies Ag | Oszillator mit einstellbaren Temparturgradienten der Referenzspannung und virtuellem Ground |
US6882172B1 (en) * | 2002-04-16 | 2005-04-19 | Transmeta Corporation | System and method for measuring transistor leakage current with a ring oscillator |
US7315178B1 (en) * | 2002-04-16 | 2008-01-01 | Transmeta Corporation | System and method for measuring negative bias thermal instability with a ring oscillator |
US7941675B2 (en) * | 2002-12-31 | 2011-05-10 | Burr James B | Adaptive power control |
US7112978B1 (en) | 2002-04-16 | 2006-09-26 | Transmeta Corporation | Frequency specific closed loop feedback control of integrated circuits |
US6898138B2 (en) * | 2002-08-29 | 2005-05-24 | Micron Technology, Inc. | Method of reducing variable retention characteristics in DRAM cells |
US7886164B1 (en) | 2002-11-14 | 2011-02-08 | Nvidia Corporation | Processor temperature adjustment system and method |
US7849332B1 (en) | 2002-11-14 | 2010-12-07 | Nvidia Corporation | Processor voltage adjustment system and method |
US7882369B1 (en) | 2002-11-14 | 2011-02-01 | Nvidia Corporation | Processor performance adjustment system and method |
US7949864B1 (en) | 2002-12-31 | 2011-05-24 | Vjekoslav Svilan | Balanced adaptive body bias control |
US7953990B2 (en) * | 2002-12-31 | 2011-05-31 | Stewart Thomas E | Adaptive power control based on post package characterization of integrated circuits |
DE10302292B3 (de) * | 2003-01-22 | 2004-04-29 | Infineon Technologies Ag | Verfahren und Regelschaltung zum Auffrischen von dynamischen Speicherzellen |
US6778457B1 (en) * | 2003-02-19 | 2004-08-17 | Freescale Semiconductor, Inc. | Variable refresh control for a memory |
US7034507B2 (en) * | 2003-07-03 | 2006-04-25 | Micron Technology, Inc. | Temperature sensing device in an integrated circuit |
KR100546347B1 (ko) * | 2003-07-23 | 2006-01-26 | 삼성전자주식회사 | 온도 검출 회로 및 온도 검출 방법 |
KR100541824B1 (ko) * | 2003-10-06 | 2006-01-10 | 삼성전자주식회사 | 반도체 집적회로에 채용하기 적합한 온도감지 회로 |
US7649402B1 (en) * | 2003-12-23 | 2010-01-19 | Tien-Min Chen | Feedback-controlled body-bias voltage source |
KR100611775B1 (ko) * | 2003-12-29 | 2006-08-10 | 주식회사 하이닉스반도체 | 온도변화에 따라 최적의 리프레쉬 주기를 가지는 반도체메모리 장치 |
JP4744807B2 (ja) * | 2004-01-06 | 2011-08-10 | パナソニック株式会社 | 半導体集積回路装置 |
US7158422B2 (en) * | 2004-02-27 | 2007-01-02 | Micron Technology, Inc. | System and method for communicating information to a memory device using a reconfigured device pin |
US7498846B1 (en) | 2004-06-08 | 2009-03-03 | Transmeta Corporation | Power efficient multiplexer |
US7336103B1 (en) | 2004-06-08 | 2008-02-26 | Transmeta Corporation | Stacked inverter delay chain |
US7142018B2 (en) | 2004-06-08 | 2006-11-28 | Transmeta Corporation | Circuits and methods for detecting and assisting wire transitions |
US7405597B1 (en) | 2005-06-30 | 2008-07-29 | Transmeta Corporation | Advanced repeater with duty cycle adjustment |
US7635992B1 (en) | 2004-06-08 | 2009-12-22 | Robert Paul Masleid | Configurable tapered delay chain with multiple sizes of delay elements |
US7173455B2 (en) | 2004-06-08 | 2007-02-06 | Transmeta Corporation | Repeater circuit having different operating and reset voltage ranges, and methods thereof |
US7304503B2 (en) | 2004-06-08 | 2007-12-04 | Transmeta Corporation | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
US7656212B1 (en) | 2004-06-08 | 2010-02-02 | Robert Paul Masleid | Configurable delay chain with switching control for tail delay elements |
US7071747B1 (en) * | 2004-06-15 | 2006-07-04 | Transmeta Corporation | Inverting zipper repeater circuit |
US7330080B1 (en) | 2004-11-04 | 2008-02-12 | Transmeta Corporation | Ring based impedance control of an output driver |
US7592842B2 (en) * | 2004-12-23 | 2009-09-22 | Robert Paul Masleid | Configurable delay chain with stacked inverter delay elements |
KR100631167B1 (ko) * | 2004-12-30 | 2006-10-02 | 주식회사 하이닉스반도체 | 셀프 리프레쉬 주기 발생장치 및 그 오실레이션 신호발생방법 |
KR100610024B1 (ko) * | 2005-01-27 | 2006-08-08 | 삼성전자주식회사 | 셀프 리프레쉬 모드를 가지는 반도체 메모리 장치 및 그의동작 방법 |
KR100733471B1 (ko) * | 2005-02-28 | 2007-06-28 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 지연 고정 루프 회로 및 그 제어 방법 |
US7739531B1 (en) | 2005-03-04 | 2010-06-15 | Nvidia Corporation | Dynamic voltage scaling |
US7663408B2 (en) * | 2005-06-30 | 2010-02-16 | Robert Paul Masleid | Scannable dynamic circuit latch |
US20070013425A1 (en) * | 2005-06-30 | 2007-01-18 | Burr James B | Lower minimum retention voltage storage elements |
KR100656430B1 (ko) * | 2005-11-09 | 2006-12-11 | 주식회사 하이닉스반도체 | 온도 검출 장치 |
US7394681B1 (en) | 2005-11-14 | 2008-07-01 | Transmeta Corporation | Column select multiplexer circuit for a domino random access memory array |
KR100654003B1 (ko) * | 2005-11-29 | 2006-12-06 | 주식회사 하이닉스반도체 | 반도체 장치의 셀프 리프레쉬 주기 측정회로 |
US7414485B1 (en) * | 2005-12-30 | 2008-08-19 | Transmeta Corporation | Circuits, systems and methods relating to dynamic ring oscillators |
US7642866B1 (en) | 2005-12-30 | 2010-01-05 | Robert Masleid | Circuits, systems and methods relating to a dynamic dual domino ring oscillator |
KR100776748B1 (ko) * | 2006-05-09 | 2007-11-19 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리프레쉬 제어 회로 및 방법 |
US7512029B2 (en) * | 2006-06-09 | 2009-03-31 | Micron Technology, Inc. | Method and apparatus for managing behavior of memory devices |
US7495466B1 (en) | 2006-06-30 | 2009-02-24 | Transmeta Corporation | Triple latch flip flop system and method |
US7710153B1 (en) * | 2006-06-30 | 2010-05-04 | Masleid Robert P | Cross point switch |
US9134782B2 (en) | 2007-05-07 | 2015-09-15 | Nvidia Corporation | Maintaining optimum voltage supply to match performance of an integrated circuit |
US8370663B2 (en) * | 2008-02-11 | 2013-02-05 | Nvidia Corporation | Power management with dynamic frequency adjustments |
US7876135B2 (en) * | 2008-02-29 | 2011-01-25 | Spectra Linear, Inc. | Power-on reset circuit |
KR100937939B1 (ko) * | 2008-04-24 | 2010-01-21 | 주식회사 하이닉스반도체 | 반도체 소자의 내부전압 생성회로 |
US9256265B2 (en) | 2009-12-30 | 2016-02-09 | Nvidia Corporation | Method and system for artificially and dynamically limiting the framerate of a graphics processing unit |
US9830889B2 (en) | 2009-12-31 | 2017-11-28 | Nvidia Corporation | Methods and system for artifically and dynamically limiting the display resolution of an application |
US8839006B2 (en) | 2010-05-28 | 2014-09-16 | Nvidia Corporation | Power consumption reduction systems and methods |
US20140244548A1 (en) * | 2013-02-22 | 2014-08-28 | Nvidia Corporation | System, method, and computer program product for classification of silicon wafers using radial support vector machines to process ring oscillator parametric data |
KR20160095468A (ko) * | 2015-02-03 | 2016-08-11 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6061992A (ja) * | 1983-09-14 | 1985-04-09 | Nec Corp | 擬似スタティックメモリ |
US5278796A (en) * | 1991-04-12 | 1994-01-11 | Micron Technology, Inc. | Temperature-dependent DRAM refresh circuit |
KR950010624B1 (ko) * | 1993-07-14 | 1995-09-20 | 삼성전자주식회사 | 반도체 메모리장치의 셀프리프레시 주기조절회로 |
KR0129197B1 (ko) * | 1994-04-21 | 1998-10-01 | 문정환 | 메모리셀어레이의 리플레쉬 제어회로 |
KR0179097B1 (ko) * | 1995-04-07 | 1999-04-15 | 김주용 | 데이타 리드/라이트 방법 및 장치 |
-
1995
- 1995-03-24 KR KR1019950006320A patent/KR0172234B1/ko not_active IP Right Cessation
-
1996
- 1996-03-21 US US08/619,221 patent/US5680359A/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100520580B1 (ko) * | 2002-07-16 | 2005-10-10 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100803352B1 (ko) * | 2006-06-12 | 2008-02-14 | 주식회사 하이닉스반도체 | 반도체 메모리의 리프레쉬 제어장치 및 방법 |
US7474580B2 (en) | 2006-06-12 | 2009-01-06 | Hynix Semiconductor Inc. | Apparatus and method for controlling refresh operation of semiconductor integrated circuit |
KR100834404B1 (ko) * | 2007-01-03 | 2008-06-04 | 주식회사 하이닉스반도체 | 리프레쉬신호 생성수단을 포함하는 반도체메모리소자와그의 구동방법 |
US7672184B2 (en) | 2007-01-03 | 2010-03-02 | Hynix Semiconductor Inc. | Semiconductor memory device with refresh signal generator and its driving method |
US11868153B2 (en) | 2021-09-07 | 2024-01-09 | SK Hynix Inc. | Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same |
Also Published As
Publication number | Publication date |
---|---|
US5680359A (en) | 1997-10-21 |
KR960035634A (ko) | 1996-10-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR0172234B1 (ko) | 셀프 리프레쉬 주기 조절장치 | |
JP3780030B2 (ja) | 発振回路およびdram | |
US5805508A (en) | Semiconductor memory device with reduced leak current | |
US7489184B2 (en) | Device and method for generating a low-voltage reference | |
KR0129197B1 (ko) | 메모리셀어레이의 리플레쉬 제어회로 | |
US6731558B2 (en) | Semiconductor device | |
US6201437B1 (en) | Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor | |
US6809576B1 (en) | Semiconductor integrated circuit device having two types of internal power supply circuits | |
US5097303A (en) | On-chip voltage regulator and semiconductor memory device using the same | |
KR0158478B1 (ko) | 반도체 메모리장치의 기판전압 조절회로 | |
US5545977A (en) | Reference potential generating circuit and semiconductor integrated circuit arrangement using the same | |
KR940009250B1 (ko) | 복수개의 동작전압에 대응하는 리프레쉬 타이머 | |
US20030189859A1 (en) | Timer circuit and semiconductor memory incorporating the timer circuit | |
JPH0660648A (ja) | パルス信号発生回路および半導体記憶装置 | |
US20030218931A1 (en) | Semiconductor memory device requiring refresh operation | |
US6690226B2 (en) | Substrate electric potential sense circuit and substrate electric potential generator circuit | |
US6967877B2 (en) | Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device | |
US4905199A (en) | Method of and apparatus for reducing current of semiconductor memory device | |
KR0140175B1 (ko) | 반도체 메모리 장치의 센스앰프 회로 | |
US5313435A (en) | Semiconductor memory device having address transition detector | |
US7977966B2 (en) | Internal voltage generating circuit for preventing voltage drop of internal voltage | |
JP4330585B2 (ja) | 温度依存性を有する電流発生回路 | |
JP3359618B2 (ja) | 遅延時間補正機能を備えた半導体集積回路及び電源回路 | |
US20060229839A1 (en) | Temperature sensing and monitoring technique for integrated circuit devices | |
JP3098808B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19950324 |
|
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19950324 Comment text: Request for Examination of Application |
|
PG1501 | Laying open of application | ||
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19980429 Patent event code: PE09021S01D |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19980828 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19981023 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 19981023 End annual number: 3 Start annual number: 1 |
|
PG1601 | Publication of registration | ||
PR1001 | Payment of annual fee |
Payment date: 20010918 Start annual number: 4 End annual number: 4 |
|
PR1001 | Payment of annual fee |
Payment date: 20020918 Start annual number: 5 End annual number: 5 |
|
PR1001 | Payment of annual fee |
Payment date: 20030919 Start annual number: 6 End annual number: 6 |
|
PR1001 | Payment of annual fee |
Payment date: 20040920 Start annual number: 7 End annual number: 7 |
|
PR1001 | Payment of annual fee |
Payment date: 20050922 Start annual number: 8 End annual number: 8 |
|
PR1001 | Payment of annual fee |
Payment date: 20060920 Start annual number: 9 End annual number: 9 |
|
PR1001 | Payment of annual fee |
Payment date: 20070914 Start annual number: 10 End annual number: 10 |
|
PR1001 | Payment of annual fee |
Payment date: 20081006 Start annual number: 11 End annual number: 11 |
|
PR1001 | Payment of annual fee |
Payment date: 20090922 Start annual number: 12 End annual number: 12 |
|
PR1001 | Payment of annual fee |
Payment date: 20100920 Start annual number: 13 End annual number: 13 |
|
FPAY | Annual fee payment |
Payment date: 20110923 Year of fee payment: 14 |
|
PR1001 | Payment of annual fee |
Payment date: 20110923 Start annual number: 14 End annual number: 14 |
|
FPAY | Annual fee payment |
Payment date: 20120921 Year of fee payment: 15 |
|
PR1001 | Payment of annual fee |
Payment date: 20120921 Start annual number: 15 End annual number: 15 |
|
LAPS | Lapse due to unpaid annual fee | ||
PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20140909 |