KR0130154B1 - Differential amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier of a semiconductor device, and implements an operating voltage control unit using a switching element in a pull-up driving stage and its operating state according to the potential of the power supply voltage Vcc using a power supply voltage detector. By adjusting, the output swing is improved in the case of high power supply voltage, thereby improving the speed delay, and in the case of the low power supply voltage, it is possible to prevent malfunction of the differential amplifier.

Description

Differential amplifier

1 is a circuit diagram of a differential amplifier according to the prior art.

2 is a block diagram of a differential amplifier according to the present invention.

3 is a detailed view of a voltage sensor used in the present invention.

4 is a circuit diagram of a differential amplifier as a first embodiment using the present invention.

5 is a circuit diagram of a differential amplifier as a second embodiment using the present invention.

* Explanation of symbols for main parts of the drawings

100: voltage detector 101: operating voltage control unit

102: differential amplifier 200: power supply voltage divider

201: comparator 202: voltage completion part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier of a semiconductor device. In particular, an operating voltage control unit using a switching device is implemented in a pull-up driving stage and the power supply voltage detector is used according to the potential of the power supply voltage Vcc. The present invention relates to a differential amplifier that realizes stable operation by reducing noise generated from a power supply line inside a chip by adjusting an operating state.

1 is a circuit diagram of a differential amplifier according to the prior art, which is a pull-up driving stage connected between a power supply voltage Vcc and a node N1 and whose operation is controlled by a differential amplifier control signal .phi.SEP. Q1), PMOS transistors Q2 and Q3 having a current mirror type structure connected between the node N1 and the nodes N2 and N4 and whose gates are commonly connected to the node N4, and the nodes N2 and N2, respectively. A source is connected between N4) and node N5, and is connected between NMOS transistors Q4 and Q5 that accept a data input, and between node N5 and ground voltage Vss and to a differential amplifier control signal .phi.SEN. NMOS transistor Q6, which is a pull-down driving stage, whose operation is controlled by the control circuit.

When the differential amplifier control signals ΦSEP and ΦSEN are enabled when the potential difference between the input lines Vg1 and Vg2 is several tens mV or more, the pull-up driving transistor Q1 supplies current from the power supply voltage Vcc to the differential amplifier. The pull-down driving transistor Q6 discharges a current from the differential amplifier to the ground voltage Vss. The voltage signals generated at the nodes N2 and N4 have opposite magnitudes according to the magnitudes of the potential signals Vgl and Vg2 of the input data supplied to the gates of the NMOS transistors Q4 and Q5, respectively. . In fact, when the input potential signal Vg2 is larger than the input potential signal Vg1, the voltage signal generated at the node N2 has a voltage level greater than the voltage signal generated at the node N4. . On the contrary, when the input potential signal Vg2 is smaller than the input potential signal Vg1, the voltage signal generated at the node M2 has a voltage level smaller than the voltage signal generated at the node N4. . The magnitude of the voltage signal generated at the node H2 and the voltage signal generated at the node N4 is proportional to the difference between the input data potential signals Vgl and Vg2.

The NMOS transistor Q6 connected between the node N5 and the ground voltage Vss is a constant current that maintains the total amount of current flowing through the NMOS transistors Q4 and Q5 by the sense amplifier control signal .phi.SEN. It functions as a circle. The sense amplifier is implemented as a differential amplifier composed of PMOS transistors Q2 and Q3 forming a current mirror and NMOS transistors Q4 and Q5 receiving a data input.

Here, the pull-up driving transistor Q1 and the pull-down driving transistor Q6 operate according to the differential amplifier control signals ΦSEP and ΦSEN, respectively, regardless of the potential of the power supply voltage Vcc. In Vcc), a large amount of current flows through the pull-up and pull-down driving stages, resulting in a large output swing, which delays the output time of the differential amplifier during continuous data input.

In addition, in the low potential power supply voltage Vcc, the operation voltage required for the operation of the differential amplifier is low, which causes a problem that the differential amplifier malfunctions.

Accordingly, an object of the present invention is to provide a differential amplifier capable of adjusting the amount of current consumed by the differential amplifier according to the potential of the power supply voltage Vcc.

In order to achieve the above object, the differential amplifier of the present invention outputs the output of the voltage detector as 'logic high' and 'logic low' as the power supply voltage Vcc is high and low. By controlling the operating state of the pull-up drive stage.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. 2 is a block diagram of a differential amplifier according to the present invention. The voltage detector 100 which compares and amplifies a reference voltage Vref and a power supply voltage Vcc and controls the differential voltage is controlled by an output signal of the voltage detector. An operating voltage adjusting unit 101 for driving an amplifier and a differential amplifier 102 for differentially amplifying an input data signal from a bit line are provided.

3 is a detailed view of the voltage sensor used in the present invention, and includes a power supply voltage divider 200, a comparator 201, and a voltage complete layer 202.

The power supply voltage divider 200 includes a resistor Rl connected between a power supply voltage Vcc and a node N6, a resistor R2 connected in series between the node N6 and a ground voltage Vss, and The gate is composed of an NMOS transistor Q7 connected to a power supply voltage Vcc.

When the NMOS transistor Q7 is turned on, a current flows through the power voltage Vcc and the ground voltage Vss so that the resistor Rl and the resistor R2 are supplied to the power voltage divider 200. A potential corresponding to) is induced at the node N6.

According to the present invention, an input from a fuse or a bond pad may be connected instead of the power voltage divider 200.

The comparator 201 is connected between a power supply voltage Vcc and a node N7 and a PMOS transistor Q8 which is a pull-up driving stage whose operation is controlled by a differential amplifier control signal BSEP, and the node. PMOS transistors Q9 and Q10 which are connected between N7 and nodes N8 and NIO and whose gates are commonly connected to the node N10, and the nodes N8 and N10 and N11. Is connected between the NMOS transistors Q11 and Q12 receiving the data input and the node N11 and the ground voltage Vss, and its operation is controlled by the differential amplifier control signal .phi.SEN. An NMOS transistor Q13, which is a pull-down driving stage, is provided.

The comparison unit 201 is a differential amplifier for comparing the potential signal of the node N6 with the reference voltage Vref potential and amplifying the signal to the node N8.

In the case of low power supply voltage (VN6 Vref condition), the current flow in the NNOS transistor Q11 becomes smaller than the NMOS transistor Q12 so that the potential signal of the node N8 maintains the logic high state. In the case of a high power supply voltage (VN6 Vref condition), the current flow in the NMOS transistor Q11 becomes larger than the NMOS transistor Q12 so that the potential signal of the node N8 has a logic low state.

The voltage buffer unit 202 includes gates G1 and C2 connected in series between the node N8 and the output terminal det. The voltage buffer unit 202 receives a potential signal of the node N8 induced by the comparison unit 202. Inverter connection according to the load amount can be determined according to the load amount of the output signal det determined in the entire chip.

4 shows a circuit diagram of a differential amplifier according to a first embodiment of the present invention, wherein a PMOS transistor Q14 connected between a power supply voltage Vcc and a node Nl3 and whose gate is connected to a node Nl2, The NMOS transistor Q16 is connected between the node Nl2 and the ground voltage Vss and the driving voltage det is connected to the gate, and is connected between the node Nl2 and the node Nl3 and the driving voltage is applied to the gate. an operating voltage control unit 101 including a PMOS transistor Q15 connected to det),

PMOS transistors Q17 and Q18 which are connected between the node Nl3 and the nodes Nl4 and Nl6 and whose gates are commonly connected to the node Nl6, and the nodes Nl4 and Nl6 and the node. A channel is connected between Nl7 and NMOS transistors Q19 and Q20 that accept data input, and is connected between the node Nl7 and the ground voltage Vss, and its operation is controlled by the differential amplifier control signal .phi.SEN. And a differential amplifier 102 composed of an NMOS transistor Q21 that is a controlled pull-down driving stage.

In operation, the output signal det of the voltage sensor 100 commonly connected to the gates of the NMOS transistor Q16 and the PMOS transistor Q15 in a state where the potential difference between the input lines Vg3 and Vg4 is several tens of mV or more. Is applied, the conduction state of the NMOS transistor Q16 and the PMOS transistor Q15 is determined. Therefore, the potential of the node Nl2 is determined to operate the PMOS transistor Q14 connected to the node Nl3 and the power supply voltage Vcc.

Accordingly, the pull-up driving transistor Q14 supplies a current from the power supply voltage Vcc to the differential amplifier 202, and the pull-down driving transistor Q21 applies the differential amplifier control signal ΦSEN applied to its gate. ) Is turned on as the logic low state changes to the logic high state to discharge current from the differential amplifier 102 to the ground voltage Vss. The voltage signals generated at the nodes Nl4 and Nl6 may have mutually opposite magnitudes according to the magnitudes of the potential signals Vg3 and Vg4 supplied to the gates of the NMOS transistors Q19 and Q20, respectively. In fact, when the input potential signal Vg4 is larger than the input potential signal Vg3, the voltage signal generated at the node Nl4 has a voltage level greater than the voltage signal generated at the node Nl6. On the contrary, when the input potential signal Vg4 is smaller than the input potential signal Vg3, the voltage signal generated at the node Nl4 has a voltage level smaller than the voltage signal generated at the node Nl6. . The magnitude of the voltage signal generated at the node Nl4 and the voltage signal generated at the node Nl6 is proportional to the difference between the input data potential signals Vg3 and Vg4.

In other words, the difference between the input signals into the two input terminals Vg3 and Vg4 is amplified by the drain terminals of the NMOS transistors Q19 and Q20 and output to the node Nl4.

Therefore, the potential of the output node Nl3 of the operation voltage adjusting unit 101 can be appropriately adjusted according to the change of the power supply voltage.

That is, in the case of a high power supply voltage (for example, 6V), the MMOS transistor Q16 is turned off and the PMOS transistor Q15 is turned on because it has a low voltage output signal det. Thus, the potentials of the node Nl3 and the node Nl2 may be about 'Vcc − Vt' (diode structure) to lower the output swing when the differential amplifier 202 operates.

In the case of a low power supply voltage (for example, 3V and 3V), the output signal det of the voltage detector is kept high, so that the PMOS transistor Q15 is turned off and the NMOS transistor Q16 is turned off. Is turned on so that the node Nl2 maintains the ground voltage Vss, and the PMOS transistor Q14 is strongly turned on to supply the potential of the node Nl3 near the power supply voltage Vcc potential. The common mode input range (CMR) value at low power supply voltage can be improved.

The operating voltage adjusting unit 101 of the present invention can be used to adjust the operating voltage in configuring various types of amplifiers.

5 is a circuit diagram of a differential amplifier according to a second embodiment of the present invention, wherein a PMOS transistor Q22 connected between a power supply voltage Vcc and a node Nl9 and a gate connected to a node Nl8, and the node ( The NMOS transistor Q24 connected between the Nl8 and the ground voltage Vss and the driving voltage det is connected to the gate, and is connected between the node Nl8 and the node Nl9 and the driving voltage det on the gate. An operating voltage adjusting unit 101 including a PMOS transistor Q23 connected thereto;

NMOS transistors Q25 and Q26 connected between the nodes Nl9 and N20 and N21 and input data are respectively input to gates, and a cross latch structure between the nodes N20, N2l and N22. NMOS transistors Q29 and Q28, which are connected between the node N22 and the ground voltage Vss and are pull-down driving stages whose operation is controlled by a differential amplifier control signal ΦSEN. It is provided with a differential medium width portion (102).

Referring to the operation, the output signal det of the voltage sensor 100 commonly connected to the gates of the NMOS transistor Q24 and the PMOS transistor Q23 while the potential difference between the input lines Vg5 and Vg6 is several tens of mV or more. Is applied, the conduction state of the NMOS transistor Q24 and the PMOS transistor Q23 is determined. Therefore, the potential of the node Nl8 is determined to operate the PMOS transformer Q22 connected to the node Nl9 and the power supply voltage Vcc.

Accordingly, the pull-up driving transistor Q22 supplies a current from the power supply voltage Vcc to the differential amplifier 202, and the pull-down driving transistor Q29 applies the differential amplifier control signal? SEN applied to its gate. ) Is turned on as the logic low state changes to the logic high state to discharge current from the differential amplifier 102 to the ground voltage Vss. In addition, the voltage signals generated at the nodes N20 and N2l are opposite to each other according to the magnitudes of the potential signals Vg5 and Vg6 from the input lines supplied to the gates of the NMOS transistors Q25 and Q26, respectively. Will have In fact, when the input potential signal Vg6 is larger than the input potential signal Vg5, the voltage signal generated at the node N20 has a voltage level greater than the voltage signal generated at the node N21. . On the contrary, when the input potential signal Vg6 is smaller than the input potential signal Vg5, the voltage signal generated at the node N20 has a voltage level smaller than the voltage signal generated at the node N21. . The magnitude of the voltage signal generated at the node N20 and the voltage signal generated at the node N2l is proportional to the difference between the input data potential signals Vg5 and Vg6.

That is, the difference between the input signals into the two input terminals Vg5 and Vg6 is amplified by the source terminals of the NMOS transistors Q25 and Q26 and output to the nodes N20 and N2l.

Therefore, the potential of the output node N9 of the operating voltage adjusting unit 101 can be appropriately adjusted according to the change of the power supply voltage.

That is, in the case of a high power supply voltage (for example, 6V), since the output signal det of the voltage sensor has a bow, the NMOS transistor Q24 is turned off and the PMOS transistor Q23 is turned on. When turned on, the potentials of the node Nl9 and the node Nl8 are about 'Vcc-Vt' (diode structure), so that the output scan can be lowered when the differential amplifier 102 operates.

In the case of a low power supply voltage (eg, 3.3V), the output signal det of the voltage detector is kept high, so that the PMOS transistor Q23 is turned off and the NMOS transistor Q24 is turned off. On, the node Nl8 maintains the ground voltage Vss, and the PMOS transistor Q22 is strongly turned on to form a voltage near the potential of the node Nl9 near the power supply voltage Vcc potential. It is possible to improve the common mode input range CMR value, which is a problem at low power supply voltage.

When the differential amplifier of the present invention described above is implemented in the semiconductor device, the amount of current consumed by the differential amplifier can be adjusted according to the potential of the power supply voltage Vcc, thereby reducing noise generated from the power line inside the chip. There is an effect that can realize a stable operation.

Claims (5)

Power supply voltage detecting means 100 for detecting a change in power supply voltage, an operating voltage adjusting means 101 for outputting a stable operating voltage by an output from the power supply voltage detecting means 100 and the operating voltage adjusting means. An amplifying means 102 for receiving and operating a stable operating voltage output from the 101 as a bias voltage, and adjusting the operating residual pressure controlled by the power supply voltage detecting means 100 when the power supply voltage exceeds a reference value. The means 101 lowers the bias voltage applied to the amplifying means below the power supply voltage, and when the power supply voltage falls below the reference value, the operating voltage adjusting means 101 controlled by the power supply voltage sensing means 100. ) Makes the bias voltage applied to the amplifying means equal to the power supply voltage. The method of claim 1, wherein the power supply voltage detecting means 100 is divided by the voltage dividing means (200) which is controlled by the power supply voltage to divide the power supply voltage and outputs it, and the output potential from the voltage dividing means (200); Voltage comparator 201 for comparatively amplifying a predetermined reference voltage, and slower means for buffering the comparative amplified output signal from the voltage comparator 201 and outputting an output signal for detecting a change in the power supply voltage. (202), characterized in that the differential amplifier. 3. A differential amplifier as set forth in claim 2, wherein said slow means (202) is comprised of an inverter. The differential amplifier according to claim 1, wherein the operating voltage adjusting means (101) adjusts a common mode range of the amplifying means according to a change in the power supply voltage. The first PMOS transistor (Q22) of claim 2, wherein the operating voltage adjusting means (101) is connected between the power supply voltage and the first node (N19) and whose gate is connected to the second node (Nl8). An NMOS transistor Q24 connected between a second node Nl8 and a ground voltage Vss, to which an output signal of the buffer means is applied, and between the second node Nl8 and the first node Nl9. And a second PMOS transistor (Q23) connected to the gate and to which an output signal of the buffer means is applied.