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JPS6481068A - Simulation circuit for digital signal processing circuit - Google Patents

Simulation circuit for digital signal processing circuit

Info

Publication number
JPS6481068A
JPS6481068A JP23951287A JP23951287A JPS6481068A JP S6481068 A JPS6481068 A JP S6481068A JP 23951287 A JP23951287 A JP 23951287A JP 23951287 A JP23951287 A JP 23951287A JP S6481068 A JPS6481068 A JP S6481068A
Authority
JP
Japan
Prior art keywords
data
circuit
test data
output
byte
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23951287A
Other languages
Japanese (ja)
Inventor
Ikuo Hanajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23951287A priority Critical patent/JPS6481068A/en
Publication of JPS6481068A publication Critical patent/JPS6481068A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

PURPOSE:To easily set, change and analyze the test data by storing this data into a 1st memory device for each block and at the same time storing the processing result of the test data into a 2nd memory device for each block. CONSTITUTION:The test data for simulation is written into each address of a ROM 2 every byte and the test data on the ROM 2 is successively outputted every byte for the address designated by the output of a counter 1 for basic clocks CLK. The output test data is converted into the serial data SD by a parallel/serial converter 3 and processed by a digital signal processing circuit 4. Then the output data SDD of the circuit 4 is converted into the parallel data by a serial/parallel converter 6 and stored every byte in a RAM 7 of the address designated by the output of a counter 5 which counts the clock signals CP2 outputted from the circuit 4.
JP23951287A 1987-09-22 1987-09-22 Simulation circuit for digital signal processing circuit Pending JPS6481068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23951287A JPS6481068A (en) 1987-09-22 1987-09-22 Simulation circuit for digital signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23951287A JPS6481068A (en) 1987-09-22 1987-09-22 Simulation circuit for digital signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6481068A true JPS6481068A (en) 1989-03-27

Family

ID=17045897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23951287A Pending JPS6481068A (en) 1987-09-22 1987-09-22 Simulation circuit for digital signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6481068A (en)

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