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JPS57191750A - Buffer memory device - Google Patents

Buffer memory device

Info

Publication number
JPS57191750A
JPS57191750A JP7693681A JP7693681A JPS57191750A JP S57191750 A JPS57191750 A JP S57191750A JP 7693681 A JP7693681 A JP 7693681A JP 7693681 A JP7693681 A JP 7693681A JP S57191750 A JPS57191750 A JP S57191750A
Authority
JP
Japan
Prior art keywords
signal
ffs
bits
stages
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7693681A
Other languages
Japanese (ja)
Inventor
Tadao Sasaki
Motoaki Bito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7693681A priority Critical patent/JPS57191750A/en
Publication of JPS57191750A publication Critical patent/JPS57191750A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To convert a clock frequency with the least number of bytes, by dividing a data signal to every optional number and providing a memory with a specific number of stages to convert the frequency. CONSTITUTION:A data signal is divided to every optional number, and a memory with a number of stages which is larger than a value obtained by adding 1 to the value, which is obtained by multiplying the proportion of the difference between periods of the first and the second clocks to the period of the first clock by the optional number, is provided. For example, upper 4 bits and lower 4 bits of data of 1 byte=8 bits are inputted to input terminals 1 and 2 respectively, and these signals are supplied to memories 3 and 4 and memories 5 and 6 with a prescribed number of stages, and output signals are transmitted to output terminals 7 and 8 respectively. Next, the start of data in a detected transmission signal is inputted to an input terminal 10, and this signal is supplied to an FF 11, and the output signal is supplied to FFs 12-14. Thus, the clock frequency is converted through FFs 20 and 21 and FFs 22-24.
JP7693681A 1981-05-21 1981-05-21 Buffer memory device Pending JPS57191750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7693681A JPS57191750A (en) 1981-05-21 1981-05-21 Buffer memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7693681A JPS57191750A (en) 1981-05-21 1981-05-21 Buffer memory device

Publications (1)

Publication Number Publication Date
JPS57191750A true JPS57191750A (en) 1982-11-25

Family

ID=13619608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7693681A Pending JPS57191750A (en) 1981-05-21 1981-05-21 Buffer memory device

Country Status (1)

Country Link
JP (1) JPS57191750A (en)

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