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JPS6490611A - Waveform generator - Google Patents

Waveform generator

Info

Publication number
JPS6490611A
JPS6490611A JP24731187A JP24731187A JPS6490611A JP S6490611 A JPS6490611 A JP S6490611A JP 24731187 A JP24731187 A JP 24731187A JP 24731187 A JP24731187 A JP 24731187A JP S6490611 A JPS6490611 A JP S6490611A
Authority
JP
Japan
Prior art keywords
adder
output
multiplexer
register
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24731187A
Other languages
Japanese (ja)
Inventor
Akira Ichinose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP24731187A priority Critical patent/JPS6490611A/en
Publication of JPS6490611A publication Critical patent/JPS6490611A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a desired output frequency setting resolution by optionally setting an output period consequtively accumulated by an adder in response to the operation clock frequency. CONSTITUTION:A step signal is supplied to a 1st register 6 to store an address interval data corresponding to the output frequency. The output of the register 6 is added to the output of a multiplexer 10 by a 1st adder 7. The sum 11 is supplied to an adder 9 and a terminal B of the multiplexer 10 via a 2nd register 8. The adder 9 adds a '2' complement inverse T which is a reciprocal of the frequency setting resolution to the output of the adder 7 and the sum is fed to terminals A, S of the multiplexer 10. One of the signals from the terminals A, B is selected by using a signal from the terminal S in the multiplexer 10 and outputted as an integration value of the adder 7. The output of the multiplexer 10 is fed to the adder 7 and the register 11. The registers 8, 11 store the signal and initialized by the inverse of RST, and the result is outputted synchronously with the clock CLK, then the output of the multiplexer 10 has a prescribed resolution.
JP24731187A 1987-09-30 1987-09-30 Waveform generator Pending JPS6490611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24731187A JPS6490611A (en) 1987-09-30 1987-09-30 Waveform generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24731187A JPS6490611A (en) 1987-09-30 1987-09-30 Waveform generator

Publications (1)

Publication Number Publication Date
JPS6490611A true JPS6490611A (en) 1989-04-07

Family

ID=17161515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24731187A Pending JPS6490611A (en) 1987-09-30 1987-09-30 Waveform generator

Country Status (1)

Country Link
JP (1) JPS6490611A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003082925A (en) * 2001-06-22 2003-03-19 Mitsuboshi Belting Ltd Support member of slider and support structure of slider using it
JP2007189506A (en) * 2006-01-13 2007-07-26 Yokogawa Electric Corp Dds signal generation apparatus
JP2022159932A (en) * 2021-04-05 2022-10-18 興治郎 川井 direct digital synthesizer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003082925A (en) * 2001-06-22 2003-03-19 Mitsuboshi Belting Ltd Support member of slider and support structure of slider using it
JP2007189506A (en) * 2006-01-13 2007-07-26 Yokogawa Electric Corp Dds signal generation apparatus
JP2022159932A (en) * 2021-04-05 2022-10-18 興治郎 川井 direct digital synthesizer

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