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JPS5531335A - Pulse addition system - Google Patents

Pulse addition system

Info

Publication number
JPS5531335A
JPS5531335A JP10456878A JP10456878A JPS5531335A JP S5531335 A JPS5531335 A JP S5531335A JP 10456878 A JP10456878 A JP 10456878A JP 10456878 A JP10456878 A JP 10456878A JP S5531335 A JPS5531335 A JP S5531335A
Authority
JP
Japan
Prior art keywords
output
parallel
pulse input
signal
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10456878A
Other languages
Japanese (ja)
Inventor
Kazunori Omura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10456878A priority Critical patent/JPS5531335A/en
Publication of JPS5531335A publication Critical patent/JPS5531335A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain the bit parallel output by supplying once the pulse input of over 2 into the memory and then forming these parallel signals into the bit serial output. CONSTITUTION:The rise is detected at waveform shaping part 12 for the pulse input given from input terminals 11-1-11-4, and corresponding pluse output SV1- SV4 are supplied to the corresponding register within memory 13. These pluse output are then read out every fixed time, and the signals PI1-PI4 are supplied to P/S conversion part 14 in parallel to be delivered in the form of bit serial signal Sout. This signal is then applied to counter 15 and also delivered through terminal 19. Counter 15 counts signal Sout to deliver it every fixed time in the form of the n-bit parallel signal. This system can be used effectively to the addition of the random pulse input for plural channels.
JP10456878A 1978-08-28 1978-08-28 Pulse addition system Pending JPS5531335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10456878A JPS5531335A (en) 1978-08-28 1978-08-28 Pulse addition system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10456878A JPS5531335A (en) 1978-08-28 1978-08-28 Pulse addition system

Publications (1)

Publication Number Publication Date
JPS5531335A true JPS5531335A (en) 1980-03-05

Family

ID=14384046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10456878A Pending JPS5531335A (en) 1978-08-28 1978-08-28 Pulse addition system

Country Status (1)

Country Link
JP (1) JPS5531335A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5751042A (en) * 1980-09-10 1982-03-25 Kubota Ltd 120(degrees) crankshaft for internal-combustion engine
JPS5860021U (en) * 1981-10-19 1983-04-22 日野自動車株式会社 6 crank pins 12 balance crankshaft
JPH0298214A (en) * 1988-10-05 1990-04-10 Takahata Denshi:Kk Multi-input count display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5751042A (en) * 1980-09-10 1982-03-25 Kubota Ltd 120(degrees) crankshaft for internal-combustion engine
JPS5860021U (en) * 1981-10-19 1983-04-22 日野自動車株式会社 6 crank pins 12 balance crankshaft
JPS6330834Y2 (en) * 1981-10-19 1988-08-17
JPH0298214A (en) * 1988-10-05 1990-04-10 Takahata Denshi:Kk Multi-input count display device

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