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JPS6435633A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS6435633A
JPS6435633A JP19000687A JP19000687A JPS6435633A JP S6435633 A JPS6435633 A JP S6435633A JP 19000687 A JP19000687 A JP 19000687A JP 19000687 A JP19000687 A JP 19000687A JP S6435633 A JPS6435633 A JP S6435633A
Authority
JP
Japan
Prior art keywords
interruption
level
bpu
interruption level
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19000687A
Other languages
Japanese (ja)
Inventor
Sunao Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19000687A priority Critical patent/JPS6435633A/en
Publication of JPS6435633A publication Critical patent/JPS6435633A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To switch an interruption level by a program control, by providing a storage means of the interruption level in a controller for requesting an interruption, and outputting an interruption to an interruption level designated by information of a stored interruption level. CONSTITUTION:A processor BPU 1 and a controller IOA 2 are connected by a common bus 10. The device IOA 2 requests an interruption to the device BPU 1 by using plural interruption levels INT 0-n being a part of the common bus 10. An interruption control circuit is provided with an interruption level register INT LVL REG 4 for storing the interruption level by a program control, instead of a conventional switch and a pull-up resistance. An output of the register REG 4 becomes an input of NAND gates 30-32, respectively. The interruption level designated by the program control passes through the common bus 10 from the device BPU 1 and stored in the register REG 4.
JP19000687A 1987-07-31 1987-07-31 Interruption control system Pending JPS6435633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19000687A JPS6435633A (en) 1987-07-31 1987-07-31 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19000687A JPS6435633A (en) 1987-07-31 1987-07-31 Interruption control system

Publications (1)

Publication Number Publication Date
JPS6435633A true JPS6435633A (en) 1989-02-06

Family

ID=16250810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19000687A Pending JPS6435633A (en) 1987-07-31 1987-07-31 Interruption control system

Country Status (1)

Country Link
JP (1) JPS6435633A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0390936A (en) * 1989-09-01 1991-04-16 Nec Corp Conversion system for hardware interruption level

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57204950A (en) * 1981-06-11 1982-12-15 Fujitsu Ltd Interruption controlling system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57204950A (en) * 1981-06-11 1982-12-15 Fujitsu Ltd Interruption controlling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0390936A (en) * 1989-09-01 1991-04-16 Nec Corp Conversion system for hardware interruption level

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