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JPS5741727A - Interruption controlling sysyem - Google Patents

Interruption controlling sysyem

Info

Publication number
JPS5741727A
JPS5741727A JP11596580A JP11596580A JPS5741727A JP S5741727 A JPS5741727 A JP S5741727A JP 11596580 A JP11596580 A JP 11596580A JP 11596580 A JP11596580 A JP 11596580A JP S5741727 A JPS5741727 A JP S5741727A
Authority
JP
Japan
Prior art keywords
interruption
module
processor
level
noncorrespondence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11596580A
Other languages
Japanese (ja)
Other versions
JPS6242306B2 (en
Inventor
Toshitaka Hara
Makoto Yamanouchi
Satoshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11596580A priority Critical patent/JPS5741727A/en
Publication of JPS5741727A publication Critical patent/JPS5741727A/en
Publication of JPS6242306B2 publication Critical patent/JPS6242306B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To decreae the number of interruption signal lines, by feeding the interruption information to the address/data line of a common bus from a control module of a requester input/output device and deciding the own correspondence or noncorrespondence through each processor module. CONSTITUTION:A multiprocessor consists of plural processor modules 10 plus input/output control modules 11 and a common bus 12. The interruption information including the number of the processor module to be interrupted plus the interruption level of the module and fed to an address/data line 44 of the bus 12 from the module 11 receives an interruption process according to the interruption level and after deciding the correspondence or noncorrespondence to the own module number through a processor number decoder 30 and an interruption level decoder 31, etc. provided in each module 10. In such way, the number of interruption signal lines can be decreased with increase of the number of interruption levels.
JP11596580A 1980-08-25 1980-08-25 Interruption controlling sysyem Granted JPS5741727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11596580A JPS5741727A (en) 1980-08-25 1980-08-25 Interruption controlling sysyem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11596580A JPS5741727A (en) 1980-08-25 1980-08-25 Interruption controlling sysyem

Publications (2)

Publication Number Publication Date
JPS5741727A true JPS5741727A (en) 1982-03-09
JPS6242306B2 JPS6242306B2 (en) 1987-09-08

Family

ID=14675515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11596580A Granted JPS5741727A (en) 1980-08-25 1980-08-25 Interruption controlling sysyem

Country Status (1)

Country Link
JP (1) JPS5741727A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159172A (en) * 1982-03-17 1983-09-21 Fujitsu Ltd Multiplex processor
JPS60172094A (en) * 1984-02-17 1985-09-05 株式会社大真空 Display information exchanger for electrostatic type display unit
JPS6145305A (en) * 1984-08-10 1986-03-05 Koike Sanso Kogyo Co Ltd Numerical controller
JPS62147045U (en) * 1986-03-10 1987-09-17
JPS634363A (en) * 1986-06-25 1988-01-09 Matsushita Electric Ind Co Ltd Multi-cpu device
EP0263886A1 (en) * 1986-04-15 1988-04-20 Fanuc Ltd. Interrupt control method in a multiprocessor system
EP0316138A2 (en) * 1987-11-11 1989-05-17 Fujitsu Limited Grouping device for interrupt controller
EP0324144A2 (en) * 1988-01-11 1989-07-19 Siemens Aktiengesellschaft Data-processing system with arrangement for identifying interrupt supplying units

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3041863U (en) * 1997-03-26 1997-10-03 株式会社イシバシヤ Auxiliary antenna

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155149A (en) * 1974-06-03 1975-12-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155149A (en) * 1974-06-03 1975-12-15

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159172A (en) * 1982-03-17 1983-09-21 Fujitsu Ltd Multiplex processor
JPS6330659B2 (en) * 1982-03-17 1988-06-20 Fujitsu Ltd
JPS60172094A (en) * 1984-02-17 1985-09-05 株式会社大真空 Display information exchanger for electrostatic type display unit
JPH0369116B2 (en) * 1984-02-17 1991-10-30 Daishinku Kk
JPS6145305A (en) * 1984-08-10 1986-03-05 Koike Sanso Kogyo Co Ltd Numerical controller
JPS62147045U (en) * 1986-03-10 1987-09-17
EP0263886A1 (en) * 1986-04-15 1988-04-20 Fanuc Ltd. Interrupt control method in a multiprocessor system
JPS634363A (en) * 1986-06-25 1988-01-09 Matsushita Electric Ind Co Ltd Multi-cpu device
EP0316138A2 (en) * 1987-11-11 1989-05-17 Fujitsu Limited Grouping device for interrupt controller
US5146595A (en) * 1987-11-11 1992-09-08 Fujitsu Limited Grouping device for forming input signals into groups
EP0324144A2 (en) * 1988-01-11 1989-07-19 Siemens Aktiengesellschaft Data-processing system with arrangement for identifying interrupt supplying units

Also Published As

Publication number Publication date
JPS6242306B2 (en) 1987-09-08

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