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JPS57204950A - Interruption controlling system - Google Patents

Interruption controlling system

Info

Publication number
JPS57204950A
JPS57204950A JP8985681A JP8985681A JPS57204950A JP S57204950 A JPS57204950 A JP S57204950A JP 8985681 A JP8985681 A JP 8985681A JP 8985681 A JP8985681 A JP 8985681A JP S57204950 A JPS57204950 A JP S57204950A
Authority
JP
Japan
Prior art keywords
interrupt
gates
terminals
imr
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8985681A
Other languages
Japanese (ja)
Inventor
Tetsuya Hagiwara
Toshio Shimada
Tetsuhiko Ifuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8985681A priority Critical patent/JPS57204950A/en
Publication of JPS57204950A publication Critical patent/JPS57204950A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent overrun and etc. to perform a rational interruption processing, by changing the interrupt level of each input/output device in accordance with contents of an interrupt mask register. CONSTITUTION:Interrupt request signal lines Li and Lj are connected to interrupt terminals T1-Tn through switching gates consisting of OR gates G1-Gn, which are provided in correspondence of 1:1 to interrupt terminals T1-Tn of a microprocessor MPU, and plural AND gates A11-A1j, A21-A2k, A31-A3l, - belonging to gates G1-Gn. The other inputs of gates A11-A1j, A21-A2k, A31-A3l, - are given from interrupt mask registers iMR to determine one of interrupt terminals T1-Tn to which each of interrupt request signal lines Li and Lj should be connected in the current stage. Contents of registers iMR are determined by current run level signals iMR1-iMRn, which indicate priority levels, from the processor MPU.
JP8985681A 1981-06-11 1981-06-11 Interruption controlling system Pending JPS57204950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8985681A JPS57204950A (en) 1981-06-11 1981-06-11 Interruption controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8985681A JPS57204950A (en) 1981-06-11 1981-06-11 Interruption controlling system

Publications (1)

Publication Number Publication Date
JPS57204950A true JPS57204950A (en) 1982-12-15

Family

ID=13982425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8985681A Pending JPS57204950A (en) 1981-06-11 1981-06-11 Interruption controlling system

Country Status (1)

Country Link
JP (1) JPS57204950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435633A (en) * 1987-07-31 1989-02-06 Hitachi Ltd Interruption control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5075750A (en) * 1973-11-07 1975-06-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5075750A (en) * 1973-11-07 1975-06-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435633A (en) * 1987-07-31 1989-02-06 Hitachi Ltd Interruption control system

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