[go: up one dir, main page]

JPS56108125A - Access device - Google Patents

Access device

Info

Publication number
JPS56108125A
JPS56108125A JP1060480A JP1060480A JPS56108125A JP S56108125 A JPS56108125 A JP S56108125A JP 1060480 A JP1060480 A JP 1060480A JP 1060480 A JP1060480 A JP 1060480A JP S56108125 A JPS56108125 A JP S56108125A
Authority
JP
Japan
Prior art keywords
signal
reply
reply signal
cpu1
insignificant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1060480A
Other languages
Japanese (ja)
Inventor
Hisao Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1060480A priority Critical patent/JPS56108125A/en
Publication of JPS56108125A publication Critical patent/JPS56108125A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To avoid the take-in of the reply signal of the precedent step at the CPU, by delivering the request signal of the next step onto the request signal line in case the reply signal remains on the reply signal line. CONSTITUTION:The gate circuit 4 is controlled by the logic of the reply signal on the signal line 14 and permits the passing of the request signal sent from the CPU1 only when the reply signal is insignificant. Accordingly, the address signal is delivered from the CPU1 when the reply signal is insignificant, and then the request signal is delivered. When an access is given from the CPU1 in case a delay is given to the change of the reply signal of the precedent step to the insignificant side, the request signal is blocked by the gate circuit 4 during the time when the reply signal remains.
JP1060480A 1980-01-29 1980-01-29 Access device Pending JPS56108125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1060480A JPS56108125A (en) 1980-01-29 1980-01-29 Access device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1060480A JPS56108125A (en) 1980-01-29 1980-01-29 Access device

Publications (1)

Publication Number Publication Date
JPS56108125A true JPS56108125A (en) 1981-08-27

Family

ID=11754843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1060480A Pending JPS56108125A (en) 1980-01-29 1980-01-29 Access device

Country Status (1)

Country Link
JP (1) JPS56108125A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281047A (en) * 1986-05-30 1987-12-05 Meisei Electric Co Ltd Output control system for data
JPH01230158A (en) * 1987-08-19 1989-09-13 Hitachi Ltd Data transfer method and device
US7178924B2 (en) 2003-08-01 2007-02-20 Funai Electric Co., Ltd. Projector having a lens cap and a string holding member attached to the lens cap

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281047A (en) * 1986-05-30 1987-12-05 Meisei Electric Co Ltd Output control system for data
JPH01230158A (en) * 1987-08-19 1989-09-13 Hitachi Ltd Data transfer method and device
US7178924B2 (en) 2003-08-01 2007-02-20 Funai Electric Co., Ltd. Projector having a lens cap and a string holding member attached to the lens cap

Similar Documents

Publication Publication Date Title
JPS56140452A (en) Memory protection system
JPS56130884A (en) Semiconductor memory device
JPS56108125A (en) Access device
JPS5259537A (en) Data processor
JPS5699531A (en) Control method for bus usufructuary right of direct memory access channel
JPS526032A (en) Main storage control unit
JPS5476027A (en) Dynamic priority circuit
JPS57109026A (en) Bus controlling system
JPS57197631A (en) Method of controlling information processing system
JPS5723132A (en) Acquisition system for priority right of interruption
JPS6491235A (en) Control system for counter circuit
JPS56108146A (en) Clocking device
JPS5515503A (en) Allocation control system for interruption request line
JPS5329480A (en) Program controller
JPS54127248A (en) Arithmetic controller
JPS55153450A (en) Control system for line polarity
JPS51144137A (en) Input/output data control unit
JPS52119039A (en) Input output controlling device
JPS5731022A (en) Bus controller
JPS57176442A (en) Information processing system
JPS5723159A (en) Data processing system
JPS5798029A (en) Bus priority processing
JPS5530756A (en) Small size electronic calculator
JPS55108068A (en) Memory control system
JPS5660955A (en) Interruption priority determination system