JPS63204766A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63204766A JPS63204766A JP62038948A JP3894887A JPS63204766A JP S63204766 A JPS63204766 A JP S63204766A JP 62038948 A JP62038948 A JP 62038948A JP 3894887 A JP3894887 A JP 3894887A JP S63204766 A JPS63204766 A JP S63204766A
- Authority
- JP
- Japan
- Prior art keywords
- channel region
- band width
- forbidden band
- regions
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
Abstract
Description
【発明の詳細な説明】 〔概要〕 ＭＯＳＦＥＴの改良である。[Detailed description of the invention] 〔overview〕 This is an improvement of MOSFET.
短チャンネル効果の発生を防止するため、ＭＯＳ ＦＥ
Ｔのチャンネル領域のみを、その他の領域より禁制帯幅
の大きな半導体で構成したものである。To prevent the occurrence of short channel effects, MOS FE
Only the channel region of T is made of a semiconductor having a larger forbidden band width than the other regions.
本発明はＭＯＳＦＥＴの改良に関する。特に、短チャン
ネル効果の発生を防止する改良に関する。The present invention relates to improvements in MOSFETs. In particular, it relates to improvements that prevent the occurrence of short channel effects.
〔従来の技術と発明が解決しようとする問題点〕ＭＯ３
ＦＥＴにおいては、高速化の要請に応えてチャンネル長
を短くする必要があるが、例えば、シリコンＭＯ３ＦＥ
Ｔの場合、チャンネル長が０．８ＪＪ、ｒｘ以下になる
と、いわゆる短チャンネル効果が発生して、しきい値電
圧が変動したり。[Problems to be solved by conventional technology and invention] MO3
In FETs, it is necessary to shorten the channel length in response to the demand for higher speeds, but for example, silicon MO3FE
In the case of T, when the channel length is less than 0.8 JJ, rx, a so-called short channel effect occurs, and the threshold voltage fluctuates.
ソース・ドレイン間耐圧が低下したりする欠点が避は難
い。It is difficult to avoid the drawback that the breakdown voltage between the source and drain decreases.
本発明の目的は、この欠点を解消することにあり、チャ
ンネル長を短くし動作速度を向上しながら、短チャンネ
ル効果の発生を防＋ＦＬうる電界効果型半導体装置を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback, and to provide a field effect semiconductor device that can prevent short channel effects from occurring while shortening the channel length and improving operating speed.
上記の目的を達成するために本発明が採った手段は、チ
ャンネル領域のみを他の領域より禁制帯幅の大きな半導
体をもって構成しておくことにある。The means taken by the present invention to achieve the above object is to configure only the channel region with a semiconductor having a larger forbidden band width than other regions.
シリコンよりなるＭＯＳＦＥＴの場合は、チャンネル領
域のみを炭化シリコンとしておけばよい、炭化シリコン
の禁制帯幅は２〜３ｅＶであり、シリコンの禁制帯幅（
１，１ｅＶ）より十分に大きいからである。In the case of a MOSFET made of silicon, only the channel region needs to be made of silicon carbide. The forbidden band width of silicon carbide is 2 to 3 eV, and the forbidden band width of silicon (
1.1 eV).
ガリウムヒ素よりなるＭＯＳＦＥＴの場合は、チャンネ
ル領域のみをガリウムヒ素リンまたはアルミニウムガリ
ウムヒ素リンとしておけばよい。In the case of a MOSFET made of gallium arsenide, only the channel region may be made of gallium arsenide phosphide or aluminum gallium arsenide phosphide.
ガリウムヒ素リンまたはアルミニウムガリウムヒ素リン
の禁制帯幅はガリウムヒ素の禁制帯幅より大きいからで
ある。This is because the forbidden band width of gallium arsenide phosphide or aluminum gallium arsenide phosphide is larger than that of gallium arsenide.
短チヤンネル効果発生の理由は、従来のＭＯＳＦＥＴの
場合、バンドダイヤグラムが第２図に示すようであり、
チャンネル領域でバイポーラトランジスタが成立するた
めである。一方、本発明のＭＯＳＦＥＴの場合のバンド
ダイヤグラムは第３図に示すようになっており、チャン
ネル領域でバイポーラトランジスタが成立しにくいので
、短チャンネル効果は発生しにくい、実験の結果によれ
ば、シリコンＭＯ３ＦＥＴの場合、チャンネル長を０．
４ル購にしても、短チャンネル効果が発生しないことが
確認された。The reason for the short channel effect is that in the case of conventional MOSFETs, the band diagram is as shown in Figure 2.
This is because a bipolar transistor is established in the channel region. On the other hand, the band diagram for the MOSFET of the present invention is as shown in FIG. In the case of MO3FET, the channel length is set to 0.
It was confirmed that the short channel effect did not occur even when the amount of 4 rupees was purchased.
以下１図面を参照しつ覧１本発明の一実施例に係る半導
体装置についてさらに説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be further described below with reference to the drawings.
第４図参照
Ｐ型シリコン基板ｌ上に、ＬＯＣＯ３法を使用して、厚
い絶縁膜２を形成する。Referring to FIG. 4, a thick insulating film 2 is formed on a P-type silicon substrate l using the LOCO3 method.
次に、リソグラフィー法を使用してチャンネル領域に幅
０．４Ｂｍ深さ０．２ｗ層の開口３を形成する。４はレ
ジストマスクである。Next, an opening 3 having a width of 0.4 Bm and a depth of 0.2 W layer is formed in the channel region using a lithography method. 4 is a resist mask.
第５図参照 プロパンとモノシランとの混合ガスを供給し。See Figure 5 Supply a mixed gas of propane and monosilane.
これらを ９００−１．１００℃において反応させて開
口３内に炭化シリコンＮＩ５を形成する。These are reacted at 900-1.100°C to form silicon carbide NI5 in the opening 3.
つＣいて、ＣＶＤ法を使用して、二酸化シリコン層６を
薄く形成する。この二酸化シリコン層６がゲート絶縁膜
である。Then, a thin silicon dioxide layer 6 is formed using the CVD method. This silicon dioxide layer 6 is a gate insulating film.
多結晶シリコン層を形成した後、これをゲート領域以外
から除去してゲート電極７を形成する。After forming the polycrystalline silicon layer, it is removed from areas other than the gate region to form gate electrode 7.
ゲート電極７をマスクとして、ｎ型不純物をイオン注入
してソース８とドレイン９とを形成する。A source 8 and a drain 9 are formed by ion-implanting n-type impurities using the gate electrode 7 as a mask.
第１図参照
ゲート電極７を絶縁１１１１０をもってカバーし、ソー
ス８とドレイン９との上に電極コンタクト窓を形成した
後、アルミニウム膜を堆積してこれをバターニングして
ソース電極１１とドレイン電極１２とを形成する。Refer to FIG. 1. After covering the gate electrode 7 with an insulator 11110 and forming an electrode contact window on the source 8 and drain 9, an aluminum film is deposited and patterned to form a source electrode 11 and a drain electrode 12. to form.
以上の工程をもって製造したＭＯＳＦＥＴは、そのチャ
ンネル領域のみ禁制帯幅が大きくしであるので、ゲート
長が０．４４ｍと短いにもか−わらず短チャンネル効果
は発生しない。Since the MOSFET manufactured by the above process has a large forbidden band width only in its channel region, no short channel effect occurs even though the gate length is as short as 0.44 m.
以上説明せるとおり、本発明に係る電界効果型半導体装
置は、そのチャンネル領域のみの禁制帯幅がその他の領
域の禁制帯幅より大きくされてなるので、ゲー１１１Ｌ
が短く動作速度が向上しているにもか−わらず短チャン
ネル効果は発生せず、しきい値電圧が変動したり、ソー
ス・ドレイン間耐圧が低下したりすることはない。As explained above, in the field effect semiconductor device according to the present invention, the forbidden band width of only the channel region is made larger than the forbidden band width of the other regions.
Despite the short channel length and improved operating speed, no short channel effect occurs, and the threshold voltage does not fluctuate or the source-drain breakdown voltage decreases.
第１図は、本発明の一実施例に係るＭＯＳＦＥＴの断面
図である。
第２図、第３図は、本発明の詳細な説明するバンドダイ
ヤグラムである。
第４図、第５図は、本発明の一実施例に係る電界効果型
半導体装置の主要製造工程図である。
１１１−１１ｐ型シリコン基板、
２・・・厚い絶縁膜。
３・−・チャンネル領域の開口。
４・・・レジストマスク、
５・・拳本発明の要旨に係る炭化シリコン層のチャンネ
ル領域、
６・拳・ゲート絶縁膜、
７・寺拳ゲート電極、
８・・・ソース、
９＠・・ドレイン、
１０・・・絶縁膜、
１１Φ・−ソース電極。
１２・・・ドレイン電極。
工程図
第 ５ 図
本発明
第１図FIG. 1 is a sectional view of a MOSFET according to an embodiment of the present invention. 2 and 3 are band diagrams illustrating the invention in detail. 4 and 5 are main manufacturing process diagrams of a field effect semiconductor device according to an embodiment of the present invention. 111-11p type silicon substrate, 2...thick insulating film. 3.--Opening of channel region. 4...Resist mask, 5...Fist, channel region of silicon carbide layer according to the gist of the present invention, 6.Fist/gate insulating film, 7.Teraken gate electrode, 8...Source, 9@...Drain , 10... Insulating film, 11Φ·-source electrode. 12...Drain electrode. Process diagram Figure 5 Present invention Figure 1
Claims (1)
り大きくされてなる ことを特徴とする電界効果型半導体装置。[Scope of Claims] A field effect semiconductor device characterized in that the forbidden band width of a channel region is made larger than the forbidden band width of other regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038948A JPS63204766A (en) | 1987-02-20 | 1987-02-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038948A JPS63204766A (en) | 1987-02-20 | 1987-02-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63204766A true JPS63204766A (en) | 1988-08-24 |
Family
ID=12539427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62038948A Pending JPS63204766A (en) | 1987-02-20 | 1987-02-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63204766A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006012626A3 (en) * | 2004-07-28 | 2008-04-17 | Micron Technology Inc | Memory devices, transistors, memory cells, and methods of making same |
-
1987
- 1987-02-20 JP JP62038948A patent/JPS63204766A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006012626A3 (en) * | 2004-07-28 | 2008-04-17 | Micron Technology Inc | Memory devices, transistors, memory cells, and methods of making same |
| US7598134B2 (en) | 2004-07-28 | 2009-10-06 | Micron Technology, Inc. | Memory device forming methods |
| US8080837B2 (en) | 2004-07-28 | 2011-12-20 | Micron Technology, Inc. | Memory devices, transistors, and memory cells |
| US8415722B2 (en) | 2004-07-28 | 2013-04-09 | Micron Technology, Inc. | Memory devices and memory cells |
| US8470666B2 (en) | 2004-07-28 | 2013-06-25 | Micron Technology, Inc. | Methods of making random access memory devices, transistors, and memory cells |
| US8703566B2 (en) | 2004-07-28 | 2014-04-22 | Micron Technology, Inc. | Transistors comprising a SiC-containing channel |
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