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KR970054387A - Most transistor manufacturing method - Google Patents

Most transistor manufacturing method Download PDF

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Publication number
KR970054387A
KR970054387A KR1019950055943A KR19950055943A KR970054387A KR 970054387 A KR970054387 A KR 970054387A KR 1019950055943 A KR1019950055943 A KR 1019950055943A KR 19950055943 A KR19950055943 A KR 19950055943A KR 970054387 A KR970054387 A KR 970054387A
Authority
KR
South Korea
Prior art keywords
forming
film
ion implantation
semiconductor substrate
concentration impurity
Prior art date
Application number
KR1019950055943A
Other languages
Korean (ko)
Inventor
김천수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950055943A priority Critical patent/KR970054387A/en
Publication of KR970054387A publication Critical patent/KR970054387A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 기판의 채널 부위에 선택적으로 채널 이온주입을 실시하는 단계; 상기 반도체 기판 상에 게이트 산화막 및 게이트 전극용 폴리실리콘막을 형성하는 단계; 저농도 불순물 이온주입을 통해 노출된 반도체 기판에 저농도 불순물 영역을 형성하는 단계; 질소(N2) 이온주입을 실시하여 이후의 열공정에 의해 게이트 산화막이 질화되도록 하는 단계; 상기 폴리실리콘막 측벽에 절연막 스페이서를 형성하는 단계; 고농도 불순물 이온주입을 통해 노출된 반도체 기판에 소오스/드레인 접합을 형성하는 단계; 선택적 증착으로 실리콘막을 형성하는 단계; 및 상기 실리콘막 상에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 하는 모스트랜지스터(MOSFET) 제조 방법에 관한 것으로, 본 발명은 선택적 채널 이온주입을 통해 접합 캐패시턴스를 감소시키고, 질소 이온주입을 통해 게이트 산화막의 신뢰성을 향상시키며, 선택적 실리콘막 증착에 의해 얕은 접합 문제점을 해결하여 서브-쿼터 미크론(sub-quarter micron) MOSFET의 특성을 향상시킨다.The present invention comprises the steps of selectively performing channel ion implantation in the channel portion of the semiconductor substrate; Forming a gate oxide film and a polysilicon film for a gate electrode on the semiconductor substrate; Forming a low concentration impurity region in a semiconductor substrate exposed through low concentration impurity ion implantation; Performing nitrogen (N 2 ) ion implantation so that the gate oxide film is nitrided by a subsequent thermal process; Forming insulating film spacers on sidewalls of the polysilicon film; Forming a source / drain junction on the exposed semiconductor substrate through high concentration impurity ion implantation; Forming a silicon film by selective deposition; And forming a silicide film on the silicon film. The present invention relates to a method for fabricating a MOSFET. The present invention provides a method for reducing junction capacitance through selective channel ion implantation and gate through nitrogen ion implantation. It improves the reliability of the oxide film and solves the shallow junction problem by selective silicon film deposition, thereby improving the characteristics of the sub-quarter micron MOSFET.

Description

모스트랜지스터 제조 방법Most transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 일실시예에 따른 MOSFET 제조 공정도.2A to 2E are MOSFET manufacturing process diagrams according to one embodiment of the present invention.

Claims (3)

모스트랜지스터(MOSFET) 제조 방법에 있어서, 반도체 기판의 채널 부위에 선택적으로 채널 이온주입을 실시하는 단계; 상기 반도체 기판 상에 게이트 산화막 및 게이트 전극용 폴리실리콘막을 형성하는 단계; 저농도 불순물 이온주입을 통해 노출된 반도체 기판에 저농도 불순물 영역을 형성하는 단계; 질소(N2) 이온주입을 실시하여 이후의 열공정에 의해 게이트 산화막이 질화되도록 하는 단계; 상기 폴리실리콘막 측벽에 절연막 스페이서를 형성하는 단계; 고농도 불순물 이온주입을 통해 노출된 반도체 기판에 소오스/드레인 접합을 형성하는 단계; 선택적 증착으로 실리콘막을 형성하는 단계; 및 상기 실리콘막 상에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 하는 모스트랜지스터 제조 방법.A method of manufacturing a MOSFET, comprising: selectively performing channel ion implantation into a channel portion of a semiconductor substrate; Forming a gate oxide film and a polysilicon film for a gate electrode on the semiconductor substrate; Forming a low concentration impurity region in a semiconductor substrate exposed through low concentration impurity ion implantation; Performing nitrogen (N 2 ) ion implantation so that the gate oxide film is nitrided by a subsequent thermal process; Forming insulating film spacers on sidewalls of the polysilicon film; Forming a source / drain junction on the exposed semiconductor substrate through high concentration impurity ion implantation; Forming a silicon film by selective deposition; And forming a silicide film on the silicon film. 제1항에 있어서, 상기 게이트 전극용 폴리실리콘막은 비도핑된 폴리실리콘막인 것을 특징으로 하는 모스트랜지스터 제조 방법.The method of claim 1, wherein the polysilicon film for the gate electrode is an undoped polysilicon film. 제1항에 있어서, 상기 실리콘막은 비도핑된 폴리실리콘막인 것을 특징으로 하는 모스트랜지스터 제조 방법.The method of claim 1, wherein the silicon film is a undoped polysilicon film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055943A 1995-12-23 1995-12-23 Most transistor manufacturing method KR970054387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950055943A KR970054387A (en) 1995-12-23 1995-12-23 Most transistor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055943A KR970054387A (en) 1995-12-23 1995-12-23 Most transistor manufacturing method

Publications (1)

Publication Number Publication Date
KR970054387A true KR970054387A (en) 1997-07-31

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Family Applications (1)

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KR1019950055943A KR970054387A (en) 1995-12-23 1995-12-23 Most transistor manufacturing method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273225B1 (en) * 1997-09-25 2001-01-15 김영환 Fabricating method for metal difflision prevention film in semiconductor device
KR100449323B1 (en) * 2001-12-26 2004-09-18 동부전자 주식회사 Method of manufacturing short-channel transistor in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273225B1 (en) * 1997-09-25 2001-01-15 김영환 Fabricating method for metal difflision prevention film in semiconductor device
KR100449323B1 (en) * 2001-12-26 2004-09-18 동부전자 주식회사 Method of manufacturing short-channel transistor in semiconductor device

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951223

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WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid