JPS60158669A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60158669A JPS60158669A JP59013677A JP1367784A JPS60158669A JP S60158669 A JPS60158669 A JP S60158669A JP 59013677 A JP59013677 A JP 59013677A JP 1367784 A JP1367784 A JP 1367784A JP S60158669 A JPS60158669 A JP S60158669A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- oxide film
- field effect
- effect transistor
- tox
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 1技術分野1 。[Detailed description of the invention] 1 Technical field 1.
本発明はMO8形電界効果トランジスタの改良2 に関
するものである。The present invention relates to improvement 2 of MO8 field effect transistors.
[従来技術1
一般に、従来のIVI OS形電界効果トランジスタに
おいて、ゲート酸化膜はゲートfi域全体に亘って一定
の膜厚が用いられる。[Prior Art 1] Generally, in a conventional IVI OS field effect transistor, a gate oxide film has a constant thickness over the entire gate fi region.
第1図は従来から用いられているこの種のMO8形電界
効果トランジスタを示す断面図で、シリコン基板lにソ
ース2.ドレイン3が形成され、この基板1上には全領
域で一定の膜厚のゲート酸化膜4が形成され、その上に
ゲート電極5が形成されている。FIG. 1 is a cross-sectional view showing this kind of conventionally used MO8 type field effect transistor, in which a silicon substrate 1 is provided with a source 2. A drain 3 is formed, a gate oxide film 4 having a constant thickness is formed over the entire region on the substrate 1, and a gate electrode 5 is formed on the gate oxide film 4.
MO8形電界効果トランシ゛スタの飽和領域動作におけ
るソース、ドレイン間電流1osはIb5= p(%−
VT)” −・・(1式)で表わされる。ここでv4は
ゲート電圧、VTは閾値電圧である。すなわちMO8形
電界効果トランジスタの能動デバイスとしての性能の一
つであるソース、ドレイン間電流をゲート電圧、閾値電
圧一定のもとで増大させるためにはβを大きくする必要
がある。The source-drain current 1os in the saturation region operation of the MO8 field effect transistor is Ib5=p(%-
VT)" -...(Equation 1) where v4 is the gate voltage and VT is the threshold voltage. In other words, the source-drain current is one of the characteristics of the MO8 field effect transistor as an active device. In order to increase with the gate voltage and threshold voltage constant, it is necessary to increase β.
しかるに従来のMO8形電界効果トランジスタにおいて
、βを増大させることができなかった。However, in the conventional MO8 field effect transistor, it was not possible to increase β.
この点を改良すべく研究の結果、本発明者はゲート中央
部のゲート酸化膜の厚さとデート両端部のゲート酸化膜
の厚さを変えること1こより、上記βの値を変化できる
ことを見出した。As a result of research to improve this point, the inventor found that the above value of β can be changed by changing the thickness of the gate oxide film at the center of the gate and the thickness of the gate oxide film at both ends of the gate. .
[発明の目的1
この発明の目的は飽和領域動作におけるソース、ドレイ
ン間電流を容易に大きくし得る半導体装置を提供するこ
とにある。[Object of the Invention 1] An object of the present invention is to provide a semiconductor device that can easily increase the current between the source and drain in saturation region operation.
[実施例1
第2図は本発明のMO8形電界効果トランジスタを示す
断面図で、従来形(第1図)との相異点はゲート酸化膜
4がゲート両端部4aで、ゲート中央部4bに比して厚
くなっている点である。[Example 1] FIG. 2 is a cross-sectional view showing an MO8 field effect transistor of the present invention. The difference from the conventional type (FIG. 1) is that the gate oxide film 4 is formed at both ends 4a of the gate, and at the central portion 4b of the gate. The point is that it is thicker than the .
ここで両端部とはソースとド/イン2と3と基板との境
界よりもある程度内側(チャンネル側)へ入り込んだ部
分から外側にある部分である。Here, both end portions are the portions located outside from the portions which are inward (to the channel side) to some extent from the boundaries between the sources, inputs 2 and 3, and the substrate.
第3図は本発明の詳細な説明するためのMOS形電界効
果トランジスタを示す断面図であり、デート中央部の酸
化膜厚をTox、両端部の酸化膜厚をTox*で示す。FIG. 3 is a cross-sectional view showing a MOS field effect transistor for explaining the present invention in detail, and the oxide film thickness at the center of the date is indicated by Tox, and the oxide film thickness at both ends is indicated by Tox*.
TOX*と(1式)のβとの関係を第・を図に示す。The relationship between TOX* and β in (Equation 1) is shown in Figure 1.
ここで゛はTox= 400人であり、Tox*=i″
ox”=400人の場合が従来形トランジスタである。Here, ゛ is Tox = 400 people, and Tox * = i''
The case where ox''=400 people is a conventional transistor.
第4図に見られる様に、Tox*をある最適値(この実
施例では1000人)にすることによってβの値が約1
6%大きくなり、トランジスタの性能向上が実現できる
ことが示されている。このゲート両端部の厚さTox*
は約800〜1400人の範囲であれぼβを天外くする
ことがでとる。As seen in Figure 4, by setting Tox* to a certain optimal value (1000 people in this example), the value of β is approximately 1.
It has been shown that the transistor performance can be improved by 6%. Thickness of both ends of this gate Tox*
This can be achieved by increasing the number of people in the range of approximately 800 to 1,400 people.
次に本発明の実施例の製造工程を述べる。まずシリコン
基板1を酸化してたとえば400人の均等な厚さのゲー
ト酸化膜4を形成し、その上にゲート電極としての不純
物をドープしたポリシリコン膜5を形成する(第5図(
a))。次にパターニングを行ない、ポリシリコン膜5
をマスクとして不純物のV−ピングを行ない、ソース、
ドレイン領域2,3を形成する。(第5図(b))。こ
の後、熱酸化を行なうことにより、ゲート5の両端部の
シリコン基板が酸化され酸化膜が上下両方向に成長し、
ゲート5の両端部4aの膜厚がたとえば1000人とデ
ート中央部4bの膜厚400人よりも厚いMO8形電界
効果トランジスタが得られる(第5図(C))。所望の
膜厚Tox木を得るためにほこの熱酸化の条件を制御す
ることによってiJ能である。Next, the manufacturing process of an example of the present invention will be described. First, a silicon substrate 1 is oxidized to form a gate oxide film 4 having a uniform thickness of, for example, 400 layers, and a polysilicon film 5 doped with impurities as a gate electrode is formed thereon (see FIG. 5).
a)). Next, patterning is performed to form a polysilicon film 5.
V-ping of impurities is performed using the mask as a source,
Drain regions 2 and 3 are formed. (Figure 5(b)). After that, by performing thermal oxidation, the silicon substrate at both ends of the gate 5 is oxidized, and an oxide film grows in both the upper and lower directions.
An MO8 type field effect transistor is obtained in which the film thickness at both end portions 4a of the gate 5 is, for example, 1000 mm thicker than the film thickness at the central portion 4b by 400 mm (FIG. 5(C)). It is possible to control the thermal oxidation conditions to obtain the desired film thickness.
もちろん熱酸化のときポリシリコンが酸化されないよう
1こ窒化シリコン酸(Si3N、)膜などで保護してお
く。Of course, the polysilicon is protected with a silicon nitride (Si3N) film or the like to prevent it from being oxidized during thermal oxidation.
[効果1
以上のように、この発明はMO3形電界効果トランジス
タのゲート酸化膜をゲート両端部で中央部よりも所定の
範囲内で厚くすることによって、(1)式のβを増大し
て飽和時のソース、ドレイン間電流を容易に増大するこ
とがでとる。[Effect 1 As described above, this invention increases β in equation (1) and saturates by making the gate oxide film of the MO3 field effect transistor thicker at both ends of the gate than at the center. This can be achieved by easily increasing the current between the source and drain.
なおゲート酸化膜の膜厚Tox+Tox*は上述の例に
は限られない。Note that the film thickness Tox+Tox* of the gate oxide film is not limited to the above example.
第1図は従来例のMO8形電界効果トランジスタの断面
図、第2図は本発明のMO8形電界効果トランジスタの
一実施例の断面図、第3図は本発明の詳細な説明するた
めの断面図、第4図は本発明によるMO3形電界効果ト
ランジスタの性能向上を示すβと’I’ox*の関係を
示すグラフ、第5図(a)、(I))、(c)は本発明
のMO8形電界効果トランジスタの製造方法の一例を示
す断面図である。
1・・・・・・シリコン基板、4・・・・・・デート酸
化膜、5・・・・・・デート電極、2,3・・・・・・
ソースとドレイン、TOX*・・・・・・デート両端部
のゲート酸化膜の膜厚、Tox・・・・・・デート中央
部のゲート酸化膜の膜厚。
特許出願人 シャープ株式会社
代 理 人 弁理士 青白 葆外2名
第4図
Tox’ IAIFIG. 1 is a sectional view of a conventional MO8 type field effect transistor, FIG. 2 is a sectional view of an embodiment of the MO8 type field effect transistor of the present invention, and FIG. 3 is a cross sectional view for explaining the present invention in detail. 4 is a graph showing the relationship between β and 'I'ox* showing the performance improvement of the MO3 field effect transistor according to the present invention, and FIG. FIG. 2 is a cross-sectional view showing an example of a method for manufacturing an MO8 field effect transistor. 1... Silicon substrate, 4... Date oxide film, 5... Date electrode, 2, 3...
Source and drain, TOX*...Thickness of the gate oxide film at both ends of the date, Tox...Thickness of the gate oxide film at the center of the date. Patent applicant Sharp Co., Ltd. Representative Patent attorney Aohaku Sogai 2 people Figure 4 Tox' IAI
Claims (1)
ゲート両端部でゲート中央部に比して、厚くしたことを
特徴とする半導体装置。A semiconductor device characterized in that a MO8 type field effect transistor gate oxide film is thicker at both ends of the gate than at the center of the gate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59013677A JPS60158669A (en) | 1984-01-28 | 1984-01-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59013677A JPS60158669A (en) | 1984-01-28 | 1984-01-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60158669A true JPS60158669A (en) | 1985-08-20 |
Family
ID=11839815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59013677A Pending JPS60158669A (en) | 1984-01-28 | 1984-01-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60158669A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244884A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
US5679968A (en) * | 1990-01-31 | 1997-10-21 | Texas Instruments Incorporated | Transistor having reduced hot carrier implantation |
US5698883A (en) * | 1989-10-09 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOS field effect transistor and method for manufacturing the same |
-
1984
- 1984-01-28 JP JP59013677A patent/JPS60158669A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244884A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
US5698883A (en) * | 1989-10-09 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOS field effect transistor and method for manufacturing the same |
US5679968A (en) * | 1990-01-31 | 1997-10-21 | Texas Instruments Incorporated | Transistor having reduced hot carrier implantation |
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