JPS59231864A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an offset gate type MISFET (MIs type field effect transistor), and in particular to a highly integrated MISFET.
The present invention relates to a technique that is effective when applied to a semiconductor device including an ISFET.

[Background technology]

In MISFETs that have short channels for higher integration, higher speed, etc., an offset structure is adopted to improve breakdown voltage. Even in this structure, the so-called self-line method is used to form the source and drain regions.

That is, after forming the gate electrode, impurity ions at a low concentration are implanted to form an offset region, and then a CVD5iO layer is formed as a sidewall on both sides of the gate electrode, and then impurity ions at a high concentration are implanted. This is a method for forming source and drain regions. The sidewalls are formed by a reactive ion etching method and are extended on both sides of the gate electrode.
The source and drain regions are offset by this sidewall (IIJE TRAN-
8ACTIONS ON ELECTRON DEVI
C.E.S.

VOL, ED-29, No. 4, 5341)).

By the way, in MISFET, after forming the source and drain regions, it is necessary to form a PSG film as an interlayer insulating film, form a contact hole in this, and then establish conduction with the source and drain regions using a conductive layer (1g layer). becomes.

However, according to studies conducted by the present inventors, if the hole formation position is shifted toward the gate electrode side when etching the contact hole, the etching of the PSG and the etching of the S
It was found that the iQ layer (sidewall) was also etched, and a contact hole was formed in the sidewall region, in other words, in the offset region. Therefore, a contact with the conductive layer is formed at the offset portion, resulting in deterioration of the characteristics of MISI''ET.

In order to prevent this, it is necessary to provide a margin for mask alignment between the contact hole formation position and the gate electrode, but this is extremely disadvantageous in terms of high integration. In addition, high precision is required for photomasks for contact holes.
Manufacturing operations will also become more difficult.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device that reliably prevents the formation of contact holes in the offset/node portions of MISFETs and stabilizes device characteristics while easily achieving high integration. It's about doing.

The above and other objects and novel features of the present invention include:
g) It will be clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by forming the sidewalls provided on both sides of the gate electrode for offset gate formation using polysilicon, the sidewalls will not be etched even when contact holes are formed by etching the PSG, and this will prevent the offset gate from being etched. This prevents the formation of contact holes in the parts, thereby achieving stable characteristics and high integration.

〔Example〕

1 to 7 show the semiconductor device of the present invention, particularly an offset gate type MI 5FET, in the order of its manufacturing process.

Step 1: As shown in Figure 1, a semiconductor (e.g. P-type silicon)
A field oxide film 2 is formed on the main surface of the substrate l by selective oxidation, while a gate oxide film 3 is formed on the active region. Further, after polysilicon is deposited on the entire surface, P (phosphorus) treatment is performed to inject P into the polysilicon. Next, the gate electrode 4 is formed by patterning the polysilicon using a conventional photoetching method. In this state, an N-type impurity ion, for example, As, is added at a low concentration, for example, I
The gate electrode 4 and the field oxide film 2 are formed at a dose of m-2.
Use it as a mask and apply it to the entire surface.

Next, as shown in FIG. 2, after forming an oxide film 5 on the surface of the gate electrode 40, a non-doped polysilicon film 6 is formed by CVD.
Deposit on the entire surface. Thereafter, by etching the entire surface of this polysilicon layer by reactive ion etching, polysilicon sidewalls 5a and 6a are formed on both sides of the gate electrode 40, as shown in FIG. and,
The surfaces of these sidewalls 5a, 6a are thinly oxidized to form oxide films 7, 7, and then high concentration, for example I
N+ type ions, e.g. arsenic A, at a dose of 10"m-2
Inject s. Thereafter, heat treatment is performed in a non-oxidizing atmosphere to complete the source and drain regions 8 and 9 and their respective offset regions 10 and 11, as shown in FIG.

Next, as shown in FIG. 5, a PSG film 12 as an interlayer insulating film is deposited over the entire surface by CVD, and contact holes 13 and 14 are opened on the source and drain regions 8 and 9 by a conventional method.

At this time, since there is etching selectivity between the PSG 12 and the polysilicon, a positional shift occurs in the contact holes 13 and 14, which leads to sidewall 6a + 6.
Even if the contact holes 13, 14 are formed along the outside of the side walls 6a, 6a, the side walls 6a, 6a, that is, the polysilicon, will not be damaged (see FIG. 6). reference). This prevents the contact holes 13 and 14 from being formed on the off-side region 10°11.

Thereafter, as shown in FIG. 7, aluminum is deposited on the entire surface and patterned by conventional photo etching to form an aluminum film 15.16, and a passivation film 17 is formed thereon.
Complete T.

〔effect〕

(1) Since the sidewalls formed on both sides of the gate electrode are made of polysilicon, the sidewalls are not etched during contact photoetching of PSG as an interlayer insulating film, and therefore the contact hole is not etched. It never forms on the sidewalls or in off-cent areas.

(2) Since the sidewalls are made of non-doped polysilicon, parasitic gates can be prevented due to the high resistance of non-doped silicon.

(3) Since the formation of a contact hole in the offset region can be prevented by the above (11, +21), the electrical characteristics of the offset gate type MISFET can be improved.

(4) Since the formation of contact holes in the offset region can be reliably prevented, contact holes can be easily formed and high integration of devices can be achieved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, when a material other than PSG film is used for the glabellar insulating film or a part of it, all the polysilicon in the sidewalls is oxidized and 5
It is possible to use a film other than polysilicon film such as the iQ2 film, that is, a film that has etching selectivity with respect to the interlayer insulating film. The field of application that formed the background for this was Offcella Toge (W)
Although the case where the present invention is applied to a MISFET semiconductor device has been described, the present invention can be applied to various semiconductor devices such as memory and logic to which this basic structure is applied.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views showing the manufacturing process of the apparatus of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor (silicon) substrate, 2... Field oxide film, 3... Gate oxide film, 4... Gate electrode,
6a...Side wall, 8...Source area, 9.
...Drain region, 10.11...Offset region,
12... Interlayer insulating film (PSG) 13.14... Contact hole 1.15, 16... Aluminum interconnect L17.
・・・ノ(Tsushibe IF!1 2nd +i Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] 1. A semiconductor having an M I S F E T with an offset gate structure, in which sidewalls are formed on both sides of a gate electrode, and source and drain regions of an offset gate structure are formed using the sidewalls. A device,
A semiconductor device characterized in that the side mail is formed of a material that is selective in etching with respect to the interlayer insulating film above the side mail. 2. A semiconductor device according to claim 1, in which the side mail is formed of non-doped polysilicon. 3. The semiconductor device according to claim 2, wherein an oxide film is formed by oxidizing the surface of non-doped polysilicon.