JPS63164554A - Automatic recognizing system for data speed - Google Patents

Abstract

PURPOSE:To improve the maneuverability of the titled system by providing the system with a processor for generating control signals for respective parts, reading out data from a buffer and analyzing receiving characters and allowing the processor to discriminate the transmission speed of an equipment to be connected. CONSTITUTION:When data for a specific character are sent from an opposite terminal, a shift register 3 fetches and shifts the transmitted dat one by one bit at every input of an output clock from a 1st counter 22. Data from the terminal are set in the order from the least significant bit of the specific character to a most significant bit and finally a parity bit. At the time of inputting the final parity bit, the output of the 1st counter 2 is fixed on a 'high' state, a sample clock input is stopped, the fetching operation of the shift register 3 is suspended and the processor 5 is interrupted. Thereby, the processor 5 applies a read signal, fetches the value of the shift register 3 to an 8-bit buffer 4 and reads out the data through a bus to decide data applied from the opposite equipment based on the received data.

Description

[Detailed Description of the Invention] [Summary] The present invention receives predetermined specific transmission characters at a fixed rate, and recognizes the transmission data rate by utilizing the fact that the received characters related to the transmission rate are different. This is how it was done.

[Field of Industrial Application] The present invention relates to a system for recognizing the data speed of a connected device in a device that transmits and receives serial data between a connected device and the like, such as a connection between a terminal and a modem.

[Prior art] Conventionally, terminals and modems have had to match the data speed of the connected device, and usually have their own receive data speed matched to the data speed of the connected device by setting a switch, keyboard, etc. Ta.

[Problems to be Solved by the Invention] With such a conventional method, manual intervention is required every time the data rate is changed, which poses a problem in operability.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic data rate recognition system that can improve operability by automatically identifying the data rate of a connected party. .

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure, 1 is a start bit detection means for detecting the start bit of serial transmission data from a terminal to be connected, 2 is a sample clock generation means for counting a reference clock and generating a predetermined number of sample clocks, and 3 is a sample clock. A shift register that takes in specific character data transmitted from a partner terminal based on a clock; 4 a buffer that temporarily stores and outputs the parallel output of the shift register 3; 5 a buffer that generates control signals for each part and receives them from the buffer 4; A processor that reads data and analyzes incoming characters.

[Operation] In the present invention, the shift register 3 receives specific character data from the other terminal at the highest data speed that can be connected, and the processor 5 analyzes the obtained received data.
The transmission speed of the other party's character is identified based on the fact that the specific character is converted into different specific data and received in relation to the transmission data speed.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of a device having an automatic recognition function provided in a modem. Start data speed by 300
．． An example will be shown in which the speed is 600.1200.2400 bits per second (bps). Note that the predetermined specific character is serial data of 8 bits consisting of 7 bits of data and 1 bit of even parity.

In FIG. 2, parts equivalent to those in FIG. 1 are given the same reference numerals. 21 is a flip-flop (hereinafter abbreviated as FF),
22 is a first counter, and 23 is a second counter.

24 and 25 are Nante gates, respectively. Note that a simple inverter may be used instead of the Nant gate.

The FF 21 is a Tsuji-trigger type FF, and a HIGH level signal (hereinafter simply referred to as HIGH) is applied to the D input terminal, and receives transmission data from a terminal applied via the Nant gate 24 as a clock. Also, FF21
is reset by the reset signal from the processor 5, and the Q output becomes a LOW level signal (hereinafter simply abbreviated as LOW?1).
')become.

Its Q output is inverted to "HIGl" at the rising edge of the input clock. This Q output is guided to the first counter 22 as a reset signal. The gate 24 and the FF 21 constitute the start bit detection means 1.

The first counter 22 divides the 38.4 KHz input clock into 1/16, and the divided outputs are given as clocks to the second counter 23 and the shift register 3, respectively. The first counter 22 constitutes the sample clock generating means 2.

The second counter 23 divides the input clock into 1/9,
The frequency-divided output passes through the Nant gate 25 and becomes an enable signal for the first counter 22 and an interrupt signal for the processor 5. Further, the second counter 23 is reset by a reset signal from the processor 5.

The shift register 3 is an 8-bit shift register that receives transmission data applied from a terminal, takes it in using a sample clock, and shifts it bit by bit. The output of the first counter 22 is used as the sample clock.

The buffer 4 is used for reading from the processor 5.
) signal to take in the 8-bit shift output, and the output is sent to the processor 5 via a data bus (not shown).
sent to.

The operation in such a configuration will be explained next with reference to the time chart of FIG. The FF 21 and the second counter 23 are reset by a reset signal (Reset) from the processor 5 in the initial state. (c) in Figure 3
Transmission data (SD) from the terminal as shown in
At the falling edge of the start bit (rising edge of the output of gate 24), the Q output of F21 changes from LOW to HIGH.
The first counter 22 is reset and then starts counting 38.4KH2 clocks. The first counter 22 has a frequency of 38°4KHz (
38.4, the clock frequency is divided by 1/16 to create a sample clock of 2400H2 as shown in the figure (a).

The second counter 23 further counts the output of the first counter 22, and after counting 9 times, its Q output becomes HIGH.
become. This l-11G +-1 signal is inverted via the gate 25 to cause the first counter 22 to stop counting and to interrupt the processor 5 on the other hand. In addition, the data SD sent from the terminal and 38°4
It is synchronized with the clock of K I-1z, therefore,
The transmission data SD and the output (sample clock) of the first counter 22 are synchronized as shown in FIG.

Now, let the specific character sent from the terminal be 'U°' (code 551-1: l-1 represents a hexadecimal number),
To explain the case of transmission at 2400 bps, the shift register 3 takes in and shifts the transmission data one bit at a time each time the output clock of the first counter 22 is input. The data from the terminal is from the least significant bit to the most significant bit of a specific character (7 bits),
Finally, the parity bit is sent.

Therefore, as shown in FIG. 3(c), the shift register 3 has 1, 0, 1, . ．． 0,1,0,1. Enter O. At the time when the last parity bit "'Opar" is fetched, the output of the first counter is fixed to HIGH, the sample clock input is stopped, the shift register fetch operation is interrupted, and the processor 5 is interrupted.

Therefore, the processor 5 applies a read signal (Read) to take the value of the shift register into the 8-bit buffer 4, reads the data via the bus, and determines the data from the other party based on the received data.

In this case, since the parity is LL Q 11 and the received data is '551-1', it is determined that the data rate from the terminal (from the other party) was 2400 bps.

In addition, in the case of other data rates, as shown in Figure 3,
At 1200 bps, 66 as shown in the same figure (d)
When the speed is 600 bps, the received data is 78H, as shown in FIG.

Although the above embodiment uses a circuit made up of separate parts, it is also possible to use an LSI as shown in FIG. In FIG. 4, 41 is a transmitter/receiver having the functions shown in FIG. In this case, (1) the connection partner has the following data speed and character configuration.

a) Data rate is 2400,1200.600.30
4 types of 0 bps.

b>Character configuration is start-stop, 7 bits, even parity.

C) The transmission specific character is "U" <55H>.

■The receiving side is 2400bl) S, start/stop, 7 bits, even parity.

Under these conditions, the specific character to be transmitted is 'Ll' (55H), and the transmission data rate is 2400 bp.
s, the received data will be character code 55H1 with no parity error and no framing error, and if the transmission data rate is 1200 bps, the reception data will be character code 66H1 without parity error and framing error, and the transmission data rate will be 600 bps.
In this case, the received data will be character code 78H1 without a parity error and with a framing error, and if the transmission data rate is 300 bps, the character code will be 5.
5H1 Received data with no parity error and no framing error.

In this way, the data rate of the terminal can be recognized based on the received characters and error status. In this case, automatic recognition as described above can be performed in devices that currently have LSI transmitters/receivers by adding some software.

In addition, in the above explanation, "u" is used as the transmission character code.
” is used as an example, but other characters may be used.

[Effects of the Invention] As described above in detail, according to the present invention, the pig speed from the connected device can be automatically recognized with a simple configuration, so that operability and performance are improved.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a configuration diagram showing an embodiment of the invention, Fig. 3 is a time chart for explaining the operation, and Fig. 4 is another embodiment of the invention. FIG. 5 is a time chart for explaining the operation in the configuration of FIG. 4. 1 and 2, 1 is a start bit detection means, 2 is a sample clock generation means, 3 is a shift register, 4 is a buffer, 5 is a processor, 21 is a flip-flop, 22 is a first counter, 23 is the second counter, and 24.25 is the Nante gate.

Claims (1)

[Scope of Claims] A device that transmits and receives serial data to and from a connected device, comprising: start bit detection means (1) that detects a start bit of serial transmission data from a connected device; and a reference clock that counts a reference clock. sample clock generating means (2) for generating a predetermined number of sample clocks, a shift register (3) for taking in specific character data transmitted from the connected partner using the sample clock, and temporarily controlling the parallel outputs of the shift register. It is equipped with a buffer (4) for storing and outputting data, and a processor (5) for generating control signals for each part, reading data from the buffer (4), and analyzing received characters. receiving the specific character with a sample clock;
An automatic data rate recognition system characterized in that the processor identifies the data transmission rate of a connection partner by utilizing the fact that the specific character is received as different character data in relation to the data rate.