JPH04111637A - Data transmission speed automatic recognition device - Google Patents

Abstract

PURPOSE:To receive a data at an optional transmission speed by sampling and storing a reception data and reading the data in response to a request of a master set. CONSTITUTION:A reception data is inputted to a start bit detection circuit 1 and a latch circuit 3. The detection circuit 1 sends a count start signal to an address control circuit 2. The control circuit 2 gives a clock from a clock generator 8 to the latch circuit 3, which latches the reception data. A selector 4 stores the reception data to a memory 5 and outputs the reception data to a bit check circuit 6 from a memory 5. The bit check circuit 6 outputs a reception data to the latch circuit 7 when no error exists and outputs an interruption signal to a CPU of a master set simultaneously. The latch circuit 7 latches the reception data till the CPU of the master set reads the data. The CPU of the master set reads the reception data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic data transmission rate recognition device used in start-stop synchronous communication, and particularly to a device used in a communication device using a central processing unit (CPU).

[Conventional technology]

Conventionally, in asynchronous communication, it is necessary for the receiving side to know the transmission speed in advance and set that value in the receiving device. For this reason, a device has been proposed that automatically determines the transmission speed on the receiving side. For example, as disclosed in Japanese Patent Application Laid-open No. 1-305644, the transmitting side manipulates the data to a specific focus, and the receiving side The speed is automatically determined by using bits.

[Problem to be solved by the invention]

However, the former receiving device has a problem in that even if the transmission rate is known in advance and the value is set, the transmission rate is fixed and it is not possible to connect to a terminal with a different transmission rate.

In addition, the latter type of receiving device that automatically determines the transmission speed requires modification of the data on the transmitting device side, so it cannot be connected to a general-purpose device to automatically determine the transmission speed.
There is a problem in that it is necessary to use a dedicated transmitter.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic data transmission rate recognition device that can be connected to a general-purpose device and can receive data at any transmission rate.

[Means for Solving the Problems] The data transmission speed automatic recognition device of the present invention includes a start focus detection circuit that detects the start bit and g of start-stop synchronization communication, a latch circuit that samples received data, and a A memory that stores data, a selector that controls input/output from the memory during sampling and bit checking, an address control circuit that controls memory addresses for sampling and focus checking, and bits that check start bit, stop bit, and parity focus. It consists of a check circuit and a latch circuit connected to the central processing unit of the parent device.

Note that the address control circuit is configured to operate the latch circuit and memory using a high-speed clock from the clock generator.

[Effect]

According to the present invention, received data is sampled and stored at high speed from the time the start focus is detected, and error checking is performed using the sampling data corresponding to the transmission speed to meet the requests of the parent device. Since the received data is read accordingly, it is possible to deal with various different transmission speeds.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing the main parts of a receiving device. When the receiving device receives received data, this received data is input to a start bit detection circuit 1 and a latch circuit 3. When the start focus detection circuit 1 detects a falling edge of the received data, it sends a count start signal to the address control circuit 2. The address control circuit 2 passes the 1/19200 clock from the clock generator 8 to the latch circuit 3, and latches 1! I3 thus latches the received data.

At the time of data latching, the selector 4 passes the received data from the latch circuit 3 to the memory 5, and the memory 5 stores the received data latched at the address given by the address control circuit 2 in synchronization with the clock.

Further, when the required number of received data is latched, the address control circuit 2 outputs the received data stored through the selector 4 from the memory 5 to the bit check circuit 6. At this time, the address of the stored received data is specified in response to a request from the bin check circuit 6.

The bit check circuit 6 checks the start focus, stop bit, and parity bit of the input received data, and if there is no error, outputs the received data to the latch circuit 7, and at the same time outputs an interrupt signal to the CPU of the parent device.

The latch circuit 7 holds the received data until the CPU of the parent device reads the data. It goes without saying that the CPU of the parent device reads the received data at its own speed, which is unrelated to the transmission speed of the received data.

FIG. 2 is a processing flow diagram in the data transmission rate automatic recognition device of the present invention.

FIG. 3 shows data sampling timing and addresses used for bit checking in the data transmission rate automatic illumination device of the present invention. Sampling is 1/19200
This is done using a fixed clock, and the address used for checking is also focused on a specific pattern and used, so the circuit size can be reduced. Furthermore, even for low-speed data, the sampling position can be set near the center of the data change point.

Therefore, in this device, the received data is sampled at a high speed clock (1/19200) from the time the start bit is detected, this is stored in the memory, and an error check is performed using the sampling data corresponding to the transmission speed. Then, by reading the received data according to the request of the parent device, it becomes possible to support any transmission speed. It becomes possible to connect to.

In addition, since error checking is performed for each piece of data, it is possible to cope with changes in transmission speed in units of data.
It is also possible to connect to multiple communication paths with different transmission speeds.

[Effects of the Invention] As explained above, the present invention samples received data, stores it, and reads it in response to a request from the parent device. This has the effect of making it possible to connect terminals with different transmission speeds, and to construct a communication system that can receive data at any transmission speed.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of the main parts of a receiving device to which the automatic data rate recognition device of the present invention is applied, Fig. 2 is a flow diagram of the processing for determining the transmission rate, and Fig. 3 is the data sampling timing and check address. FIG. DESCRIPTION OF SYMBOLS 1... Start bit detection circuit, 2... Address control circuit, 3... Latch circuit, 4... Selector, 5...
...Memory, 6...Bit check circuit, 7...Latch circuit, 8...Clock generator. Figure 2

Claims (1)

[Claims] 1. A start bit detection circuit that detects the start bit of asynchronous communication, a latch circuit that samples received data, a memory that stores sampled received data, and a memory that stores sampled received data during sampling and bit checking. A selector that controls the input/output of the main unit, an address control circuit that controls memory addresses for sampling and bit checking, and a bit check circuit that checks the start bit, stop bit, and parity bit, and the central processing unit of the parent device. What is claimed is: 1. A data transmission speed automatic recognition device comprising: a latch circuit; 2. The data transmission rate automatic recognition device according to claim 1, wherein the address control circuit operates the latch circuit and the memory using a high-speed clock from a clock generator.