JPH0537572A - Data transmission speed converter - Google Patents

Abstract

PURPOSE:To attain the connection of a communication line at an optional transmission speed to an input section by recognizing an inputted data transmission speed and outputting a data at the fixed transmission speed when the communication line whose transmission speed is unknown is connected. CONSTITUTION:A buffer 1 converts an input signal of a level of RS-232C into a TTL level. When a start bit detection circuit 2 detects the trailing of a data, an address control circuit 3 detects a clock 21, a latch circuit 4 samples a data according to the clock and latches it, a selector 5 is thrown to the position through which a data is sent from the circuit 4 to a memory 6. The circuit 3 counts the clock number and outputs the storage data in the memory 6 to a bit check circuit 7, which checks a start stop bit and a parity bit and a conversion circuit 8 applies P/S conversion to the data when no error is in existence, and a buffer 9 restores the data of TTL level into a level of the RS-232C and outputs the result to a terminal equipment. Thus, the communication line at an optional transmission speed is connected to the input section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission rate conversion device, and in particular, in start-stop synchronization communication, data transmission to be input when a general-purpose terminal whose input data transmission rate is undetermined is connected to another terminal. The present invention relates to a data transmission rate conversion device which recognizes a rate and outputs data having a fixed transmission rate.

[0002]

2. Description of the Related Art In a conventional asynchronous communication circuit, once the transmission speed is set, it is fixed at that transmission speed.
It was necessary to know the transmission rate input in advance and set that value. As a method of automatically determining the input transmission rate, a counter that counts the length of this start bit is requested by the transmission side so that the bit next to the start bit of the data is always "1". Is provided, and the data transmission rate is automatically determined based on this count value.
(See, for example, JP-A-1-305644)

Since the above-mentioned conventional asynchronous communication system has a fixed transmission rate, it has a drawback that it cannot be connected to terminals having different transmission rates. Further, in the conventional method of automatically determining the transmission rate, it is necessary to modify the data as described above on the transmitting device side, so it is not possible to connect to a general-purpose device to automatically determine the transmission rate and to use a dedicated transmitting device. There is a drawback that it is necessary to use.

[0003]

SUMMARY OF THE INVENTION The data transmission rate apparatus of the present invention comprises a level conversion buffer for converting an RS-232C level into a TTL level and a start / stop synchronization data signal based on a clock generated in the apparatus. A start bit detection circuit that detects a start bit, a latch circuit that samples and temporarily holds data, a memory that stores the sampling data of this latch circuit, and an input / output from the memory at the time of sampling and bit check Selector, an address control circuit that counts the number of clocks from the start bit and controls sampling timing and a bit check memory address, a bit check circuit that checks a start / stop bit and a parity bit, and Converts data from parallel to serial / And S conversion circuit, the TTL level R
And a level conversion buffer for converting to a T-232C level.

[0004]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a timing chart of data sampling of this embodiment, and FIG. 3 is a bit check address of this embodiment. In FIG. 1, the level conversion buffer 1 converts a signal input at the RS-232C level into a TTL level. The start bit detection circuit 2 sends a count start signal to the address control circuit 3 when detecting the fall of the received data. The address control circuit 3 passes the 19200 BPS clock 21 to the latch circuit 4. The latch circuit 4 samples and latches data according to the clock. The selector 5 passes data from the latch circuit 4 to the memory 6 at the time of data latch.
The memory 6 stores the data latched at the address given by the address control circuit 3. When the address control circuit 3 latches the necessary data, it outputs the data from the memory 6 to the bit check circuit 7. The bit check circuit 7 checks the start / stop bit and the parity bit, and if there is no error, outputs the data to the parallel / serial conversion circuit (P / S) 8. P / S8 is 19
Parallel / serial conversion of data is performed with a clock of 200 BPS. The level conversion buffer 9 restores the serially converted TTL level data to the RS-232C level and outputs it to the terminal device.

Next, one type of fixed clock (19200B
The relationship between the sampling address and the timing of sampling the input data whose transmission rate is indefinite by PS) will be described with reference to FIGS. FIG. 2 shows a clock 19
Baud rate of 1, 1/2, 1/4, 1 with 200 BPS
/ 8, 1/16 5th speed, that is, 19200 BPS,
9600BPS, 4800BPS, 2400BPS, 1
It shows the case of determining the transmission rate of 200 BPS,
In the case of a transmission rate of 9600 BPS, the positions of sampling addresses 1, 3, 5 to 19 (circles in the figure) are sampled with respect to the sampling positions defined by the clock. As shown in FIG. 3, when the data bit is the start bit 1, the data is 7 bits from the LSB to the MSB, the parity bit 1 and the start bit 1, the position "1001B" of the address 19 of the stop bit is checked to check the transmission speed. It is determined to be 9600 BPS. Similarly, 4800
In the case of BPS, the position "1001B" of the sampling address 38 is checked, it is determined that it is a stop bit, and the transmission rate is 4800 BPS. Such an operation is performed for each data transmission rate by the start bit detection circuit 2, the address control circuit 3, the latch circuit 4, the selector 5,
This is performed by a data transmission rate recognition circuit formed by the memory 6 and the bit check circuit 7. This data is P /
The S conversion circuit 8 converts it to a fixed transmission rate of 19200 BPS and outputs it.

As described above, sampling is performed in 1920
The circuit scale can be reduced because the address used for checking is bit-shifted with a specific pattern and used with a constant clock of 0 BPS. Even for low speed data, the data check point can be near the center of the data change point.

[0007]

As described above, by inserting the data transmission rate converter main body of the present invention into the asynchronous communication channel, the data is sampled by the high speed clock from the start bit detection, and the sampling data corresponding to the transmission rate is obtained. The error check is performed by using the communication path from 150 baud to 19.2 kilobaud for which the transmission rate of the input data is unknown, and it is automatically converted to a fixed transmission rate of 19.2 kilobaud and transmitted to the terminal. It is possible to connect a communication path of transmission speed. In addition, since error checking is performed for each data, it is possible to cope with the case where the transmission rate of the data changes in units of 1 byte, so that it is possible to convert the transmission rate of a plurality of communication paths with different transmission rates with one circuit. Has the effect of

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a sampling timing chart for explaining the present embodiment.

FIG. 3 is an explanatory diagram of sampling addresses for explaining the present embodiment.

[Explanation of symbols]

1 level conversion buffer 2 Start bit detection circuit 3 Address control circuit 4 Latch circuit 5 selector 6 memory 7-bit check circuit 8 Parallel / serial conversion circuit (P / S) 9 level conversion buffer

Claims (3)

[Claims] 1. A level conversion buffer for converting an RS-232C level to a TTL level, a start bit detection circuit for detecting a start bit of an start / stop synchronization data signal based on a clock generated in the present device, and data Latch circuit for sampling and holding temporarily, memory for storing sampling data of this latch circuit, selector for controlling input / output from the memory at the time of sampling and bit check, and counting the number of clocks from the start bit And an address control circuit for controlling sampling timing and memory address for bit check,
A bit check circuit for checking a start / stop bit and a parity bit, a P / S conversion circuit for performing parallel / serial conversion on the checked data, and a level conversion buffer for converting a TTL level into an RT-232C level. And data transmission rate converter. 2. The data transmission rate converter according to claim 1, wherein the sampling address of the address control circuit is generated by bit-shifting a specific bit pattern. 3. A clock for the sampling is the P
The data transmission rate conversion device according to claim 1, wherein the data transmission speed conversion device is used as a clock of a serial data signal output from the / S conversion circuit.