KR100202170B1 - Receiving method and its apparatus of data for serial interface - Google Patents

Abstract

The present invention relates to a data receiving apparatus for a serial interface, and receives serial data and shifts the data according to a synchronous clock to parallel data. The clock counter counts the synchronous clock to detect when the shift register is full of data, and generates a carry signal when the shift register is full. The latch unit is enabled by the carry signal to receive and latch the parallel data. Data latched in the latch unit is input to the buffer unit, and the data, enabled by the second control signal, is output to the memory. The memory is enabled by the first control signal to store data output from the buffer unit. The control means receives the carry data and the serial data reception permission signal from the outside and generates a first control signal and a second control signal.

Description

Data receiver for serial interface

1 is an exemplary view for explaining a schematic operation sequence of a receiving device for a serial interface according to the present invention.

2 is an exemplary block diagram embodying the concept of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

1: 3 bit counter 2: AND gate

3, 4: JK flip-flop 5: DMA controller

6: Interrupt Processing Unit 7: 8-bit Shift Register

8 latch portion 9 buffer

10: DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receive part of a serial interface, and more particularly, to a receiving device for a serial interface adapted to interface with a PC and an external device.

In general, a method of communicating with an external device in a computer may be classified into a serial communication method and a parallel communication method. When a device such as a mouse or a digitizer is used, serial communication is performed.

At this time, a serial data receiving device for serial communication with a peripheral device in a PC has not been widely known until now, and often used a method of searching and receiving 8-bit valid data when receiving data using software.

This conventional method has a problem in that the CPU efficiency decreases because the CPU, which is a central processing unit, needs to simultaneously perform an operation process for the operation of the PC while executing the serial data reception software for serial communication.

An object of the present invention for solving such a problem is to provide a receiving device for a serial interface suitable for the interface between a PC and an external device.

A data receiving apparatus for a serial interface according to the present invention for achieving the above object comprises a shift register, a clock counter, a latch unit, a buffer unit, a memory, and a control unit. The shift register receives serial data and shifts it to parallel data according to a synchronous clock. The clock counter counts the synchronous clock to detect when the shift register is full of data, and generates a carry signal when the shift register is full. The latch unit is enabled by the carry signal to receive and latch the parallel data. Data latched in the latch unit is input to the buffer unit, and the data, which is enabled by the second control signal and is input, is output to the memory. The memory is enabled by the first control signal to store data output from the buffer unit. The control means receives the carry data and the serial data reception permission signal from the outside and generates a first control signal and a second control signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is an exemplary diagram for explaining a schematic operation sequence of a receiving device for a serial interface according to the present invention. In the shift register unit A, the serial data SD input by the sync clock RCLK is a bit. Each bit is shifted up to 8 bits. The 8-bit data stored in the shift register unit A is transferred to the latch unit B by the reception termination RSTP of 1 byte. The reception buffer C receives data latched to the latch unit B by a permission signal ACK generated by a DMA controller (not shown) or a CPU permission signal generated by an interrupt. Transmits the data.

The above description of FIG. 1 is shown in FIG. 2 to which a block configuration incorporating this is applied as a concept applied in the present invention. As shown in FIG. 2, the 3-bit clock counter 1 counts the received sync clock RCLK. The AND gate 2 receives the carry data output from the clock counter 1 and a reception permission signal generated from a CPU (not shown) and performs an AND operation to output the calculated value. The interrupt processor 6 receives the output signal of the AND gate 2 and performs processing related to the interrupt generation from the CPU. The DRAM 10 stores data input according to a control signal. A direct memory access controller (DMA) 5 controls an operation for storing or reading data in the DRAM 10. The first JK flip-flop 3 inputs an interrupt processing signal generated by the interrupt processing unit 6 or a permission signal ACK generated by the DMA controller 5 to generate a signal for determining a buffer full state. Enable 10). The second JK flip-flop 4 receives the same data input to the first JK flip-flop 3 and generates a request signal for accessing the DRAM 10 to the DMA controller 5. The 8-bit shift register 7 receives serial data SD according to the synchronous clock RCLK and converts the serial data SD into 8-bit parallel data. The latch unit 8 is composed of eight buffers, and receives and generates data generated by the 8-bit shift register 7 by using a carry signal generated by the 3-bit clock counter 1 as an enable signal. The buffer 9 temporarily stores the data output from the latch unit 8 before storing it in the DRAM 10.

Looking at the preferred operation of the receiving device for a serial interface according to the present invention configured as described above are as follows.

The 8-bit shift register 7 shifts the input serial data SD by one bit according to the synchronization clock RCLK. At this time, the 3-bit counter 1 counts the synchronous clock RCLK and provides a signal indicating that 8 bits have been received, that is, a carry signal to the latch unit 8 as an enable signal. The latch unit 8 receives and latches data generated from the shift register 7.

The carry signal output from the 3-bit counter 1 is input to the AND gate 2 to be ANDed with the reception permission signal generated by the CPU. The output of the AND gate 2 is used as an interrupt signal or a DMA request signal. Note that the data transfer must be determined by the firmware (FIRMWARE) whether to handle the interrupt or the DMA request signal.

In this case, assuming that the DMA request signal is processed, a signal of logic '1' is applied to the first input terminal J and the logic '0' is applied to the second input terminal K of the two input terminals of the second JK flip-flop 4. By inputting a signal, the output becomes one.

Accordingly, since the state of the output signal of the second JK flip-flop 4 is logic '1', the DMA controller 5 which receives the signal generates the address of the desired RAM by activating the serial DMA request signal. Generate an grant signal (ACK) for the serial DMA request signal. The permission signal ACK generated by the DMA controller 5 is input to the second input terminal K of the second JK flip-flop 4, and the logic value at this time maintains a state of '1'. As a result, the output has a value of logic '0'.

As the state of the output value of the second JK flip-flop 4 becomes a logic '0', the DMA controller 5 receiving this signal disables the permission signal ACK generated.

At the moment when the output of the AND gate 2 is a logic '1', the output signal of the first JK flip-flop 3 remains the same as the output of the second JK flip-flop 4 while the buffer ' 9) is provided as a enable signal of the DRAM 10 to warn that the data is full. The DRAM 10 stores data stored in the buffer 9 at an address, and thus the buffer 9 becomes empty.

Thereafter, the buffer 9 is enabled by the permission signal ACK generated by the DMA controller 5 in accordance with the above-described operation, and the new data in the latch 8 is stored. This completes one operation and the above operation is performed at about the same time.

Providing the receiving device for the serial interface according to the present invention operating as described above, it is possible to receive the serial data with a relatively simple device, it is possible to reduce the cost. In addition, by providing a counter, 8-bit data can be transmitted using a simple device without additional calculation.

Claims (3)

A shift register which receives serial data and shifts the parallel data according to a synchronous clock; A clock counter for counting the synchronization clock to detect a time point when the shift register is full of data and generating a carry signal when the shift register is full; A latch unit enabled by the carry signal to receive and latch the parallel data; A buffer unit configured to input data latched to the latch unit and to output data, which is enabled by a second control signal and inputted to the memory; A memory enabled by a first control signal to store data output from the buffer unit; And control means for receiving the carry data and the serial data reception permission signal and generating the first control signal and the second control signal. 2. The apparatus of claim 1, wherein the control unit comprises: an AND gate configured to receive the carry signal and the serial data reception permission signal and perform an AND operation; An interrupt processor which receives an output signal of the AND gate and generates an interrupt control signal; A memory controller for generating a memory access permission signal; A first JK flip-flop that receives the output signal of the AND gate and the second control signal and generates the first control signal; And a second JK flip-flop for receiving the output signal of the AND gate and the second control signal to generate the memory controller control signal. The apparatus of claim 1 or 2, wherein the second control signal comprises the interrupt processing signal or the memory access permission signal.