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JPS6232656A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6232656A
JPS6232656A JP17124685A JP17124685A JPS6232656A JP S6232656 A JPS6232656 A JP S6232656A JP 17124685 A JP17124685 A JP 17124685A JP 17124685 A JP17124685 A JP 17124685A JP S6232656 A JPS6232656 A JP S6232656A
Authority
JP
Japan
Prior art keywords
melting point
thin film
point metal
high melting
metal thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17124685A
Other languages
Japanese (ja)
Inventor
Yoichi Kuriyama
洋一 栗山
Shinichi Ofuji
大藤 晋一
Hitoshi Nagano
永野 仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17124685A priority Critical patent/JPS6232656A/en
Publication of JPS6232656A publication Critical patent/JPS6232656A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an element having excellent high frequency characteristics, by providing a very thin layer, which includes a material, whose bonding strength with oxygen is higher than any of a semiconductor substrate and a high melting point metal thin film, between the semiconductor substrate and the high melting point metal thin film. CONSTITUTION:On one main surface of a semi-insulating substrate 1, an N-type active layer 2 is formed by using a selective ion implanting technology. Then, by using a magnetron sputtering method, Si and W are sequentially deposited. An electrode is machinged by a dry etching technology using CF4+O2. Then heat treatment is performed. Thereafter, gold (Au)-germanium (Ge) (12wt% Ge is included) is deposited by an electron beam evaporation method to a thickness of about 1,500Angstrom . Nickel (Ni) is deposited by the same evaporation method to a thickness of about 500Angstrom . Electrodes are machined by a liftoff method. Then, heat treatment is performed in argon (Ar) bubbles for one minute, and a source electrode 6 and a drain electrode 7 are formed. Thus the gate electrode characterized by low resistance and high heat resistance in comparison with a conventional technology can be implemented.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、化合物半導体装置及びその製造方法に関する
ものである。特に、高融点金属?I!膜をゲート電極に
有する化合物半導体装置及びその製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a compound semiconductor device and a method for manufacturing the same. Especially high melting point metals? I! The present invention relates to a compound semiconductor device having a film as a gate electrode and a method for manufacturing the same.

(発明の概要) 本発明は、半導体基板の1主面上に高融点金属薄膜を有
する半導体装置において、前記半導体基板と前記高融点
金属薄膜の間に、前記半導体基板および前記高融点金属
薄膜のいずれよりも酸素との結合力の大きな物質からな
る厚さ2〜100Aの中間層を有することによって、低
抵抗率かつ耐熱性の高い高融点金属薄膜からなるゲート
電極を有する半導体装置をつることにある0 また本発明な、半導体基板の1主面上に、高融点金属薄
膜を堆積する工程ケ含む半導体装置の製造方法において
、前記高融点金属薄[’(z堆積する前に、中間層とし
てスパッタリング法。
(Summary of the Invention) The present invention provides a semiconductor device having a high melting point metal thin film on one main surface of a semiconductor substrate, in which the semiconductor substrate and the high melting point metal thin film are disposed between the semiconductor substrate and the high melting point metal thin film. By having an intermediate layer with a thickness of 2 to 100 A made of a material with a stronger bonding force with oxygen than either of these, it is possible to create a semiconductor device having a gate electrode made of a high melting point metal thin film with low resistivity and high heat resistance. 0 Also, in the method of manufacturing a semiconductor device according to the present invention, which includes a step of depositing a high melting point metal thin film on one main surface of a semiconductor substrate, the high melting point metal thin film ['(z) is deposited as an intermediate layer before being deposited. Sputtering method.

蒸着法、気相成長法のいずれかによりシリコン(St)
e堆積することによって低抵抗率かつ耐熱性の高い高融
点金属薄膜からなるゲート電極を有する半導体装置の製
造方法を提供することにある。
Silicon (St) by either evaporation method or vapor phase growth method
An object of the present invention is to provide a method for manufacturing a semiconductor device having a gate electrode made of a high melting point metal thin film having low resistivity and high heat resistance by e-deposition.

(従来技術及び発明が解決しようとする問題点)近年、
数GHz以上の高周波帯での通信において、化合物半導
体、例えば砒化ガリウム(GaAs )を用い友素子が
注目されており、特に高融点金属薄11iffiゲート
電極に有する素子は、製造工程の簡単さのために注目さ
れ研究開発がさかんに行なわれている。
(Prior art and problems to be solved by the invention) In recent years,
In communication in high frequency bands of several GHz or higher, friend elements using compound semiconductors, such as gallium arsenide (GaAs), are attracting attention. In particular, elements with high-melting point metal thin 11iffi gate electrodes are attracting attention due to the simplicity of the manufacturing process. is attracting attention and research and development is being actively carried out.

砒化ガリウム(GaAs )ショットキーゲート電界効
果トランジスタを例にとり、従来の高融点金属薄1li
Iをゲート電極に有する半導体装置の主要部の断面図を
第3図に示す。第3図において、1は半絶縁性基板、2
はn型能動層であり、直列抵抗を低減するためにソース
・ドレイン領域にn+領域3.4が設けられている。5
はショットキーゲート電極、6はソース電極、7はドレ
イン電極である。
Taking a gallium arsenide (GaAs) Schottky gate field effect transistor as an example, the conventional refractory metal thin 1li
FIG. 3 shows a cross-sectional view of the main part of a semiconductor device having I as a gate electrode. In Fig. 3, 1 is a semi-insulating substrate, 2
is an n-type active layer, and an n+ region 3.4 is provided in the source/drain region to reduce series resistance. 5
is a Schottky gate electrode, 6 is a source electrode, and 7 is a drain electrode.

従来、高融点金属薄膜からなるショットキーゲート電極
5においては、硅化タングステン(WSiz)などの高
融点金属化合物や、タングステンCW)などの単体の高
融点金属薄膜全半導体表面に直接堆積したものが用いら
れていた。しかし、高融点金属化合物、例えばW Si
tでは半導体表面との接合部の電気特性の耐熱性は高い
もののその抵抗率が100μΩ・σ以上と高く、高周波
特性における雑音指数の増大をもたらすという欠点があ
った。このためシート抵抗を下げることが必要であるが
、膜厚を厚くすることは加工性が悪くなるなどの製造上
の制約から困難であった。ま友、単体の高融点金属、例
えばWでは抵抗率は10μΩ・G程度と低いものの半導
体基板表面との間の付着力、電気特性の耐熱性に問題を
有していた。
Conventionally, in the Schottky gate electrode 5 made of a high melting point metal thin film, a high melting point metal compound such as tungsten silicide (WSiz) or a single high melting point metal thin film such as tungsten CW) deposited directly on the entire semiconductor surface has been used. It was getting worse. However, high melting point metal compounds, such as WSi
At t, the heat resistance of the electrical characteristics of the junction with the semiconductor surface is high, but the resistivity is as high as 100 μΩ·σ or more, which has the disadvantage of causing an increase in the noise figure in the high frequency characteristics. For this reason, it is necessary to lower the sheet resistance, but increasing the film thickness has been difficult due to manufacturing constraints such as poor processability. Although a single high-melting point metal such as W has a low resistivity of about 10 μΩ·G, it has problems with adhesion to the surface of a semiconductor substrate and heat resistance of electrical properties.

(問題点全解決する友めの手段) 本発明の目的は、これらの欠点を解決した低抵抗率かつ
耐熱性の高い高融点金属薄膜からなるゲート電極を有す
る半導体装置及びその製造方法を提供することにある。
(Friendly Means to Solve All Problems) An object of the present invention is to provide a semiconductor device having a gate electrode made of a high melting point metal thin film with low resistivity and high heat resistance, which solves these drawbacks, and a method for manufacturing the same. There is a particular thing.

本発明に係る半導体装置は、半導体基板と高融点金属薄
膜の間に、前記半導体基板および前記高融点金属薄膜の
いずれよりも酸素との結合力の大きな物質を含む極めて
薄い層を有することを最も主要な特徴とする。
Most preferably, the semiconductor device according to the present invention has an extremely thin layer between the semiconductor substrate and the high melting point metal thin film that contains a substance having a stronger bonding force with oxygen than either the semiconductor substrate or the high melting point metal thin film. Main characteristics.

半導体基板、例えば砒化ガリウム(GaAs )基板お
よび高融点金属薄膜、例えばタングステン(W)とのい
ずれよりも酸素との結合力の大きな物質であるかどうか
は、酸化物生成エネルギーから判断することができる。
Whether the substance has a stronger bonding force with oxygen than either a semiconductor substrate, such as a gallium arsenide (GaAs) substrate, or a high melting point metal thin film, such as tungsten (W), can be determined from the oxide formation energy. .

例えば、Ga。For example, Ga.

As + W、 Siの酸化物生成エネルギーは、酸素
原子1モル当シそれぞれ約−80Kcal 、 −46
Kcal 。
The oxide formation energies of As + W and Si are approximately -80 Kcal and -46 per mole of oxygen atoms, respectively.
Kcal.

−60Kcal 、 −100Kcalであり、Siが
一香酸素と結合しやすいことがわかる。
-60 Kcal and -100 Kcal, which shows that Si easily combines with Ikko oxygen.

本発明による電極膜の作用を従来技術による高融点化合
物、例えば金属シリサイドを用い元ものと、抵抗性及び
耐熱性の点より比較して説明する。
The function of the electrode film according to the present invention will be explained in comparison with that of a conventional electrode film using a high melting point compound such as metal silicide in terms of resistance and heat resistance.

寸ず抵抗性については、本発明においては、はさみ込む
中間層の厚さが100 Å以下と極めて薄い几め、全膜
厚(200A )に比べて、この部分の抵抗は無視でき
るため、結局単体の高融点金属と同等の低抵抗がえられ
るものである。
In terms of resistance, in the present invention, the thickness of the sandwiched intermediate layer is extremely thin, less than 100 Å, and the resistance of this part can be ignored compared to the total film thickness (200 Å). It provides low resistance equivalent to that of high melting point metals.

また耐熱性については、両者は同等であるので、結局抵
抗性及び耐熱性の画点について、本発明は単体の高融点
化合物を用いたものと同等である。
In addition, as for heat resistance, both are equivalent, so in terms of resistance and heat resistance, the present invention is equivalent to using a single high melting point compound.

(゛実施例) 第1図は本発明の一実施例でろる砒化ガリウム(GaA
s ) を界効果トランジスタを説明する図であって、
図において1は半絶縁性基板、2はn形能動層、3,4
は?領域、5は映厚約200OAのタングステン(W)
薄膜、5′はシリコン(Si)を主成分とする極めて薄
い層、6はソース電極、7はドレイン電極である。
(Example) Figure 1 shows an example of the present invention.
s) is a diagram illustrating a field effect transistor,
In the figure, 1 is a semi-insulating substrate, 2 is an n-type active layer, 3, 4
teeth? Area 5 is tungsten (W) with a film thickness of approximately 200OA.
The thin film 5' is an extremely thin layer mainly composed of silicon (Si), 6 is a source electrode, and 7 is a drain electrode.

この構造を実現するkめには、第1図の実施例では次6
ようにすればよい。半絶縁性基板1の1主面上に、選択
イオン注入技術を用いて、n形能動層2を形成する。次
に、マグネトロン・スパッタリング法を用いて、St 
+ W f順次堆積する。CF4 + Ot ’t”用
いたドライエツチング技術により電極に加工し、しかる
のちに、熱処理を行なう。その後、金(Au)−ゲルマ
ニウム(Ge)(Get12wt%含む)を約150O
A 、ニッケル(Ni)を約500 ′Aを順次電子ビ
ーム蒸着法を用いて堆積し、リフトオフ法によって電極
に加工したのちに、アルゴン(Ar)気泡中で450℃
In order to realize this structure, in the embodiment of FIG.
Just do it like this. An n-type active layer 2 is formed on one main surface of a semi-insulating substrate 1 using a selective ion implantation technique. Next, using the magnetron sputtering method, St
+ W f sequentially deposited. It is processed into an electrode by dry etching technology using CF4 + Ot 't', and then heat treated. Thereafter, gold (Au)-germanium (Ge) (containing 12 wt% of Get) is etched at about 150O
A, Approximately 500'A of nickel (Ni) was sequentially deposited using the electron beam evaporation method, processed into an electrode by the lift-off method, and then heated at 450°C in an argon (Ar) bubble.
.

1分間の熱処理を行ない、ソース電極6.ドレイン電極
7とする。このように、本発明の構造は公知の工程によ
り、容易に形成可能である。
Heat treatment is performed for 1 minute, and the source electrode 6. It is assumed to be a drain electrode 7. As described above, the structure of the present invention can be easily formed using known processes.

Si層の厚きを0−5OAの範囲で変化させた場合の、
1ooo℃、数秒間のランプアニール法による熱処理後
の前記実施例のショットキー障壁高さ、理想因子を第2
図に示す。ショットキー障壁高さ、理想因子はショット
キーバリヤダイオードの電流−電圧特性から公知の方法
によシ求められる。しかして理想因子は1に近いほど理
想的なショットキー接合であることを示す。ここに第2
図に示すように、15A程度のSi層をはさんだ場合に
は、/ヨツトキー接合特性の向上が見られる。ま友、S
i層の厚さは、100 A k越えるとwHとGaAs
基板との界面にWシリサイド層が生成され、体積収縮を
生じて膜の剥離の原因となる。また、2A以下と薄すぎ
ても、Si層の十分な効果を得ることはできない。Si
層の厚さが2〃・ら100 Aの範囲内であれば、熱処
理によ、9.Si層が酸素やW[1にと反応し化合物を
形成してもさしつかえない。
When the thickness of the Si layer is changed in the range of 0-5OA,
The Schottky barrier height and ideality factor of the above example after heat treatment by lamp annealing for several seconds at 100°C were
As shown in the figure. The Schottky barrier height and ideality factor are determined by a known method from the current-voltage characteristics of the Schottky barrier diode. Therefore, the closer the ideality factor is to 1, the more ideal the Schottky junction is. here the second
As shown in the figure, when a Si layer of approximately 15 A is sandwiched, the /Yottky junction characteristics are improved. Mayu, S.
When the thickness of the i layer exceeds 100 A k, wH and GaAs
A W silicide layer is generated at the interface with the substrate, causing volumetric contraction and causing film peeling. Moreover, even if it is too thin, such as 2A or less, sufficient effects of the Si layer cannot be obtained. Si
If the thickness of the layer is within the range of 2〃. There is no problem even if the Si layer reacts with oxygen or W[1 to form a compound.

以上の結果から明らかなように、本発明は従来の技術に
比べて低抵抗かつ高い耐熱性を有するゲート電極が実現
できる。
As is clear from the above results, the present invention can realize a gate electrode having lower resistance and higher heat resistance than conventional techniques.

なお、半導体基板及び高融点金属薄膜のいずれよりも酸
素との結合力の大きな物質よりなる中間層としてVi、
h次の第1表のものが好ましい〇第1表 (発明の効果) 以上説明し几ように、本発明によれば、低抵抗かつ高い
耐熱性を有する高融点金属薄膜を電極に有する半導体装
置を実現することができ。
Note that as an intermediate layer made of a substance that has a stronger bonding force with oxygen than either the semiconductor substrate or the high melting point metal thin film, Vi,
Table 1 (Effects of the Invention) As explained above, according to the present invention, a semiconductor device having an electrode of a refractory metal thin film having low resistance and high heat resistance. can be realized.

高周波特性に優れ友素子が実現できる利点がある。It has the advantage of excellent high frequency characteristics and can be used as a companion element.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明装置の一実施例の断面図、第2図は本発
明の説明に供するSi層厚とショットキー障壁高さ、理
想因子の関係を表わす線図、第3図は従来の高融点金属
薄膜によるゲート電極を有する化合物半導体装置の断面
図を示す01・・・・・・・・・・・・半絶縁性基板2
・・・・・・・・・・・・n型能動層3.4・・・・・
・♂領域 5・・・・・・・・・・・・ショットキーゲート電極5
′・・・・・・・・・・・・シリコンを主成分とする極
めて薄い層6・・・・・・・・・・・・ソース電極7・
・・・・・・・・・・・ドレイン電極第 1 図 第3図 第2図 Si層の(亡(A)
FIG. 1 is a cross-sectional view of one embodiment of the device of the present invention, FIG. 2 is a diagram showing the relationship between Si layer thickness, Schottky barrier height, and ideality factor for explaining the present invention, and FIG. 3 is a diagram of the conventional device. 01 showing a cross-sectional view of a compound semiconductor device having a gate electrode made of a high melting point metal thin film... Semi-insulating substrate 2
・・・・・・・・・・・・N-type active layer 3.4・・・・・・
・Female region 5... Schottky gate electrode 5
′......Extremely thin layer 6 whose main component is silicon...Source electrode 7.
・・・・・・・・・Drain electrode No. 1 Fig. 3 Fig. 2 Si layer (destruction (A)

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の1主面上に高融点金属薄膜を有する
半導体装置において、前記半導体基板と前記高融点金属
薄膜の間に、前記半導体基板および前記高融点金属薄膜
のいずれよりも酸素との結合力の大きな物質からなる厚
さ2〜100Åの中間層を有することを特徴とする半導
体装置。
(1) In a semiconductor device having a high melting point metal thin film on one main surface of a semiconductor substrate, there is a greater amount of oxygen between the semiconductor substrate and the high melting point metal thin film than in either the semiconductor substrate or the high melting point metal thin film. A semiconductor device characterized by having an intermediate layer with a thickness of 2 to 100 angstroms made of a material with a large bonding force.
(2)中間層が、少なくともシリコン(Si)を含む物
質からなることを特徴とする特許請求の範囲第1項記載
の半導体装置。
(2) The semiconductor device according to claim 1, wherein the intermediate layer is made of a material containing at least silicon (Si).
(3)半導体基板の1主面上に、高融点金属薄膜を堆積
する工程を含む半導体装置の製造方法において、前記高
融点金属薄膜を堆積する前に、中間層としてスパッタリ
ング法、蒸着法、気相成長法のいずれかによりシリコン
(Si)を堆積することを特徴とする半導体装置の製造
方法。
(3) In a method for manufacturing a semiconductor device including a step of depositing a high melting point metal thin film on one main surface of a semiconductor substrate, before depositing the high melting point metal thin film, an intermediate layer is formed by sputtering, vapor deposition, or vapor deposition. A method for manufacturing a semiconductor device, comprising depositing silicon (Si) by one of phase growth methods.
JP17124685A 1985-08-05 1985-08-05 Semiconductor device and manufacture thereof Pending JPS6232656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17124685A JPS6232656A (en) 1985-08-05 1985-08-05 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17124685A JPS6232656A (en) 1985-08-05 1985-08-05 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6232656A true JPS6232656A (en) 1987-02-12

Family

ID=15919756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17124685A Pending JPS6232656A (en) 1985-08-05 1985-08-05 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6232656A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0559182A2 (en) * 1992-03-03 1993-09-08 Sumitomo Electric Industries, Limited Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294773A (en) * 1976-02-05 1977-08-09 Sumitomo Electric Ind Ltd Semiconductor element and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5294773A (en) * 1976-02-05 1977-08-09 Sumitomo Electric Ind Ltd Semiconductor element and its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0559182A2 (en) * 1992-03-03 1993-09-08 Sumitomo Electric Industries, Limited Semiconductor device
EP0559182A3 (en) * 1992-03-03 1995-05-10 Sumitomo Electric Industries

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