JPH0439774B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to the structure of a field effect transistor that has sufficient drain breakdown voltage, good characteristics, and is suitable for high output.

(b) Technology background In order to achieve higher speeds and lower power consumption that exceed the limits of silicon (Si) semiconductor devices, which are currently the mainstay of electronics, gallium, which has a much higher electron mobility than silicon, has been developed as a carrier. - Development of semiconductor devices using compound semiconductors such as arsenic (GaAs) is being promoted.

As a transistor using a compound semiconductor,
Field-effect transistors (hereinafter abbreviated as FETs) have been developed first because their manufacturing process is simpler than bipolar transistors.
A Schottky barrier type FET that uses a semi-insulating compound semiconductor as a substrate to reduce stray capacitance.
has become the mainstream.

(c) Prior art and problems Schottky barrier FETs (hereinafter abbreviated as GaAs MESFETs) using GaAs as a semiconductor material have already been put into practical use, for example, for amplification in the microwave band.

Figure 1a is a perspective view showing an example of the structure of a high-power GaAs MESFET, in which 1 is a semi-insulating GaAs substrate;
2 is an n-type GaAs layer. Each electrode is combined in a comb-like shape to increase current capacity, and S
indicates a source electrode, D indicates a drain electrode, and G indicates a gate electrode. Note that 6 is an insulating film, but only a part of it is shown.

Figure 1b is a partial cross-sectional view of a GaAs MES FET.
As in the previous figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type
It shows a GaAs layer, and 3 is a source electrode, 4 is a drain electrode, 5 is a gate electrode, and 6 is a surface protection film.

The source and drain electrodes of GaAs MES FETs such as the one described above are conventionally made of gold-germanium alloy (AuGe) with a thickness of 30 nm in order to form good ohmic contact between the electrodes and the n-type GaAs layer. ] and further coated with gold (Au) to AuGe
After depositing on the film to a thickness of about 300 [μm] and forming the desired pattern, heat treatment is performed at a temperature of 450 [℃] for about 2 minutes to form As, Ge, Ga,
Alloying is performed by interdiffusion with As.

For the electrode structure that makes ohmic contact with the n-type GaAs layer, nickel (Ni) is added to the AuGe/Au structure.
Or AuGe/Ni/Au with platinum (Pt) film inserted,
Various structures are known, such as an AuGe/Pt/Au structure or using silicon (Si) or tin (Sn) instead of Ge.

The above-mentioned alloying has the effect of doping the surface of an n-type compound semiconductor with Ge, etc., which serves as a donor impurity, at a high concentration to form an n ⁺ type region aligned with the electrode. It is widely used as a manufacturing process. However, the electrode formation region after this alloying is usually a semiconductor.
The GaAs layer is not in a uniform alloy layer state, and as a result, local current concentration and electric field distribution are likely to occur, resulting in a decrease in the withstand voltage of the electrode.

In order to achieve high output in devices such as the GaAs MES FET mentioned above, it is necessary to set the drain voltage high, but conventional alloyed electrode structures often suffer from insufficient drain breakdown voltage. This has occurred and improvement is required.

As a means of improving drain breakdown voltage, methods such as introducing donor impurities at a high concentration in advance into the drain electrode formation region to alleviate electric field concentration are already known, but in compound semiconductors such as GaAs, it is difficult to There are problems such as impurities not being completely activated due to the protective film and other factors, making it impossible to obtain a sufficiently high carrier concentration.

(d) Object of the Invention It is an object of the present invention to address the above-mentioned problems and provide a structure in which the drain breakdown voltage of a GaAs-based field effect transistor is improved with high reliability.

(e) Structure of the Invention The object of the present invention is to provide an indium-gallium-arsenide compound semiconductor layer on a gallium-arsenide compound semiconductor layer including a region where the composition changes continuously, This is achieved by a semiconductor device comprising a field effect transistor comprising a drain electrode in Schottky contact with a compound semiconductor layer.

That is, in the structure of the drain electrode according to the present invention, a Schottky contact structure is used instead of the conventional Ohmic contact electrode structure that involves alloying.
In order to selectively set the barrier potential of this shot key contact to a low value as explained later, the semiconductor layer on which the drain electrode is arranged is made of an indium-gallium-arsenic compound (InxG _a1-x As).
The InxG _a1-x As layer and the GaAs substrate are made of Iny
By connecting in the G _a1-y As (0≦y≦x) region, barriers caused by lattice mismatch and differences in electron affinity are eliminated.

Compared to conventional ohmic contact electrodes that involve alloying, the Schottky contact electrode has a very smooth interface and does not cause local electric field concentration, so its withstand voltage is improved. Further, as for the drain electrode, since the drain end resistance is generated due to the forward potential drop of the shot key contact, the equalization of the electric field within the electrode region is promoted, which is advantageous for improving the withstand voltage.

However, if a drain electrode that contacts the shot key is used, power loss due to the shot key barrier φB cannot be avoided. In shot-key contact with n-type GaAs, which is conventionally performed in gate electrodes, etc., there is a barrier of about 0.9 [eV] for gold (Au) and 0.8 [eV] for aluminum (Al), resulting in large power loss. On the other hand, in the shot-key contact between InxG _a1-x As and metal used in the present invention, the shot-key barrier φB decreases as the In composition ratio X increases. FIG. 2 shows the correlation with the composition ratio X of the Schottky barrier φB between Au and InxG _al-x As.

Suppression of power loss by shot key barrier,
On the other hand, considering that a slight shot key barrier is provided in order to average out the bias in the current density distribution on the drain electrode surface due to the difference in current path length, the shot key barrier height can be adjusted by changing the In composition ratio X. Normally
The characteristics of the FET can be optimized by selectively suppressing it to about 1.0 to 0.4 [eV].

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

FIG. 3a is a sectional view showing an embodiment of the present invention, and FIG. 3b is an energy band diagram on the drain side thereof.

This example uses a semiconductor substrate in which the following half layers are stacked on a semi-insulating GaAs substrate 11 by molecular beam epitaxial growth (MBE) or metal organic pyrolysis vapor deposition (MOCVD). There is. In other words, 12 is, for example, the impurity concentration 1×10 ¹⁷
[cm ^-3 ], n-type GaAs layer with a thickness of about 0.5 [μm], 1
For example, 3 has an impurity concentration of about 5×10 ¹⁷ [cm ^-3 ],
Continuing with the GaAs layer 12, the composition ratio of In gradually increases from X=0 to
= 0.5, n ⁺ type InxG _a1-x As layer, 14 is n ⁺ type In _0.5 Ga _0.5 with the same impurity concentration and continuous composition as layer 13.
The thickness of the As layer is approximately 50 [μm]. Although this layer 14 is not absolutely necessary, its provision improves the stability of the manufacturing process.

The area other than the drain electrode formation area of this semiconductor substrate
The n ⁺ -type InGaAs layers 14 and 13 are removed using a resist mask, for example, with a metalul (CH ₃ OH) solution containing 0.5 to 1% bromine (Br ₂ ) until the GaAs surface is exposed. source electrode 15
A drain electrode 16 is formed using AuGe/Au using conventional techniques on the n-type GaAs layer 12, and then a drain electrode 16, in this example using Au, is formed on the n ⁺ -type In _0.5 Ca _0.5 As layer 14. . The gate electrode 17 is formed using Al in a recess that is selectively etched in the n-type GaAs layer 12 using a conventional technique.

Drain electrode 16 of this embodiment and n ⁺ type In _0.5 Ga _0.5
The barrier height φB of the Schottky contact with the As layer 14 is approximately 0.2 [eV], which is significantly reduced compared to the conventional Schottky contact on n-type GaAs, as seen in Figure 3b. There is. Furthermore n ⁺ type
The energy bands are smoothly connected by the InxG _a1-x As (0≦x≦0.5) layer 13, and no step in potential occurs within the semiconductor substrate.

Although the above explanation is directed to MESFETs in which the gate electrode makes short key contact with the semiconductor substrate, the present invention applies to junction type FETs and insulated gate type FETs.
The same can be applied to FETs.

(g) Effects of the Invention As explained above, according to the present invention, the drain electrode, which requires a high withstand voltage among the electrodes of a field effect transistor, is made into a low-barrier shot-key contact electrode that can be selected arbitrarily, and the potential difference in the semiconductor is generated. By preventing this, it is possible to realize a high-output field effect transistor that has sufficient drain breakdown voltage and good power efficiency.

[Brief explanation of drawings]

Figures 1a and b are perspective views and cross-sectional views of conventional GaAs MES FETs, Figure 2 is a diagram showing an example of the correlation between the InGaAs composition ratio and the Schottky barrier height, and Figure 3a is a diagram of a conventional GaAs MES FET. A cross-sectional view of an embodiment of the invention, and FIG. 3B is an energy band diagram thereof. In the figure, 11 is a semi-insulating GaAs substrate, 12
is an n-type GaAs layer, 13 is an n ⁺ type InxG _a1-x As (0≦x
≦0.5) layer, 14 is an n ⁺ type In _0.5 Ga _0.5 As layer, 15 is a source electrode, 16 is a drain electrode, and 17 is a gate electrode.

Claims (1)

[Claims] 1. An indium-gallium-arsenide compound semiconductor layer is provided on a gallium-arsenide compound semiconductor layer including a region where the composition changes continuously, and a drain electrode is provided in short key contact with the indium-gallium-arsenide compound semiconductor layer. 1. A semiconductor device comprising a field effect transistor.