JP2000340581A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a satisfactory conduction characteristic to a gate electrode by interposing a film, having properties to suppress increase in the electrical resistance between the gate electrode and a compound semiconductor layer. SOLUTION: On a substrate 101, a buffer layer 102, a spacer layer 103, and an electron feeding layer 104 are deposited in the order. In an ohmic electrode forming region of the electron feeding layer 104, a p-type impurity diffused layer 111 is formed, where an oxide film is easy to form. On the impurity diffused layer 111 and the electron feeding layer 104, an insulation film 106 made of silicon oxide is formed. In an ohmic electrode formation region of the insulation film 106, an ohmic electrode 112 which is a gate electrode is formed in an opening which is so formed as to reach the impurity diffused layer 111. Between the ohmic electrode 112 and the impurity diffused layer 111 which is a compound semiconductor layer, a high resistance preventing film 113 is formed so as to suppress the increase in the electrical resistance by the oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (HEMT: High Electron Mo) utilizing electrons having high mobility accumulated at a heterojunction interface.
The present invention relates to a semiconductor device having a feature in a gate electrode structure of a "billness transistor" and a manufacturing method thereof. In particular, the present invention provides a method for forming a gate electrode on an electron supply layer whose surface is susceptible to oxidation or an impurity diffusion region provided on the electron supply layer. The present invention is characterized by an ohmic electrode free from an increase or variation in electric resistance due to an oxide film formed on the surface of the region, and a method for forming the ohmic electrode.

In the present invention, AlGaAs is:
To be precise, it is a compound semiconductor represented by Al _x Ga _{1 -x} As (x represents a positive number less than 1), but may be simply referred to as AlGaAs below. Further, the first forbidden band compound semiconductor refers to a compound semiconductor having a predetermined forbidden band width, and the second forbidden band compound semiconductor refers to a compound semiconductor having a forbidden band width different from the first forbidden band compound semiconductor. . Further, the first conductivity type impurity is n-type or p-type.
Type impurity, and the second conductivity type impurity refers to a conductivity type impurity opposite to the first conductivity type impurity.

[0003]

2. Description of the Related Art On a semi-insulating GaAs substrate, a two-dimensional electron gas layer made of a semiconductor having a narrow band gap is provided, and an electron supply layer made of a semiconductor having a wide band gap is further provided thereon. A field effect transistor (HEMT: High Electron Mo) utilizing electrons having high mobility accumulated at the heterojunction interface and utilizing the electrons.
Biliability Transistor) is known.

FIG. 10 shows a general sectional structure of this HEMT (junction field effect transistor). The transistor includes a buffer layer 302 made of undoped GaAs on a semi-insulating GaAs substrate 301, a spacer layer 303 made of undoped AlGaAs on the buffer layer 302, and an n-type material such as Si on the spacer layer 303. An electron supply layer 304 made of AlGaAs doped with an impurity, a p-type impurity diffusion region 311 in the ohmic electrode formation region of the electron supply layer 304, and a silicon nitride layer on the impurity diffusion region 311 and the electron supply layer 304. And an ohmic electrode 312 as a gate electrode in an opening provided to reach the impurity diffusion region 311 in the ohmic electrode formation region of the insulating film 306.

Further, source / drain regions 308 serving as input / output terminals are formed in the electron supply layer 304 on both sides of the ohmic electrode 312, and ohmic contacts 309 are formed on those regions.

At the interface between the buffer layer 302 and the spacer layer 303, the spacer layer 303 is depleted, and electrons are accumulated at the interface of the buffer layer 302 with a thickness of about 100 °, that is, a so-called two-dimensional electron gas layer (channel layer).
305 are formed.

[0007] The two-dimensional electron gas layer 305 is formed on the undoped GaAs layer 302, and is not scattered by impurities when electrons travel, thereby increasing electron mobility. Therefore, high-speed and high-frequency operation can be performed as compared with other field effect transistors.

In this transistor, when the voltage Vg applied to the gate is changed, the concentration of the two-dimensional electron gas in the lower layer is increased or decreased, and as a result, the drain current _ID flowing between the source and the drain is changed. GaAsF
It exhibits transistor characteristics similar to ET.

[0009]

In the HEMT, the p-type impurity diffusion layer 311 and the p-type impurity diffusion
On 11, there is provided an ohmic electrode 312 serving as a gate electrode in which Ti, Pt, and Au are stacked in this order. The p-type impurity diffusion layer 311 below the ohmic electrode 312 is made of AlGaAs doped with a p-type impurity such as Zn.
It is formed of an s semiconductor.

By the way, compound semiconductors containing aluminum generally have a property of being easily oxidized and thus easily deteriorated in the air (for example, “Compound Semiconductor Device” p73, edited by Tetsuo Imai et al., Industrial Research Institute, 1984.
See year, etc. ). Since the AlGaAs semiconductor also contains aluminum as a constituent component, when the surface of the impurity diffusion region formed by diffusing impurities into the AlGaAs semiconductor layer is exposed to air, the surface is oxidized to form a natural oxide film. .

Generally, an oxide film has an insulating property. In addition, the thickness of the formed natural oxide film varies due to a difference in manufacturing conditions and the like. Therefore, when a gate electrode is formed on an impurity diffusion region having a native oxide film formed on the surface, the electric resistance between the impurity diffusion region and the gate electrode may be increased or the resistance value may be varied. become. In addition, it adversely affects the transistor characteristics of the HEMT, which is characterized by high-speed and high-frequency operation.

In order to solve such a problem, the present invention has a so-called gate electrode having a very small increase in electric resistance between a gate electrode and an impurity diffusion layer below the gate electrode and having good conduction characteristics. An object of the present invention is to provide a semiconductor device having a heterojunction type field effect transistor and a method for manufacturing the same.

[0013]

Means for Solving the Problems The inventors of the present invention have conducted intensive studies to achieve the above object, and as a result, have found that a semiconductor device having a field effect transistor formed on a substrate in which compound semiconductors having different forbidden band widths are heterojunctioned In forming a gate electrode on a compound semiconductor layer on which an oxide film is easily formed on the surface, the electric resistance of the oxide generated between the gate electrode and the compound semiconductor layer on which an oxide film is easily formed is reduced. It has been found that a gate electrode having good conduction characteristics can be formed by interposing a film having a property of suppressing the rise, and the present invention has been completed.

According to the present invention, first, a substrate, a buffer layer formed of a first bandgap compound semiconductor formed on the substrate, and a first conductive type impurity formed on the buffer layer and containing a first conductivity type impurity are formed. (2) an electron supply layer made of a forbidden semiconductor; a two-dimensional electron gas layer formed on the electron supply layer side of the buffer layer; and a high resistance containing oxygen atoms on the electron supply layer at least from the impurity diffusion layer side. Provided is a semiconductor device having a gate electrode formed by stacking an oxidation prevention layer and a metal layer.

In the semiconductor device of the present invention, the substrate is preferably a compound semiconductor substrate. The compound semiconductor substrate generally means a semiconductor composed of two or more elements, but the kind of the compound semiconductor is not particularly limited.

As such a compound semiconductor substrate, for example,
Compound semiconductors such as GaAs and InGaAs are exemplified. In the present invention, it is more preferable to use a semi-insulating GaAs substrate from the viewpoint of availability, versatility, handleability, and the like.

The semiconductor device of the present invention uses a substrate formed by heterojunction of a first bandgap compound semiconductor and a second bandgap semiconductor having different bandgap (Eg) values. In the present invention, it is preferable that the forbidden band width of the first forbidden band semiconductor is smaller than the forbidden band width of the second forbidden band compound semiconductor.

In the semiconductor device of the present invention, the buffer layer is preferably an undoped compound semiconductor layer,
More preferably, it is an undoped GaAs semiconductor layer.

Further, in the semiconductor device according to the present invention, the second device is provided between the two-dimensional electron gas layer and the electron supply layer.
It is preferable to further include a spacer layer made of a forbidden band semiconductor.

In this case, the spacer layer comprises:
An undoped compound semiconductor layer containing aluminum as a component is preferable, and undoped Al _1-x Ga _x A
s (where x represents a positive number less than 1) is more preferably a semiconductor layer.

[0021] The electron supply layer is preferably a compound semiconductor layer containing aluminum containing a first conductivity type impurity as an element.
More preferably, it is a _1-x Ga _x As (where x is a positive number less than 1) semiconductor layer.

Further, it is preferable that the electron supply layer has an impurity diffusion region containing a second conductivity type impurity formed in the gate electrode formation region.

The impurity diffusion region is preferably made of a compound semiconductor layer containing aluminum as a constituent element containing an impurity of the second conductivity type, and Al _1-x Ga _x As containing an impurity of the second conductivity type (where , X represents a positive number less than 1.) More preferably, it is made of a semiconductor.

The high resistance preventing layer containing oxygen atoms is formed on the side of the electron supply layer of the gate electrode of the semiconductor device of the present invention, and is formed by an oxide film formed on the surface of the electron supply layer. It is made of an electrode material that suppresses a rise in resistance. As such an electrode material, for example, titanium nitride oxide (TiON) can be preferably used.

The gate electrode is preferably an ohmic electrode formed on the impurity diffusion region, and more preferably, titanium nitride oxide (TiON) and another metal are sequentially laminated from the impurity diffusion region side. Ohmic electrode.

In this case, the gate electrode is formed of titanium nitride oxide (TiO 2) from the side of the impurity diffusion region.
N), titanium (Ti), platinum (Pt) and gold (A
It is more preferable that u) is an ohmic electrode formed by sequentially laminating u).

According to the present invention, there is also provided, secondly, a step of forming a buffer layer made of a first forbidden band semiconductor on a compound semiconductor substrate, and a step of forming a second forbidden layer containing a first conductivity type impurity on the buffer layer. Forming an electron supply layer made of a band semiconductor, forming a second conductivity type impurity diffusion region in a region of the electron supply layer where an ohmic electrode is formed, and forming an impurity diffusion region on the electron supply layer and the impurity diffusion layer. A step of forming an insulating film, a step of forming an opening reaching the impurity diffusion region in a region of the insulating film on the impurity diffusion layer, and an electric resistance of an oxide film on the surface of the impurity diffusion layer in the opening. Forming a gate electrode by laminating an electrode material for suppressing the rise and an electrode material; and providing a method for manufacturing a semiconductor device.

The method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device according to the first present invention.

In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the substrate is a compound semiconductor substrate. As such a compound semiconductor substrate, for example, Ga
Compound semiconductors such as As and InGaAs are exemplified. In the present invention, it is more preferable to use a semi-insulating GaAs substrate from the viewpoint of availability, versatility, handleability, and the like.

The first forbidden compound semiconductor and the second forbidden compound semiconductor used in the present invention have different forbidden bandwidths, and the forbidden bandwidth of the first forbidden compound semiconductor is the second forbidden band. It is preferable that the band gap is smaller than the band gap of the compound semiconductor.

Preferably, the step of forming the buffer layer made of the first forbidden band semiconductor includes the step of forming an undoped GaAs layer on the compound semiconductor substrate on the compound semiconductor substrate.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a spacer layer made of a second bandgap semiconductor is further provided between the step of forming the buffer layer and the step of forming the electron supply layer. It is preferred to have.

In the step of forming the spacer layer, preferably, a compound semiconductor layer containing undoped aluminum as a constituent component on the undoped GaAs layer, more preferably, undoped Al on the undoped GaAs layer.
Forming a _1-x Ga _x As (where x represents a positive number less than 1) semiconductor layer;

In the step of forming the electron supply layer, preferably, a compound semiconductor layer containing aluminum containing a first conductivity type impurity as a constituent component, more preferably, a first conductive layer is formed on the buffer layer or the spacer layer. Forming an Al _1-x Ga _x As (where x represents a positive number less than 1) semiconductor layer containing a type impurity.

In the step of forming the impurity diffusion region, the second conductivity type impurity is ion-implanted into a region of the electron supply layer where the gate electrode is to be formed. It is preferable to include a step of forming a two-conductivity-type impurity diffusion region.

The step of forming the gate electrode includes the step of depositing an electrode material for suppressing an increase in electric resistance due to an oxide film on the surface of the impurity diffusion region in the opening, and the step of depositing another electrode material on the deposited electrode material. It is preferable to have a step of vapor-depositing the metal.

In the step of forming the gate electrode, titanium nitride oxide (TiON), titanium (Ti), platinum (Pt), and gold (Au) are sequentially laminated in the opening, and then alloyed. More preferably, the method includes a step of forming an ohmic electrode.

In the method of manufacturing a semiconductor device according to the present invention, a gate electrode of the electron supply layer is formed between the step of forming the electron supply layer and the step of forming an insulating film on the electron supply layer. It is preferable that the method further includes a step of forming a second conductivity type impurity diffusion region in the region.

In this case, the step of forming the opening is performed in a region of the insulating film where a gate electrode is to be formed.
More preferably, the method further includes a step of forming an opening reaching the impurity diffusion region of the electron supply layer.

The step of forming the gate electrode includes the step of depositing an electrode material for suppressing an increase in electric resistance due to an oxide film on the surface of the impurity diffusion region in the opening, and the step of depositing another electrode material on the deposited electrode material. It is preferable to include a step of forming an ohmic electrode by vapor-depositing the metal and alloying it.

In the step of forming the gate electrode, titanium nitride oxide (TiON), titanium (Ti), platinum (Pt), and gold (Au) are sequentially laminated in the opening, and then alloyed. More preferably, the method includes a step of forming an ohmic electrode.

The gate electrode of the semiconductor device of the present invention may be an ohmic electrode or a Schottky barrier type electrode.

The semiconductor device of the present invention has a field effect transistor formed on a substrate obtained by heterojunction of semiconductor layers having different bandgap (Eg) values on a supporting substrate. When a gate electrode is formed on a layer (an electron supply layer or an impurity diffusion region) made of a compound semiconductor material which is liable to be formed, the resistance including oxygen atoms is increased between the electron supply layer or the impurity diffusion region and the gate electrode. It is characterized in that a prevention layer is interposed.

In the semiconductor device of the present invention, since the high resistance preventing layer containing oxygen atoms is provided at the boundary between the gate electrode and the electron supply layer (or impurity diffusion region) thereunder, the electron supply layer (or The oxide film formed on the surface of the impurity diffusion region) causes an increase in the electrical resistance between the electron supply layer (or the impurity diffusion region) and the gate electrode, or variations in the electrical resistance due to variations in the thickness of the oxide film. It is a high quality and highly reliable semiconductor device without any.

The method of manufacturing a semiconductor device according to the present invention
This is a method for manufacturing the semiconductor device of the present invention. According to the method of manufacturing a semiconductor device of the present invention, when forming a gate electrode made of a laminate (or metal alloy) of a plurality of metals,
The gate electrode may be formed by continuously and additionally stacking a higher resistance prevention layer containing an oxygen atom as compared with the related art.

Therefore, according to the method for manufacturing a semiconductor device of the present invention, the same manufacturing apparatus as that of the conventional method is used as it is, without increasing the number of steps, and without significantly changing the manufacturing process. The semiconductor device of the present invention can be manufactured.

[0047]

Next, embodiments of the present invention will be described with reference to the drawings. The following is merely an embodiment of the present invention, and the types, thicknesses and formation conditions of the substrate, buffer layer, spacer layer, and electron supply layer, and n-type are provided without departing from the gist of the present invention. The kind of the impurity and the p-type impurity, the doping condition, the material of the ohmic contact and the gate electrode, and the like can be appropriately selected.

First Embodiment A first embodiment of the present invention relates to a semiconductor device H of the present invention.
EMT (junction field effect transistor type). FIG. 1 is a structural cross-sectional view of the HEMT of this embodiment.
This HEMT is a substrate 1 such as a semi-insulating gallium arsenide substrate.
Undoped (does not contain impurities) GaAs
Buffer layer 102 composed of
On top, a spacer layer 1 made of undoped AlGaAs
03 and n such as Si or Ge on the spacer layer 103.
An electron supply layer 104 made of AlGaAs doped with a p-type impurity, and a p-type impurity diffusion layer 111 doped with a p-type impurity such as Zn in an ohmic electrode formation region of the electron supply layer 104.

Further, an insulating film 106 made of silicon nitride or silicon oxide is provided on the impurity diffusion layer 111 and the electron supply layer 104, and an ohmic electrode formation region of the insulating film 106 is provided so as to reach the impurity diffusion layer 111. The opening has an ohmic electrode 112 as a gate electrode.

In the HEMT, at the interface between the buffer layer 102 containing no impurities and the spacer layer 103, the spacer layer 103 side is depleted, and electrons accumulate at the interface with a thickness of about 10 nm on the buffer layer 102 side. It has a structure in which a three-dimensional electron gas layer (channel layer) 105 is formed.

Further, source / drain regions 108 are formed in the electron supply layer 104 on both sides of the ohmic electrode 112, and an ohmic contact 109 for making an ohmic contact with the two-dimensional electron gas layer 105 is formed on those regions. Have.

In this transistor, when the voltage Vg applied to the gate is changed, the concentration of the two-dimensional electron gas in the lower layer is increased or decreased. As a result, the drain current _ID flowing between the source and the drain is changed. GaAsF
It exhibits transistor characteristics similar to ET and operates as a field effect transistor.

Further, since the two-dimensional electron gas layer 105 is formed on the undoped GaAs layer, it is not scattered by impurities when electrons travel. Accordingly, electron mobility is increased, and high-speed and high-frequency operation can be performed as compared with other types of field-effect transistors.

Although the HEMT is a junction field effect transistor, in manufacturing a junction transistor, the impurity diffusion layer is an electron supply layer containing an impurity of the opposite conductivity type to the impurity doped in the electron supply layer. It is formed of the same compound semiconductor as above, for example, a compound semiconductor containing aluminum as a constituent component such as AlGaAs.

On the impurity diffusion layer 111, Ti (11
4) When forming an ohmic electrode made of a laminate of Pt (115) and Au (116), the impurity diffusion layer 11
When a natural oxide film is formed on one surface, the electrical resistance between the impurity diffusion layer and the ohmic electrode may increase or vary due to the influence of the oxide film.

The HEMT according to the present embodiment uses the impurity diffusion layer 1
A structure in which a high resistance prevention film 113 such as titanium nitride oxide (TiON) and another metal layer made of a laminate of Ti (114), Pt (115) and Au (116) and the like are laminated on 11 Ohmic electrode. The resistance increasing prevention layer containing oxygen atoms has a function of suppressing an increase in electric resistance due to an oxide film formed on the surface of the impurity diffusion layer.

Therefore, the semiconductor device according to the present embodiment has high reliability and high reliability without the electric resistance between the impurity diffusion layer and the ohmic electrode being increased or uneven due to the natural oxide film on the surface of the impurity diffusion layer 111. It is a quality semiconductor device.

Second Embodiment A second embodiment of the present invention relates to a semiconductor device H of the present invention.
EMT (Schottky barrier type field effect transistor type). FIG. 2 is a structural cross-sectional view of the HEMT of the present embodiment.

This HEMT has substantially the same layer structure as that of the first embodiment, except that the gate electrode 212 is of a Schottky barrier type. The gate electrode has a Schottky barrier between the gate metal and the semiconductor, and has a rectifying property in which electrons are prevented from flowing from the metal to the semiconductor.

That is, the HEMT of the present embodiment comprises a buffer layer 20 made of undoped (does not contain impurities) GaAs on a substrate 201 such as a semi-insulating gallium arsenide substrate.
2 and undoped AlGa on the buffer layer 202.
A spacer layer 203 made of As and the spacer layer 2
An electron supply layer 204 made of AlGaAs doped with an n-type impurity such as Si or Ge; an insulating film 206 made of silicon nitride or silicon oxide; In the gate electrode formation area,
It has a Schottky barrier type gate electrode 212.

Further, source / drain regions 208 are formed in the electron supply layer 204 on both sides of the gate electrode 212, and an ohmic contact 209 for making an ohmic contact with the two-dimensional electron gas layer is formed on those regions.
have.

This transistor has a Schottky barrier type gate electrode, and by changing the voltage Vg applied to the gate to control the electron density of the electron supply layer below the gate electrode, the lower two-dimensional electron The concentration of the gas can be increased or decreased. As a result, the drain current _ID flowing between the source and the drain changes, so that transistor characteristics similar to those of a MOS transistor or a GaAs FET are exhibited, and the device operates as a field effect transistor.

Since the two-dimensional electron gas layer 105 is formed on an undoped GaAs layer, it does not suffer from scattering due to impurities when electrons travel. Therefore, electron mobility is increased, and high-speed and high-frequency operation can be performed as compared with other types of field-effect transistors.

Since the gate electrode of the HEMT of this embodiment is of a Schottky barrier type,
Even if the gate electrode is of the Schottky barrier type, the electron supply layer 204 is not formed.
Is made of a compound semiconductor, such as AlGaAs, which is easily oxidized in the air, so that a natural oxide film is formed on the surface thereof, and the electric resistance between the electrode and the electron supply layer may increase or the electric resistance may vary. is there.

In the semiconductor device of the present embodiment, the gate electrode is connected to the high resistance preventing layer 213 from the electron supply layer side 204.
And other metal layers are laminated, the oxide film formed on the surface of the electron supply layer increases the electrical resistance between the electrode and the electron supply layer, or changes in the thickness of the oxide film. As a result, the semiconductor device has high reliability and high quality without causing variation in electric resistance.

Third Embodiment This embodiment is an example of manufacturing the semiconductor device of the first embodiment. Hereinafter, a method of manufacturing the HEMT shown in FIG. 1 will be described with reference to the drawings.

First, a semi-insulating gallium arsenide substrate 101 having a specific resistance of about 10 ⁶ to 10 ⁸ Ω · cm is prepared. The semi-insulating gallium arsenide substrate 101 can be manufactured and obtained by a known method such as a horizontal Bridgman method or a pulling method.

Next, as shown in FIG. 3A, an undoped GaAs layer (buffer layer) 102, an undoped Al
A GaAs layer (spacer layer) 103 and an AlGaAs layer (electron supply layer) 104 containing an n-type impurity are sequentially stacked.

The undoped GaAs layer 102 has a thickness of 0.1 mm.
It is about 2 to 0.3 μm, and can be formed by, for example, a method using liquid phase epitaxy, a method using gas phase epitaxy, a method using molecular beam epitaxy, or the like.

The spacer layer 103 is made of undoped AlG
It is made of aAs and has a thickness of about 1 to 2 nm. This can be formed by, for example, a method using liquid phase epitaxy, a method using gas phase epitaxy, a method using molecular beam epitaxy, or the like.

Although the spacer layer 103 is not always necessary in view of the operation principle of the HEMT, the potential of the impurity in the upper electron supply layer 104 is reduced by the GaAs layer 10.
2 is provided to prevent a decrease in the mobility of electrons in the two-dimensional electron gas layer 105 due to seepage.

The electron supply layer 104 has a thickness of 0.1 to 0.2.
μm, and in fact, Al _x Ga _{1 -x} As (x
Represents a positive number less than 1. Usually, x is about 0.3. ). The electron supply layer 104 uses a compound of an element of Group IV or Group VI of the Periodic Table such as Si, Ge, or Se as an n-type impurity, for example, a method by liquid phase epitaxy, a method by vapor phase epitaxy, It can be formed by an epitaxy method or the like.
The n-type impurity concentration in the electron supply layer 104 is usually 1 × 1
It is about 0 ^{18 to} 2 × 10 ¹⁸ / cm ³ .

In the present embodiment, the buffer layer 20
2 is formed of a GaAs semiconductor, and the spacer layer 203 and the electron supply layer 204 are formed of an AlGaAs semiconductor. This is because, when the buffer layer 202 is heterojuncted with the spacer layer 203 and the electron supply layer 204, it is necessary to form an epitaxial layer having the same lattice constant as the compound semiconductor forming the buffer layer. As another example, when an InGaAs semiconductor substrate is used, In
An example using an AlAs semiconductor is given.

Next, as shown in FIG.
The active region is electrically separated by etching. In this case, instead of the mesa etching, the active region can be electrically separated by implanting O ⁺ ions into the region to be electrically separated.

Thereafter, as shown in FIG. 3C, an insulating film 106 is formed on the entire surface. As the insulating film 106, a silicon oxide or silicon nitride film can be given. These insulating films are formed, for example, by CVD (Chemical V).
(a deposition) method.

Next, as shown in FIG. 4D, a resist pattern 107 for forming ohmic on-tact (source / drain) is formed on the insulating film 106, and an ohmic contact formation region of the insulating film 106 is formed. An opening A is formed by opening by etching.

Next, as shown in FIG. 4E, Zn. A p-type impurity such as Mg (Group II element of the periodic table) is implanted by, for example, an ion implantation method to form the ohmic region 108.

Next, as shown in FIG. 5F, as an ohmic contact material, for example, Au, G
e and Ni are sequentially deposited. Next, after the resist pattern is removed, alloying is performed, thereby forming FIG.
As shown in FIG. 5, an ohmic contact (source / drain) 109 for forming an ohmic contact with a two-dimensional electron channel is formed (a so-called lift-off method).

In the drawings after FIG. 5 (f),
Detailed illustration of a laminated body composed of three layers of Au, Ge and Ni is omitted from the substrate side for convenience, and is shown as 109 'in total. In addition, alloying can be performed by continuously depositing Au, Ge, and Ni, and then performing a heat treatment at about 490 to 540 ° C.

In this step, an ohmic contact is formed on ohmic region 108 made of AlGaAs containing a p-type impurity. In this case, since the surface of the ohmic region 108 is easily susceptible to natural oxidation, a high resistance preventing film is interposed at the interface between the ohmic region 108 and the ohmic contact 109 for the same reason as when a gate electrode described later is formed. You can also.

Next, as shown in FIG. 6H, a resist pattern 110 for forming a gate electrode is formed and formed, and the insulating film 106 in the gate electrode forming region is etched to form an opening B. Form.

Thereafter, as shown in FIG. 6I, a p-type impurity such as Zn or Mg is implanted into the electron supply layer 104 below the opening B by, for example, an ion implantation method.
A p-type impurity region 111 is formed.

In this case, as shown in FIG. 7, the insulating film 106 and the electron supply layer 104 are etched to a predetermined depth to form an opening C, into which an opening C is formed.
For example, the p-type impurity diffusion region 111 made of AlGaAs containing a p-type impurity can be formed by a method using liquid phase epitaxy, a method using gas phase epitaxy, a method using molecular beam epitaxy, or the like.

Next, as shown in FIG. 8J, the resist pattern 110 and the p-type impurity diffusion region 111 are
The electrode materials TiON, Ti, Pt and Au are sequentially deposited. After that, the resist is removed to leave the electrode material 112 ′ only on the p-type impurity diffusion layer 119.
The ohmic electrode 112 serving as a gate electrode can be formed by alloying by performing heat treatment.

The TiON layer 113 is made of, for example, O ₂ and N
It can be formed by a sputtering method using Ti as a target under _two atmospheres. In FIG. 8, a detailed illustration of a laminate made of TiON, Ti, Pt, and Au is omitted for convenience, and these are collectively referred to as 112 ′,
It is shown as 112.

This gate electrode is formed in p-type impurity diffusion region 1
It is characteristic that a TiON layer 113 is provided between the TiN layer 19 and the Ti layer 114. The TiON layer 113 serves to prevent the electric resistance between the p-type impurity diffusion region 119 and the gate electrode 112 from increasing. TiON and p
Some action acts on the native oxide formed on the surface of the impurity diffusion layer 119, and the native oxide is taken into the TiON layer, so that the same electrical resistance value as that without the oxide film is obtained. It is thought that it will have.

The thickness of the natural oxide film formed on the surface of the p-type impurity diffusion region 111 varies due to slight differences in manufacturing conditions. The electric resistance between the impurity diffusion region 111 and the gate electrode 112 varies. According to the present embodiment, by interposing the TiON layer on the oxide film, the electric resistance between the p-type impurity diffusion region 111 and the gate electrode 112 for each lot can be made uniform.

In this embodiment, the gate electrode 112 having the same gate length as the width (the horizontal length in the drawing) of the p-type impurity diffusion region 111 is formed. As shown in the figure, an electrode having a predetermined length and height can be formed, for example, a gate electrode longer than the width of the p-type impurity diffusion region 111 can be formed. Further, in the present embodiment, an example in which the gate electrode is formed by a so-called lift-off method is described. However, after the electrode material is continuously deposited, the gate electrode may be processed by using a photoresist processing technique. it can.

Thereafter, although not shown, a wiring layer is formed on the ohmic contact 109 and an interlayer insulating film or the like is formed on the entire surface to manufacture an HMET similar to that shown in FIG. Can be.

Fourth Embodiment This embodiment is an example of manufacturing the semiconductor device of the second embodiment. Hereinafter, a method of manufacturing the HEMT shown in FIG. 2 will be described with reference to the drawings. First, a structure similar to that shown in FIG. 6H is obtained through the same steps as in the third embodiment.

Next, as shown in FIG. 9A, after forming and forming a resist pattern 210 for forming a gate electrode, TiON, Ti, Pt and Au are deposited on the electron supply layer 204 and the resist pattern 212. Continuously. These metal layers can be formed by a known vapor deposition method or the like. In FIG. 9, detailed illustration of a gate electrode layer composed of four layers of TiON, Ti, Pt and Au is omitted, and is illustrated as a gate electrode layer 212.

As the electrode material of the metal layer other than the high resistance preventing layer containing oxygen atoms of the Schottky electrode, Al, Cr
-Pt-Au, Ti-Pt-Au, Pt, Mo, W, T
_{iW, WSi x, WAl, WN} , Si-Ge-B, Ta
Si, TaWSi or the like can be used.

Thereafter, as shown in FIG. 9B, by removing the resist pattern 210, the electron supply layer 2 is removed.
The gate electrode 212 is formed while leaving the gate electrode layer only on the substrate 04. This gate electrode is not alloyed and is a Schottky barrier type gate electrode.

Thereafter, although not shown, a wiring layer is formed on the ohmic contact 109, and an interlayer insulating film and the like are formed on the entire surface to manufacture an HMET similar to that shown in FIG. Can be.

The gate electrode of the HEMT of this embodiment is also
TiON (213), Ti (214), Pt (215)
And a layered structure of Au (216), and a TiON layer 21 is formed on a boundary surface between the electron supply layer 204 and the gate electrode 212.
3 is characteristic.

The TiON layer 213 plays a role in preventing the electric resistance between the electron supply layer 204 and the gate electrode 212 from increasing. In this embodiment, the electrode material is not alloyed, but some action acts between the third TiON and the oxide formed on the surface of the electron supply layer 204,
It is considered that the electric resistance value is the same as the state without the oxide film.

Further, since the thickness of the oxide film formed on the surface of the electron supply layer 204 varies due to slight differences in the manufacturing conditions, the thickness of the oxide film formed on the surface of the electron supply layer 204 varies depending on the thickness of the oxide film. The electric resistance between the gate electrodes 212 varies. According to the present embodiment, T is formed on the oxide film.
By interposing the iON layer, the electric resistance between the electron supply layer 204 and the gate electrode 212 for each lot can be made uniform.

[0098]

As described above, the semiconductor device of the present invention has a high resistance preventing layer containing oxygen atoms at the boundary between the gate electrode and the electron supply layer (or impurity diffusion region) thereunder. Therefore, due to the oxide film formed on the surface of the electron supply layer (or the impurity diffusion region), the electric resistance between the electron supply layer (or the impurity diffusion region) and the gate electrode increases, and the thickness of the oxide film varies. This is a high-quality and highly-reliable semiconductor device that does not cause variations in electric resistance due to the semiconductor device.

The method of manufacturing a semiconductor device according to the present invention
This is a method for manufacturing the semiconductor device of the present invention. According to the method of manufacturing a semiconductor device of the present invention, when forming a gate electrode made of a laminate (or metal alloy) of a plurality of metals,
The gate electrode may be formed by successively laminating an extra layer of high resistance containing oxygen atoms as compared with the related art.

Therefore, according to the method for manufacturing a semiconductor device of the present invention, the same manufacturing apparatus as that of the conventional method is used as it is, without increasing the number of steps, without significantly changing the manufacturing process, and improving the yield. The semiconductor device of the present invention can be manufactured.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a semiconductor device (HEMT) of the present invention.

FIG. 2 is a structural sectional view of a semiconductor device (HEMT) of the present invention.

FIG. 3 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a sectional view of a main step in a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a structural sectional view of a conventional semiconductor device (HEMT).

[Explanation of symbols]

101, 201, 301 ... substrate, 102, 202, 30
2 ... buffer layer, 103, 203.303 ... spacer layer, 104, 204, 304 ... electron supply layer, 105,
205, 305: two-dimensional electron gas layer, 106, 206,
306: insulating film, 107, 110: resist pattern,
108: ohmic region, 109: ohmic contact, 109 ': metal layer for ohmic contact, 111,
311: impurity diffusion region, 112, 212, 312: gate electrode, 113, 213: TiO layer, 114, 21
4,314 ... Ti layer, 115,215,315 ... Pt
Layers, 116, 216, 316... Au layers, A, B, C.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/808 (72) Inventor Mitsuhiro Nakamura 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo (72) Inventor Hironori Tsukamoto 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo F-term within Sony Corporation (reference) 4M104 AA05 BB02 BB06 BB13 BB15 BB16 BB18 BB27 BB28 BB29 BB33 CC01 CC03 DD07 DD16 DD17 DD34 DD62 DD63 DD68 DD78 FF07 FF18 HH16 5F102 GD01 GD04 GJ05 GK05 GM06 GQ01 GR04 GS02 GS04 GT03 GT04 GV07 GV08 HC01 HC07 HC11 HC19 HC21

Claims (38)

[Claims] 1. A substrate, a buffer layer made of a first bandgap compound semiconductor formed on the substrate, and a second bandgap semiconductor containing a first conductivity type impurity formed on the buffer layer. An electron supply layer, a two-dimensional electron gas layer formed on the electron supply layer side of the buffer layer, and a high resistance prevention layer containing oxygen atoms on the electron supply layer at least from the electron supply layer side; A semiconductor device comprising: a gate electrode on which a metal layer is stacked. 2. The semiconductor device according to claim 1, wherein said substrate is a compound semiconductor substrate. 3. The semiconductor device according to claim 1, wherein said substrate is a semi-insulating GaAs substrate. 4. The semiconductor device according to claim 1, wherein the first forbidden band compound semiconductor has a forbidden band width smaller than that of the second forbidden band compound semiconductor. 5. The semiconductor device according to claim 1, wherein said buffer layer is an undoped compound semiconductor layer. 6. The buffer layer is made of undoped GaAs.
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor layer. 7. The semiconductor device according to claim 1, further comprising a spacer layer made of a second bandgap semiconductor between the two-dimensional electron gas layer and the electron supply layer. 8. The semiconductor device according to claim 7, wherein said spacer layer is a compound semiconductor layer containing undoped aluminum as a constituent. 9. The spacer layer is made of undoped Al.
The semiconductor device according to claim 7, wherein the semiconductor device is a _1-x Ga _x As (where x represents a positive number less than 1) semiconductor layer. 10. The semiconductor device according to claim 1, wherein said electron supply layer is a compound semiconductor layer containing aluminum containing a first conductivity type impurity as a constituent. 11. The semiconductor device according to claim 1, wherein the electron supply layer is an Al _1-x Ga _x As (where x is a positive number less than 1) semiconductor layer containing a first conductivity type impurity. Semiconductor device. 12. The semiconductor device according to claim 1, wherein said electron supply layer has a second conductivity type impurity diffusion region formed in a gate electrode formation region. 13. The semiconductor device according to claim 12, wherein said impurity diffusion region is made of a compound semiconductor containing aluminum containing a second conductivity type impurity as a constituent. 14. The impurity diffusion region according to claim 12, wherein said impurity diffusion region is made of an Al _1-x Ga _x As (where x is a positive number less than 1) semiconductor containing an impurity of a second conductivity type. Semiconductor device. 15. The semiconductor device according to claim 12, wherein said gate electrode is formed on said impurity diffusion region. 16. The high resistance prevention layer containing oxygen atoms,
2. The semiconductor device according to claim 1, comprising an electrode material for suppressing an increase in electric resistance due to an oxide film formed on a surface of said impurity diffusion region. 17. The high resistance preventing layer containing oxygen atoms,
The semiconductor device according to claim 1, wherein the semiconductor device is a titanium nitride oxide (TiON) layer. 18. The semiconductor device according to claim 1, wherein said ohmic electrode is formed by sequentially laminating titanium nitride oxide (TiON) and another metal from said impurity diffusion region side. 19. The ohmic electrode according to claim 1, wherein titanium oxide (TiON), titanium (Ti), platinum (Pt), and gold (Au) are sequentially stacked from the side of the impurity diffusion region. Semiconductor device. 20. A step of forming a buffer layer made of a first bandgap semiconductor on a substrate, and forming a second layer containing a first conductivity type impurity on the buffer layer.
Forming an electron supply layer made of a forbidden band semiconductor; forming an insulating film on the electron supply layer; forming an opening reaching the electron supply layer in a region of the insulating film where a gate electrode is formed. A step of forming a gate electrode by laminating an electrode material for suppressing an increase in electric resistance due to an oxide film on the surface of the impurity diffusion layer and another electrode material in the opening. Manufacturing method. 21. The method according to claim 20, wherein the substrate is a compound semiconductor substrate. 22. The method according to claim 20, wherein the substrate is a semi-insulating GaAs substrate. 23. The semiconductor device according to claim 20, wherein said first forbidden band compound semiconductor has a forbidden band width narrower than that of said second forbidden band compound semiconductor. 24. The semiconductor according to claim 20, wherein the step of forming the buffer layer made of the first bandgap semiconductor includes a step of forming an undoped GaAs layer on the compound semiconductor substrate on the compound semiconductor substrate. Device manufacturing method. 25. The semiconductor device according to claim 20, further comprising a step of forming a spacer layer made of a second bandgap semiconductor between the step of forming the buffer layer and the step of forming the electron supply layer. 26. The method according to claim 25, wherein the step of forming the spacer layer includes a step of forming a compound semiconductor layer containing undoped aluminum as a constituent. 27. The method according to claim 25, wherein forming the spacer layer includes forming an undoped Al _1-x Ga _x As (where x is a positive number less than 1) semiconductor layer. The manufacturing method of the semiconductor device described in the above. 28. The method according to claim 20, wherein the step of forming the electron supply layer includes a step of forming, on the buffer layer, a compound semiconductor layer containing aluminum containing a first conductivity type impurity as a component. A method for manufacturing a semiconductor device. 29. The method according to claim 29, wherein the step of forming the electron supply layer comprises: forming an Al-containing first conductivity type impurity on the buffer layer.
21. The method for manufacturing a semiconductor device according to claim 20, comprising a step of forming a _1-x Ga _x As (where x represents a positive number less than 1) semiconductor layer. 30. The method according to claim 25, wherein the step of forming the electron supply layer includes a step of forming, on the spacer layer, a compound semiconductor layer containing aluminum containing a first conductivity type impurity as a component. A method for manufacturing a semiconductor device. 31. The step of forming the electron supply layer includes forming an Al-containing first conductivity type impurity on the spacer layer.
_The method of manufacturing a semiconductor device according to claim 25, further comprising: forming a _1-x Ga _x As (where x represents a positive number less than 1) semiconductor layer. 32. Between the step of forming the electron supply layer and the step of forming an insulating film on the electron supply layer, a region of the electron supply layer where a gate electrode is formed is doped with a second conductivity type impurity. The method for manufacturing a semiconductor device according to claim 20, further comprising a step of forming a region. 33. The step of forming the impurity diffusion region,
33. The method for manufacturing a semiconductor device according to claim 32, further comprising a step of ion-implanting a second conductivity type impurity into a region of the electron supply layer where a gate electrode is to be formed. 34. The step of forming the gate electrode comprises the steps of: depositing, in the opening, an electrode material for suppressing an increase in electric resistance due to an oxide film on the surface of the electron supply layer; 21. The method for manufacturing a semiconductor device according to claim 20, further comprising a step of depositing another metal on the substrate. 35. In the step of forming the gate electrode, titanium nitride oxide (TiON), titanium (Ti), platinum (Pt) and gold (Au) are sequentially laminated in the opening, and then alloyed. 21. The method for manufacturing a semiconductor device according to claim 20, further comprising the step of forming an ohmic electrode. 36. The method according to claim 32, wherein the step of forming the opening includes a step of forming an opening reaching the impurity diffusion region of the electron supply layer in a region of the insulating film where the gate electrode is formed. A method for manufacturing a semiconductor device. 37. A step of forming the gate electrode, comprising: depositing, in the opening, an electrode material for suppressing an increase in electric resistance due to an oxide film on the surface of the impurity diffusion region;
33. The method for manufacturing a semiconductor device according to claim 32, further comprising a step of forming an ohmic electrode by depositing another metal on the deposited electrode material and alloying the same. 38. In the step of forming the gate electrode, titanium nitride oxide (TiON), titanium (Ti), platinum (Pt) and gold (Au) are sequentially laminated in the opening, and then alloyed. 33. The method for manufacturing a semiconductor device according to claim 32, further comprising a step of forming an ohmic electrode.