JPS6396965A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JPS6396965A JPS6396965A JP61243427A JP24342786A JPS6396965A JP S6396965 A JPS6396965 A JP S6396965A JP 61243427 A JP61243427 A JP 61243427A JP 24342786 A JP24342786 A JP 24342786A JP S6396965 A JPS6396965 A JP S6396965A
- Authority
- JP
- Japan
- Prior art keywords
- schottky contact
- schottky
- semiconductor device
- gate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910008310 Si—Ge Inorganic materials 0.000 claims abstract description 9
- 238000002844 melting Methods 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- -1 FET nitride Chemical class 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6738—Schottky barrier electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はショットキ接触を有する半導体装置およびその
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a Schottky contact and a method for manufacturing the same.
従来の技術
ショットキ接触を有する半導体装置のうちショットキ接
触電界効果トランジスタ（以下５ＢＦＥＴと略記する）
は高周波帯におけるトランジスタとして有望視されてい
る。この様な５ＢＦＥＴの材料として通常Ｇ ａ Ａ
ｓが用いられている。Ｇ ａ Ａ ！Ｉを用いた電界効
果トランジスタ（以下ＧａＡＳ ＦＥＴとよぶ）の基本
構造は第４図に示す様に、半絶縁性Ｇ ａ Ａ ｓ基板
１上に気相成長法でキャリヤ濃度１０１７ｃｍ”−３程
度、厚み０．３μｍ程度のｎ型導電層からなる能動層２
を積層し、この能動層２の表面にソース３．ドレイン４
となる非整流性電極、ゲート５となるショットキ接触を
設置した形になってｂる。Conventional technology Among semiconductor devices having a Schottky contact, a Schottky contact field effect transistor (hereinafter abbreviated as 5BFET)
is seen as promising as a transistor in the high frequency band. The material for such 5BFET is usually G a A
s is used. G a a! The basic structure of a field effect transistor (hereinafter referred to as GaAS FET) using I is as shown in FIG. Active layer 2 consisting of an n-type conductive layer with a thickness of about 0.3 μm
are stacked, and a source 3. is layered on the surface of this active layer 2. drain 4
The non-rectifying electrode becomes the gate 5, and the Schottky contact becomes the gate 5.
このような５ＢＦＥＴの高周波特性を改善せしＧＤニド
レイン出力コンダクタンス、ＲＧｓ：ゲート・ソース間
抵抗、ＲＧ：ゲート電極抵抗、Ｒ５：チャネル抵抗）か
ら明らかな様にゲート・ソース間抵抗ＲＧＳを減少せし
めることが“ｆ工。を増大せしめるには有効な方法であ
る。ゲート・ソース間抵抗ＲＧｓを減少せしめる方法と
して、ソース・ゲート間のｎ型導電層からなる能動層２
のキャリヤ濃度；厚みを大きくする方法、あるいはソー
ス・ゲート間距離を減少せしめる方法が有効である。To improve the high-frequency characteristics of such a 5BFET and reduce the gate-source resistance RGS as evident from the GD drain output conductance, RGs: gate-source resistance, RG: gate electrode resistance, R5: channel resistance). is an effective method for increasing the "f". As a method for reducing the gate-source resistance RGs, an active layer 2 consisting of an n-type conductive layer between the source and gate is used.
Carrier concentration: A method of increasing the thickness or a method of decreasing the distance between the source and gate is effective.
前者の従来の方法として第６図に示す様に、高濃度ｎ型
導電層２′を形成し、ゲート６の近傍の高濃度ｎ型導電
層２′を除去し、ゲート６を形成したものがある。これ
は高濃度ｎ型導電層２′によってゲート・ソース間抵抗
ＲＧＳを減少せしめたものである。As shown in FIG. 6, the former conventional method involves forming a highly doped n-type conductive layer 2', removing the heavily doped n-type conductive layer 2' near the gate 6, and forming the gate 6. be. This is because the gate-source resistance RGS is reduced by the highly doped n-type conductive layer 2'.
後者の従来の方法としては第６図に示す様Ｋ、ゲート電
極５を傘状にして傘状ゲート電極５をマスクとして自己
整合法でソース３．ドレイン４となる非整流性接触を形
成する。これによりソース・ゲート間距離が短縮しゲー
トリソース間抵抗ＲＧＳ が減少する。The latter conventional method is as shown in FIG. 6, in which the gate electrode 5 is formed into an umbrella shape and the source 3. A non-rectifying contact is formed to become the drain 4. This shortens the source-gate distance and reduces the gate-resource resistance RGS.
又ＧａＡｓ Ｆ Ｅ Ｔ ｆ ｘ ７ハンスメント型Ｆ
ＥＴとデプレッション型からなる論理回路に用いる場合
には、論理振巾及び雑音余裕度の点から接触電位の大き
いショットキ接触用材料を用いるのが望ましい。Also, GaAs FET f x 7 hancement type F
When used in a logic circuit consisting of ET and depression type, it is desirable to use a Schottky contact material with a large contact potential in terms of logic amplitude and noise margin.
発明が解決しようとする問題点
このように従来においては、高温に耐え、かつ接触電位
の大きいショットキ接触材料と、それを用い自己整合的
に半導体装置を製造する方法が望まれていた。Problems to be Solved by the Invention As described above, in the past, there has been a desire for a Schottky contact material that can withstand high temperatures and has a large contact potential, and a method for manufacturing semiconductor devices in a self-aligned manner using the Schottky contact material.
問題点を解決するための手段
本発明は、高融点金属を含むＳｉ−Ｇｅよシなるショッ
トキ接触材料を用いるものであシ、さらに望ましくはこ
の杼判よシなるゲート電極を形成し、この電極をマスク
として化合物半導体の所望領域に不純物領域を形成する
ものである。Means for Solving the Problems The present invention uses a Schottky contact material such as Si-Ge containing a refractory metal, and more preferably forms a gate electrode in the shape of this shuttle, and Using this as a mask, an impurity region is formed in a desired region of the compound semiconductor.
そこで本発明の第１の目的は高温に耐えかつ接触電位φ
Ｂの大きい、ショットキ接触材料を提供することであシ
、第２の目的は上記ショットキ接触材料を用いて、自己
整合法でソース・ドレイン領域となる高濃度不純物領域
を形成する半導体装置を提供するものである
作 用
本発明を用いることにより、高温処理に耐えかつ層抵抗
が低い良好なシッットキ電極が形成でき、これを用いて
自己整合法で８ＢＦＥＴｌ形成することにより、５ＢＦ
ＥＴの特性向上、高性能な論理回路の実現が可能となる
。Therefore, the first object of the present invention is to withstand high temperatures and to provide a contact potential φ
The second purpose is to provide a Schottky contact material with a large B. A second purpose is to provide a semiconductor device in which a high concentration impurity region that becomes a source/drain region is formed by a self-alignment method using the above Schottky contact material. By using the present invention, it is possible to form a good Schittky electrode that can withstand high temperature treatment and has low layer resistance.
It becomes possible to improve the characteristics of ET and realize high-performance logic circuits.
実施例
以下本発明の半導体装置とその製造方法を実施例で説明
する。EXAMPLES Hereinafter, the semiconductor device of the present invention and its manufacturing method will be explained using examples.
（実施例１）
第１図ａに示す様にキャリア濃度５ Ｘ １０ ” ３
− ’程度のｎ型Ｇ ａ Ａ ｍ基板１１上に第１図す
に示す様［Ｗｌ含有する８１−Ｇ＠膜１２を３００ｏ人
堆積する。Ｗ−８Ｌ−Ｇｅ膜１２はＷＳｉＧｅ板をター
ゲットとし、アルコン雰囲気中で高周波（ＲＦ）スパッ
タ装置を用いて行なった。次に第１図Ｃに示すようにＷ
−８１−Ｇｅ膜１２上にシリコン窒化膜１３’（Ｈ２０
００人堆積する。シリコン窒化膜１３は基板温度３００
℃にし、プラズマ堆積法を用いて形成した。Ｇ ａ Ａ
ｍ基板１１とＷ−８ｉ−Ｇｅ膜１２からなるショット
キ接触の熱処理温度による変化を見るため、アルゴン雰
囲気中で３０分間熱処理を行う。(Example 1) As shown in Figure 1a, the carrier concentration was 5 x 10'' 3
As shown in FIG. 1, 300 layers of 81-G@ film 12 containing Wl is deposited on an n-type GaAm substrate 11 of about -'. The W-8L-Ge film 12 was formed using a radio frequency (RF) sputtering device in an Alcon atmosphere using a WSiGe plate as a target. Next, as shown in Figure 1C, W
-81-Silicon nitride film 13' (H20
00 people deposited. The silicon nitride film 13 has a substrate temperature of 300
℃ and formed using a plasma deposition method. G a A
In order to observe changes in the heat treatment temperature of the Schottky contact consisting of the m-substrate 11 and the W-8i-Ge film 12, heat treatment is performed for 30 minutes in an argon atmosphere.
次に第１図ｄに示すようにＧ ａ Ａ ｍ基板１１に金
−ゲルマニウム（Ａｕ −Ｇｅ ）からなるオーミック
電極１４を形成し、さらにＷ −Ｓ ｉ −Ｇｅ膜１２
を通常の写真食刻法を用いて適当な形状にしてＷ −Ｓ
１−Ｇｅ膜からなるショットキ接触１２′を形成する
。さらにショットキ接触１２′へのポンディングを容易
にするためシ目ットキ接触り２′上にチタン−金（Ｔｉ
−Ａｕ）からなる電極１６を形成し、適当なパッケージ
に組立て＼、Ｗ −Ｓ ｉ Ｇｅ カラなるシタット
キ接触ダイオードが完成する。Next, as shown in FIG.
into a suitable shape using ordinary photo-etching method and form W-S.
A Schottky contact 12' made of 1-Ge film is formed. Furthermore, in order to facilitate bonding to the Schottky contact 12', titanium-gold (Ti) is placed on the Schottky contact 2'.
-Au) and assembled into a suitable package to complete a W-S i Ge color contact diode.
第２図は上記実施例で得られたシッットキ接触ダイオー
ドの熱処理温度による特性の変化を示したものである。FIG. 2 shows the change in characteristics of the Sittky contact diode obtained in the above example depending on the heat treatment temperature.
本実施例のシロットキ接触ダイオードとの比較のため、
従来からＧ ａ Ａ ａのショットキ接触材料として用
いられているアルミニウムＡｅを用いたショットキ接触
ダイオードの特性を同時に示す。同図で理想係数ｎ、接
触電位φＢはショットキ接触ダイオードの順方向特性か
ら求めたものである。即ちｎ、φＢは次式から求めた。For comparison with the Shirotki contact diode of this example,
The characteristics of a Schottky contact diode using aluminum Ae, which has been conventionally used as a Schottky contact material for G a A a, are also shown. In the figure, the ideality coefficient n and the contact potential φB are determined from the forward characteristics of the Schottky contact diode. That is, n and φB were determined from the following equations.
Ｉ、＝Ｉｓ（ｅｘｐ（ｑＶ／ｎｋＴ）−１：）Ｉ ＝
ＡＴ２ｅｘｐ （−ｑφＢ／ｋＴ）第２図から明らか
な様に従来のＡＩのショー／ ）キ接触を有するダイオ
ードではＳＯＯ℃の装処理でショットキ接触として動作
しなくなる。−力木発明の実施例によるＷ−８ｉ−Ｇｅ
のショットキ接触を用いたダイオードは８５０℃の熱処
理に耐える。即ちＷ−ｓｔ−Ｇｅはショットキ接触材料
として、耐熱性を有し、かつφＢの大きい材料であるこ
とが分かる。I,=Is(exp(qV/nkT)-1:)I=
AT2exp (-qφB/kT) As is clear from FIG. 2, a conventional AI diode with a Schottky contact no longer operates as a Schottky contact when subjected to SOO°C treatment. - W-8i-Ge according to an embodiment of the strength tree invention
diodes using Schottky contacts withstand heat treatment at 850°C. That is, it can be seen that W-st-Ge is a Schottky contact material that has heat resistance and a large φB.
（実施例２）
第３図ａ 〜ｄはＷ−３ｔ−Ｇｅｔ−用いたショットキ
接触が高温の熱処理温度に耐えることを利用して、自己
整合法で５ＢＦＥＴｉ製造する方法を示す図である。(Example 2) FIGS. 3a to 3d are diagrams showing a method of manufacturing 5BFETi by a self-alignment method, taking advantage of the fact that a Schottky contact using W-3t-Get- can withstand high temperature heat treatment.
まず第３図ａに示す様に半絶縁性Ｇ ａ Ａ ｍ基板２
１に気相成長法或はイオン注入法を用いてキャリア濃度
１０１ 程度、厚み０．３μｍ程度のｎ壓導電層からな
る能動層２２ｔ−形成する。次に第３図すに示すように
能動層２２０表面にＷ −Ｓｉ −Ｇｅ膜を実施例１と
同様の方法で堆積し、写真食刻法を用いて５ＢＦＥＴの
ゲート電極となるショットキ接触２６を形成し、これを
マスクとしてシリコｙ（Ｓｌ）（２−加速電圧２００
ＫｓＶ テ１０ ０１１ イオン注入法型ＦＥＴン窒
化膜（８１３Ｎ４）を熱処理保護膜とし８００℃で２０
分間熱処理し、高濃度ｎ型導電層２２′を形成する。高
濃度ｎ型導電層２２′上にノース２３．ドレイン２４と
なる非整流性電極を設置して５ＢＦＥＴを完成する。First, as shown in Fig. 3a, a semi-insulating GaAm substrate 2 is prepared.
In step 1, an active layer 22t consisting of an n-type conductive layer having a carrier concentration of about 10@1 and a thickness of about 0.3 .mu.m is formed using a vapor phase growth method or an ion implantation method. Next, as shown in FIG. 3, a W-Si-Ge film is deposited on the surface of the active layer 220 in the same manner as in Example 1, and a Schottky contact 26, which will become the gate electrode of the 5BFET, is formed using photolithography. Silico y (Sl) (2-acceleration voltage 200
KsV Te10 011 Ion-implanted FET nitride film (813N4) was used as a heat-treated protective film at 800°C for 20
A heat treatment is performed for a minute to form a high concentration n-type conductive layer 22'. North 23. on high concentration n-type conductive layer 22'. A non-rectifying electrode serving as the drain 24 is installed to complete the 5BFET.
図面から明らかな様に、高濃度のｎ型導電層２２′はキ
ャリヤ濃度が高く、その厚みが厚く、かつゲート電極と
なるショットキ接触と近接しているため、ソース・ゲー
ト間抵抗を減少せしめることが出来、５ＢＦＫＴの高周
波特性が向上する。As is clear from the drawing, the high concentration n-type conductive layer 22' has a high carrier concentration, is thick, and is close to the Schottky contact that will become the gate electrode, so that the source-gate resistance can be reduced. This improves the high frequency characteristics of 5BFKT.
実施例１，２では基板としてＧａＡｓｔ−用いて説明し
たが、本発明は他の■−■族化分化分物半導体材料Ｇａ
、 Ａｓを含むＡｄｘＧａｌ−ｘＡｓ 。In Examples 1 and 2, the explanation was given using GaAst as the substrate, but the present invention is also applicable to other semiconductor material Ga
, AdxGal-xAs containing As.
ＩｎｘＧａ１−ｘＡｓ等にも適用できる。又ショットキ
接触の材料として、Ｗ −Ｓ Ｌ −Ｇｅについて説明
したが、Ｗ以外の高融点合金例えばＴａ、 Ｔｉ等を用
いても良いことは勿論である。It can also be applied to InxGa1-xAs, etc. Although W-S L-Ge has been described as the material for the Schottky contact, it is of course possible to use high melting point alloys other than W, such as Ta and Ti.
発明の効果
以上実施例で説明した様に本発明は高温熱処理に耐えか
つφＢの大きいショットキ接触材料として、高融点金属
を含むＳ ｉ −Ｇｅが層抵抗が低いことを見出し、そ
れを用いて自己整合法が５ＢＦＥＴで形成することによ
り、ソース・ゲート間抵抗を減少せしめて５ＢＦＥＴの
特性を向上せしめ、かつφＢが大きいので論理振巾及び
雑音余裕度の点から論理回路の高性能化が図れる。Effects of the Invention As explained in the examples, the present invention has discovered that Si-Ge containing a high-melting point metal has a low layer resistance as a Schottky contact material that can withstand high-temperature heat treatment and has a large φB. By forming the 5BFET in the matching method, the source-gate resistance is reduced and the characteristics of the 5BFET are improved, and since φB is large, the performance of the logic circuit can be improved in terms of logic amplitude and noise margin.
第１図１−ｙ ｄは本発明の一実施例における半導体装
置の製造方法を示す工程断面図、第２図は同半導体装置
および従来の半導体装置の熱処理温度の特性の変化を比
較して示す特性図、第３図ａ〜ｄは本発明の他の実施例
における半導体装置の製造方法を示す工程断面図、第４
図、第６図、第６図はそれぞれ従来のシｗツ）キメリヤ
ゲート電界効果型トランジスタの断面図である。
１１・・・・・・ｎ型Ｇ ａ Ａ ｍ基板、１２・・・
・・・窒化シリコン（ＴＩＮ） 、 １２’−−−−−
−Ｗ−５ｌ−Ｇｅからなるシ。
ットキ接触、１３・・・・・・シリコン窒化膜、１４・
・・・・・オーミック電極、１６・・・・・・Ｔ ｉ
−Ａｕからなる電極、２１−・・・−半絶縁性Ｇ ａ
Ａ ｍ基板、２２００１１０．能動層、２２′・・・・
・・高濃度ｎｆｉ導電層、２３・・・・・・ソース電極
、２４・・・・・・ドレイン電極、２６・・・・・・シ
ョットキ接触（ゲート電極）。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名／／
＝−ｎ ’ＪＬＣｒａ−Ａｓ１０反／Ｚ −−−ｓｉ
−Ｇｅ Ｐｒ臭
第２図
り製処（Ｅ１泉 （ｔ〕
第３図
第４図
第５図
第６図FIG. 1-yd is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a comparison showing changes in heat treatment temperature characteristics of the same semiconductor device and a conventional semiconductor device. Characteristic diagrams, FIGS. 3a to 3d are process cross-sectional views showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, and FIGS.
6 and 6 are cross-sectional views of conventional chimeric gate field effect transistors, respectively. 11... n-type Ga Am substrate, 12...
...Silicon nitride (TIN), 12'------
-W-5l-Ge. contact, 13...silicon nitride film, 14.
...Ohmic electrode, 16...T i
- Electrode made of Au, 21-...-Semi-insulating Ga
A m substrate, 2200110. Active layer, 22'...
... High concentration NFI conductive layer, 23 ... Source electrode, 24 ... Drain electrode, 26 ... Schottky contact (gate electrode). Name of agent: Patent attorney Toshio Nakao and 1 other person//
=-n'JLCra-As10 anti/Z ---si
-Ge Pr odor 2nd drawing process (E1 spring (t) Figure 3 Figure 4 Figure 5 Figure 6
Claims (4)
ットキ接触を有してなる半導体装置。(1) A semiconductor device having a Schottky contact made of Si-Ge containing a high melting point metal.
となるゲート電極を設けてなる特許請求の範囲第１項に
記載の半導体装置。(2) The semiconductor device according to claim 1, wherein a gate electrode that makes a Schottky contact is provided on the semiconductor layer that acts as an active layer.
いるＳｉ−Ｇｅ、或は窒素を含有しているＳｉ−Ｇｅ或
は窒素を含む高融点金属を含有しているＳｉ−Ｇｅから
なるショットキ接触ゲート電極を設ける工程と、前記シ
ョットキ接触ゲート電極をマスクとして前記化合物半導
体の所望の領域に不純物濃度の高い領域を形成する工程
とを有してなる半導体装置の製造方法。(3) From Si-Ge containing a high melting point metal in a III-V compound semiconductor, Si-Ge containing nitrogen, or Si-Ge containing a high melting point metal containing nitrogen 1. A method for manufacturing a semiconductor device, comprising: providing a Schottky contact gate electrode; and using the Schottky contact gate electrode as a mask, forming a region with a high impurity concentration in a desired region of the compound semiconductor.
求の範囲第３項記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 3, wherein the III-V compound semiconductor is GaAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61243427A JPS6396965A (en) | 1986-10-14 | 1986-10-14 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61243427A JPS6396965A (en) | 1986-10-14 | 1986-10-14 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6396965A true JPS6396965A (en) | 1988-04-27 |
Family
ID=17103710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61243427A Pending JPS6396965A (en) | 1986-10-14 | 1986-10-14 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6396965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056995A (en) * | 1991-06-27 | 1993-01-14 | Nec Corp | High melting point metal silicide film and its formation method |
-
1986
- 1986-10-14 JP JP61243427A patent/JPS6396965A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056995A (en) * | 1991-06-27 | 1993-01-14 | Nec Corp | High melting point metal silicide film and its formation method |
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