JPS62259439A - Lithography in charged particle beam lithography equipment - Google Patents

Abstract

PURPOSE:To shorten the time of charged particle beam lithography by forming retrieved data in which is written information on each chip, dividing a region on a material to be subjected to the lithography on the basis of the data into a plurality of blocks, sorting chips according to the blocks and deciding the order of lithography of the chips in response to the blocks. CONSTITUTION:Retrieved data in which is written information on each chip is formed by a stage sequence routine 35, a region on a material to be subjected to lithography is divided into blocks having optimum block widths on the basis of the retrieved data, and the order of lithography of each chip in the block is determined in response to the block at each block. A beam lithography is performed according to a lithography execution routine 36 according to the block order and the lithography order. Thus, stage movement can be smaller to shorten the lithography time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lithography method using a charged particle beam lithography apparatus that optimizes lithography using a charged particle beam such as an ion beam.

(Prior Art) As devices for performing beam writing on chips formed on a wafer, there are an electron beam exposure device and a focused ion beam writing device. An electron beam exposure apparatus focuses an electron beam emitted from an electron gun using an electron lens, and then scans the wafer two-dimensionally using a deflector, thereby exposing and forming a predetermined pattern on the chip. On the other hand, a focused ion beam lithography system also accelerates ions emitted from an ion source, focuses them with an electron lens, and then scans the wafer two-dimensionally with a deflector to form a predetermined pattern on the chip. .

In the case of a focused ion beam lithography system, compared to the case of an electron beam exposure system, the ion species used can be exchanged with various types, and in addition to pattern formation by etching, ion implantation can be performed. There are differences.

By the way, in this type of beam lithography apparatus, various methods are employed in order to achieve optimization such as shortening the lithography time. For example, in the case of an electron beam exposure apparatus, the chip exposure order is optimized by comparing the Y coordinates and the X coordinates of individual chips.

(Problems to be Solved by the Invention) In the conventional chip exposure order optimization method described above, when the chips are scattered or when the difference in the distance between the chip center points in the Y direction is small, the stage There was a tendency for the distance traveled to increase. FIG. 9 is an explanatory diagram of a conventional exposure order optimization method. (a) and (b) Two cases are shown. In the ion beam lithography method shown here, large movements of the chip opening are performed by moving the stage, and field-by-field lithography within the chip is performed by deflecting the ion beam. The X mark in between indicates the center point of the chip.

Case (a) will be explained as an example. Even if the difference in distance Δy between the coordinates of the chip center point is small as shown in the figure,
The drawing direction of the beam is made different between the A section and the B section.

That is, the process involves scanning part A from left to right, scanning to the right end of the beam drawing area, returning, and scanning part B from right to left. Since such a scanning method is adopted for the entire area, the moving distance of the stage as a whole becomes long, and as a result, the beam drawing time also becomes long.

The present invention has been made in view of these points, and
The purpose is to realize a lithography method for a charged particle beam lithography apparatus that can shorten the moving distance of the stage and shorten the beam lithography time.

(Means for Solving the Problems) The present invention solves the above problems by creating search data that records the chip number 1 position coordinates, size, etc. of each chip for each chip diagonally above the drawing material, Based on these search data, the size of each chip is compared to determine the block width, the drawing material is divided into multiple blocks according to the determined block width, each chip is classified according to which block it belongs to, and each The present invention is characterized in that the writing order between the chips belonging to each block is determined according to the block, and beam writing is performed in the order of the blocks and in accordance with the writing order.

(Operation) The present invention creates search data in which information for each chip is written, divides the area on the drawing material into a plurality of blocks based on the search data, and determines which block each chip belongs to. The drawing order between chips belonging to each block is determined according to each block.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the present invention. The present invention will be explained below along with this flowchart.

■Chip number for each chip on the wafer.

Create search data that records position coordinates, size, pitch, etc.

FIG. 2 is a diagram showing an example of search data in which information about each chip is recorded. Such search data is usually created based on the contents of a schedule file that is separately prepared in advance. In the figure, the chip number is a number for recognizing the type of chip, and therefore chips of the same shape are given a common number. Row and column indicate coordinates in the row and column directions of the chip, respectively. The next (Xi, Yl) indicates the coordinates of the center point of each chip, and X2. Y2 indicates the size of each chip in the X direction and the Y direction (see FIG. 2(b)).

The erasing information indicates information as to whether drawing is to be performed on the chip. A wafer usually has a round shape, so if you divide it into a grid, there will be parts that are less than one grid, as shown by the diagonal lines in Figure 2 (C). (The object shows a wafer). It is pointless to irradiate this incomplete region with a beam, so such a region is skipped. For example, if "1pa" is written in the erasure information, normal drawing is caused to be performed, and if "○" is written in the erasure information, it is caused to be skipped.Alternatively, the reverse may be used.

(2) The size and pitch of each chip are compared based on the search data created in the previous step (2), and it is checked whether any other chip is placed between the chip arrays.

The comparison of each chip is for selecting parameters for performing blocking in the Y direction. Fig. 3 shows the comparative state of each gootsub. FIG. 3 shows a case where a chip of size C2 is placed between chips of size C1. The size of each chip in the Y direction is the chip size, and the distance between chips of the same type is the chip pitch.

In the case of the chip array shown in FIG. 3, another chip C2 is placed between the chip arrays of C1.

(2) The block width in the Y direction is determined according to a different algorithm depending on whether another chip array is included between the chip arrays.

If there is another chip array between the two chip arrays, the block width is a calculated value based on a plurality of chip sizes, and if not, the block width is the chip pitch itself. Calculation in the former case is performed as follows. That is, if there are four or more chip sizes, the average value is determined after excluding the maximum and small R chips, and in the case of that pond, the average value is used.

(2) The drawing fri area on the wafer is divided into a plurality of blocks in the Y direction according to the block width determined in the previous step (2), and each chip is classified according to which block it belongs to.

Here, the drawing portion of the chip on the wafer is virtually divided in the Y direction based on the determined block width.

A set of chips belonging to each block is created for each block (see FIG. 4). In the case of FIG. 4, an example is shown in which chips formed on a wafer are divided into blocks #1 to #5 with a predetermined block width. This classification is performed by determining the block in which the center coordinates of each chip are located.

(2) Ion beam writing is performed by changing the writing direction of the ion beam depending on whether block NO0 is an even number or an odd number.

Up to the previous step (2), the ranking in the Y direction has been completed. Next, optimization is performed in the X direction.

The optimization method is, for example, if each chip in the #1 block in Figure 4 is scanned in the direction in which the X coordinate increases from small to large (rightward), then the next #2 block is scanned in the opposite direction. Scans are ordered in the direction from large to small (to the left).

■Connect blocks to perform ion beam lithography.

With the above operations, the drawing order of each chip in each block is completed, and by linking each block to block numbers, the creation of data in which drawing has been optimized is completed. FIG. 5 is a diagram showing the ion beam writing order after optimization.

Although the case where blocks are formed in the Y direction has been described above, the present invention is not limited to this, and it is also possible to form blocks in the X direction.

FIG. 6 is a diagram showing an example of the configuration of a system for implementing the method of the present invention. The hardware system 10 includes a focused ion beam drawing apparatus main body 11. It is composed of a drawing driver 12 and a hardware interface 13 that connects the drawing driver 12 and the focused ion beam drawing apparatus main body 11. The software system 20 is schedule software 21. The related software 22 is composed of a drawing software 23 that incorporates the schedule software 21 and related software, and an interface software 24 that is connected to the drawing software 23. Then, the interface software 24 and the drawing driver 12 are connected, and the software system 20 and the hardware system 10 are interconnected.

The drawing software 23 is configured as shown in FIG.

The drawing software user interface 31 is a parameter input routine on the CRT for inputting and executing necessary files and parameters for routines such as high voltage control, pattern reading, calibration, and stage sequence. The high voltage control routine 32 is a routine for switching the accelerating voltage of the apparatus, the pattern read routine 33 is a routine for reading pattern data for drawing, and the calibration routine 34 is a routine for adjusting the apparatus. The stage sequence routine 35 is
Creation of files necessary for drawing execution and t-J routine with drawing order for each chip in each block and drawing execution routine 3 for chip drawing optimization
Reference numeral 6 is a routine for actually performing drawing based on pattern read and stage sequence drawing table data. The interface software 24 includes a high pressure control routine 32, a calibration routine 34, and a drawing execution routine 36.
is connected and sent to the hardware system (device side) via the interface software 24.

Figures 8(a) and 8(b) show the drawing order according to the method of the present invention,
It is a figure shown about two chip patterns. For comparison, FIGS. 9A and 9B show the conventional drawing order for the same chip pattern. As is clear from the figure,
In the case of the method of the present invention, the amount of stage movement is obviously smaller, and therefore the drawing time can also be shortened.

Note that the present invention can be similarly applied to a drawing method using an electron beam drawing apparatus, and the material to be drawn is not limited to a wafer, but may also be a mask or the like.

(Effects of the Invention) As described in detail above, according to the present invention, search data in which information for each chip is written is created, and based on this search data, a block having an optimal block width is drawn. By dividing the area on the material, determining the writing order of each chip in each block according to each block, and performing beam writing in the order of the blocks and according to this writing order, stage movement can be reduced. Therefore, it is possible to realize a drawing method using a charged particle beam drawing apparatus that can shorten drawing time.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing one embodiment of the present invention;
The figure is an explanatory diagram of the search data, Figure 3 is a diagram showing the state of chip arrangement, Figure 4 is a diagram showing the state of division into blocks, and Figure 5 is a diagram showing the state of division into blocks.
6 is a diagram showing a drawing order according to the present invention, FIG. 6 is a diagram showing a configuration example of a system for implementing the present invention, FIG. 7 is a diagram showing a configuration example of drawing software, and FIG. 8 is a diagram showing a configuration example of a drawing software according to the present invention. FIG. 9, which is an explanatory diagram of the effect, is a diagram showing the conventional drawing order. 11... Focused ion beam drawing device 12... Drawing driver 13... Hardware interface 1 Fig. 4 Fig. 5

Claims (1)

[Claims] Search data is created that records the chip number, position coordinates, size, etc. of each chip for each chip on the drawing material, and based on this search data, the size of each chip is compared to determine the block width. Divide the material to be drawn into multiple blocks according to the block width, classify each chip according to which block it belongs to, decide the drawing order among the chips to which it belongs according to each block, and draw the drawing material in the block order and according to the drawing order. A lithography method using a charged particle beam lithography apparatus, characterized in that beam lithography is performed.