JPH06101421B2 - Drawing method of charged particle beam drawing apparatus - Google Patents

Description

The present invention relates to a drawing method of a charged particle beam drawing apparatus for optimizing drawing by a charged particle beam such as an ion beam.

(Prior Art) As an apparatus for performing beam drawing on a chip formed on a wafer, there are an electron beam exposure apparatus and a focused ion beam drawing apparatus. The electron beam exposure apparatus focuses an electron beam emitted from an electron gun by an electron lens and then two-dimensionally scans a wafer by a deflector to form a predetermined pattern on a chip by exposure. On the other hand, the focused ion beam drawing apparatus also accelerates the ions emitted from the ion source and focuses them with an electron lens, and then two-dimensionally scans the wafer with a deflector to form a predetermined pattern on the chip. . In the case of a focused ion beam drawing apparatus, compared to the case of an electron beam exposure apparatus, the ion species used can be exchanged for various types, and ion implantation (ion implantation) is possible in addition to pattern formation by etching. Different.

By the way, in this type of beam drawing apparatus, various methods are adopted in order to optimize such as shortening the drawing time. For example, in the case of an electron beam exposure apparatus, optimization of the chip exposure order is performed by comparing the size of the Y coordinate and the size of the X coordinate of each chip.

(Problems to be Solved by the Invention) In the above-described conventional method for optimizing the chip exposure order, when the chips are scattered or the difference in the Y-direction distance between the chip center points is small, the stage It tended to increase the distance traveled. FIG. 9 is an explanatory diagram of a conventional exposure sequence optimization method. Two cases of (a) and (b) are shown. In the ion beam drawing method shown here, a large movement between chips is performed by moving the stage, and drawing in field units within the chip is performed by ion beam deflection. The X mark in the figure indicates the center point of the chip.

The case (a) will be described as an example. Even if the distance difference Δy between the coordinates of the chip center point is small as shown in the figure,
The beam drawing directions are made different between the A part and the B part.
That is, the process of scanning the part A from left to right, scanning to the right end of the beam drawing area, and returning to scan the part B from right to left is performed. Since such a scanning method is adopted in the entire area, the movement distance of the stage as a whole becomes long, and the beam drawing time also becomes long as a result.

The present invention has been made in view of such points,
The purpose thereof is to realize a drawing method of a charged particle beam drawing apparatus which can shorten the moving distance of the stage and shorten the beam drawing time.

(Means for Solving Problems) The present invention for solving the problems described above creates search data in which chip numbers, position coordinates, sizes, etc. of the respective chips are recorded for each chip on a drawing material, and The size of each chip is compared based on the search data to determine the block width, the drawing material is divided into multiple blocks according to the determined block width, and each chip is classified according to which block it belongs to. The drawing order between the chips belonging thereto is determined according to the above, and the beam drawing is performed according to the block order and the drawing order.

(Operation) The present invention creates search data in which information for each chip is written, divides the region on the drawing material into a plurality of blocks based on these search data, and determines which block each chip belongs to. Then, the drawing order among the chips belonging to each block is determined.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flow chart showing an embodiment of the present invention. The present invention will be described below with reference to this flowchart.

For each chip on the wafer, search data is created that records the chip number, position coordinate, size, pitch, etc. of each chip.

FIG. 2 is a diagram showing an example of search data in which information of each chip is recorded. Such search data is usually created based on the contents of a separately prepared schedule file. In the figure, the chip number is a number for recognizing the type of chip, and therefore, chips of the same shape are given common numbers. The row and column indicate the coordinates in the row direction and the column direction of the chip, respectively. The next (X1, Y1) indicates the coordinates of the center point of each chip, and X2, Y2 indicate the size of each chip in the X and Y directions (see FIG. 2B).

The erase information indicates information as to whether or not the chip is to be drawn. Since the wafer is usually in the shape of a circle, if this is divided into a grid, there will be a portion less than one grid as shown by the diagonal lines in Fig. 2C. The object shows a wafer). Irradiating the beam to this incomplete region is meaningless, and thus such a part is skipped. For example, if "1" is written in the erase information, normal drawing is performed, and if "0" is written, it is skipped. Alternatively, the reverse is also possible.

The size and pitch of each chip are compared based on the search data created in the previous step, and it is checked whether or not another chip is arranged in a certain chip arrangement.

The comparison of each chip is for selecting a parameter for performing blocking in the Y direction. FIG. 3 shows a comparison state of each chip. FIG. 3 shows a case where a chip of size C ₂ is arranged between chips of size C ₁ . The size of each chip in the Y direction is the chip size, and the distance between chips of the same type is the chip pitch. In the case of the chip arrangement shown in FIG. 3, another chip C ₂ is inserted between the chip arrangements of C ₁ .

The block width in the Y direction is obtained according to a different algorithm depending on whether another chip arrangement is included between certain chip arrangements.

When another chip arrangement is included between certain chip arrangements, the block width is a calculated value based on a plurality of chip sizes, and when not included, the block width is the chip pitch itself. The calculation in the former case is performed as follows. That is, when there are four or more chip sizes, the average value is calculated after removing the maximum and minimum values, and the average value is used in other cases.

The drawing area on the wafer is divided into a plurality of blocks in the Y direction according to the block width determined in the previous step, and each chip is classified according to which block it belongs to.

Here, the drawing portion of the chip on the wafer is virtually divided in the Y direction based on the determined block width, and a set of chips belonging to it is created for each block (see FIG. 4). . FIG. 4 shows an example in which the chips formed on the wafer are divided into blocks of # 1 to # 5 with a predetermined block width. This classification is performed by determining the block in which the center coordinate of each chip is located.

Ion beam drawing is performed by making the ion beam drawing direction different depending on whether the block number is even or odd.

Up to the previous process, the ranking in the Y direction has been performed. Next, optimization in the X direction is performed. The optimization method is, for example, if the chips in the # 1 block in FIG. 4 are ordered in the scan direction from the small X-coordinate to the large X-coordinate (to the right), the X-coordinate of the next # 2 block is reversed. The scans are ordered in the direction from large to small (to the left).

Ion beam drawing is performed by connecting blocks.

By the above operation, the drawing ordering of the chips in each block is completed, and if the blocks are connected in the order of block numbers, the creation of the drawing optimized data is completed. FIG. 5 is a diagram showing the order of ion beam writing after optimization.

Although the case of blocking in the Y direction has been described above as an example, the present invention is not limited to this, and blocking in the X direction is also possible.

FIG. 6 is a diagram showing an example of the configuration of a system for carrying out the method of the present invention. The hardware system 10 is composed of a focused ion beam drawing apparatus main body 11, a drawing driver 12, and a hardware interface 13 connecting the drawing driver 12 and the focused ion beam drawing apparatus main body 11. Soft system 20
Is composed of schedule software 21, related software 22, drawing software 23 including the schedule software 21 and related software, and interface software 24 connected to the drawing software 23. Then, the interface software 24 and the drawing driver 12 are connected, and the software system 50 and the hardware system 10 are interconnected.

The drawing software 23 is configured as shown in FIG. The drawing software user interface 31 is a parameter input routine on the CRT for inputting and executing files and parameters required for routines such as high-voltage control, pattern reading (reading), calibration, and stage sequence. The high voltage control routine 32 is a routine for switching the acceleration voltage of the device, a pattern read routine
Reference numeral 33 is a drawing pattern data reading routine, and calibration routine 34 is a routine for adjusting the apparatus. The stage sequence routine 35 is a routine for creating the files necessary for drawing execution and the above-mentioned block formation for chip drawing optimization and drawing ordering of each chip in each block, and the drawing execution routine 36 is pattern read,
This is a routine for actually drawing based on each drawing data of the stage sequence. Interface software 24 includes high-voltage control routine 32 and calibration routine 3
4 and the drawing execution routine 36 are connected and sent to the hardware system (device side) via the interface software 24.

8A and 8B show the drawing order by the method of the present invention,
It is a figure shown about two chip patterns. For comparison, FIGS. 9A and 9B show the conventional drawing order for the same chip pattern. As is clear from the figure,
According to the method of the present invention, the amount of stage movement is obviously smaller, and therefore the drawing time can be shortened.

The present invention can be similarly applied to a drawing method using an electron beam drawing apparatus, and the material to be drawn is not limited to a wafer and may be a mask or the like.

(Effects of the Invention) As described in detail above, according to the present invention, search data in which information for each chip is written is created, and drawing is performed on a block having an optimum block width based on these search data. By dividing the area on the material, determining the drawing order of each chip in the block according to each block, and performing beam drawing in the block order and according to this drawing order, the stage movement amount can be small, and therefore Thus, it is possible to realize the drawing method of the charged particle beam drawing apparatus that can reduce the drawing time.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention,
FIG. 4 is an explanatory diagram of search data, FIG. 3 is a diagram showing a state of chip arrangement, FIG. 4 is a diagram showing a division state of each block, and FIG.
FIG. 6 is a diagram showing a drawing sequence according to the present invention, FIG. 6 is a diagram showing a configuration example of a system for carrying out the present invention, FIG. 7 is a diagram showing a configuration example of drawing software, and FIG. 8 is a diagram showing the present invention. FIG. 9 is a diagram showing the effect, and FIG. 9 is a diagram showing a conventional drawing order. 11 …… Focused ion beam drawing device 12 …… Drawing driver 13 …… Hardware interface

Claims (1)

[Claims] 1. A search data in which a chip number, a position coordinate, a size, etc. of each chip are recorded for each chip on a drawing material, and the size of each chip is compared based on these search data to determine a block width. Determined, divide the drawing material into multiple blocks according to the determined block width, classify each chip according to which block it belongs to, determine the drawing order between the belonging chips according to each block, block order Further, the drawing method of the charged particle beam drawing apparatus is characterized in that the beam drawing is performed according to the drawing order.