JPS62249282A - Image memory - Google Patents

Abstract

PURPOSE:To establish an access to a dot data from the lateral direction and the longitudinal direction by shifting and storing successively either of the length and the breadth of the dot of image data for every dot. CONSTITUTION:A memory to store image data is composed of 256 bits X 256 bits, one address is composed of one word (1b-bit), X coordinate addresses OH - FH of a word unit are supplied in the horizontal direction and Y coordinate addresses OOH - FFH of the bit unit are given in the longitudinal direction. The bit arrangement in the word at respective address is D15,D14..D0 in OOH of Y coordinates, D0,D15..D1 in O1H, and as such, each time the Y coordinates are stepped, rotation shifting and arrangement are executed in an 1b-bit unit. By accessing the memory, the image memory is made obtainable to access simultaneously plural dot data which are purposes in the horizontal direction and the longitudinal direction can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory, and more particularly to an image memory for storing image data.

[Traditional technique]

The development of microprocessors has made it possible to perform complex processing of image data. For example, rotation in the displayed image of the obtained figure can be mentioned.

The image data of the above-mentioned figure is, for example, the white and black of each dot.
It is 1-bit data represented by "0" or ""11, and is stored in memory in units of multiple dots (in the case of colors or gradations, multiple bits are assigned to one door).
. FIG. 10 is a block diagram of a memory that stores image data (256 dots x 256 dots). ■The address consists of 1 word (16 bits), 16 dots in the horizontal direction (X-direction image) of the image, and 1 dot in the vertical direction (Y-direction image).
One word of dots is stored so as to correspond to the position of the image. The image is divided into 16 dots to the right of the upper left dot, and the data of the 16 dots (16 bits) is stored in the image address "0OOH", and the next 16 dots on the right are stored in the image address XG "0010".

Since there are 256 dots in the horizontal direction, 16 addresses (the lowest 4 bits of the address) are the addresses for one row. The Y-direction image address (YG) is stored in rows of one dot as "0OOH" to 1010H" (the "H" in "@" represents hexadecimal).

Conventionally, when reading data stored in the memory mentioned above, address 000, address 001, . . . address 0 are sequentially read out.
By reading in the order of 10, address 021...
It is possible to obtain image data in the normal position, that is, unrotated image data (when not rotated).

On the other hand, for example, 90 degrees from the position when displayed on the display screen.
When obtaining right-rotated image data, the bit corresponding to one dot on the lower left side is read upward. That is,
If the MSB (B15) of the 16 bits is placed on the left side of the display screen, 16 words from address FFO to address FOO are sequentially read out, and each bit 15 of the 16 words is read out.
(B15) is configured as one word, and the obtained one word is one word (address 000) at the upper left on the screen.

Next, 16 words from address EFO to address EOO are read out, and each bit 15 (
B15) as one word and the next one word (address 00
1). After reading out one vertical column, 16 words at the same addresses FFO to FOO are read out, and bit 14 (B14) of the 16 words is set as one word. After further 16 columns have been read, one word is similarly read from bit 15 (B15) of 16 words of addresses EFO to EOO. By reading out 16 words and selecting 1 bit in this manner, image data rotated to the right by 90° is obtained.

[Problems with conventional technology]

In the conventional 90° rotation described above, although data is read in units of one word, one bit of data within one read word becomes a valid bit. In other words, 15 bits out of the 16 bits read are invalid data. Further, when writing, the 16-bit data for writing is divided into 1-bit units, and 1 word at the target position is read out, 1 pinpoint conversion is performed, and the data is written again. In other words, although it has 16-bit read and write functions, the processing within it is only 1
This is done using bits, which has the problem of slow processing. Particularly in writing, since the data is read once and then written, there is a problem in that it takes additional processing time.

Directly access the memory described above sequentially in the horizontal direction, and
In the case of outputting the video signal to a display device such as T, etc., memory access is performed using a circuit that operates as described above. However, the read speed in the horizontal direction and the read speed in the vertical direction are different, and the processing of the obtained word in units of dots is different (in the horizontal direction, a parallel in-serial out register is used each time one word is read out). (in the vertical direction, the target bit is selected and output every time one word is read out), which has the problem of complicating the circuit.

[Purpose of the invention]

In view of the above conventional drawbacks, the present invention provides an image memory that simultaneously outputs a plurality of targeted dot data both when accessing the memory from the horizontal direction and when accessing the memory from the vertical direction. The purpose was to.

[Key points of the invention]

In order to achieve the above object, the present invention provides a memory that stores a plurality of dots of image data of nxn dots in units of one address. In response to this, at least one of the horizontal rows and vertical columns of the memory is sequentially shifted by one dot and stored.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a memory layout diagram of the present invention. In the figure, the upper part of the box corresponding to each dot represents a memory address, and the lower part represents a focus position within that address. When the Y coordinate (YK) of the basic image is "00" and the X coordinate (XK) of the basic image is OO, it is assigned to dot 15 (Dl5) of the memory address ADD "oooo '". Then, the basic image is sequentially stepped in the X coordinate (XK) direction by 16 addresses (FH; H is hexadecimal) in 16-bit units, and the dots in between are focused (15 to via) 0 (DI5 to Do).
). Also, the Y coordinate (YK) of the basic image is “0”
1", the dot correspondence when the Y coordinate (YK) of the basic image described above is "00" is set to 1 horizontal line of the basic image corresponding to the Y coordinate (YK) of the basic image in units of 1 word. The assignment is shifted by a bit.

In other words, if the Y coordinate (YK) of the basic image is @01'', dot O (MO) of address ADD "oioo", and bits 15 to 1 (D15 to DI) on the right side.
It is constructed by shifting 1 bit. Further, each time the Y coordinate (YK) address of the basic image increments, it is shifted by 1 bit in units of 16 bits.

In other words, the Y coordinate (YK) of the basic image is “00”
When , bits 15 to 0 (015 to DO) of address ADD “oooo”, address ADD “ooooi”
” focus 15 to bit 0 (D15 to Do), address ADD ``0002'' bit 15 to bit 0 (D15 to Do)
DO)...If the Y coordinate (YK) of the basic image is 101", the address is ADD "0100".
bit 0 (DO) followed by bit 15 to bit 1
(D15-D1), bit 0 of address 0101 (DO
) Next, bits 15 to 1 (D15 to D1), bit 0 (Do) of address 0102, and so on are closed. Furthermore, when the Y coordinate (YK) of the basic image is 102", the address ADD10200" is 1. OCDI
~DO) Then bits 15 to 2 (DI5 to D2)
) Dot 1 of address ADD “0201”. O(Dl,
Do), followed by bits 15 to 2 (D15 to D2).
)... In order to sequentially increment the Y coordinate of the basic image, the Y coordinate is shifted in units of 16 bits, that is, rotationally shifted and assigned.

Due to the above-mentioned allocation, when a basic image is read out in units of 16 bits in the horizontal and vertical directions, the bit values (D15 to Do) within the 16 bits are always different. This allows vertical and horizontal access in units of 16 bits. Note that in the horizontal direction, the same address is accessed, and in the vertical direction, different memories are accessed bit by bit.

FIG. 2 is a circuit diagram of the first embodiment of the present invention. The frame memories (M15 to MO) each have a 1-pin input/output terminal I10, and 16-bit data (D15 to D
o) constitutes a memory for inputting and outputting. Note that the number of diagonal lines in the connecting portion in the figure represents the number of bits. Each frame memory M15~MO has an address value (Y7~YO, X3~XO
) is added to the address input terminal and the block value (BLK6
~BLKO) is added to the block input terminal.

The frame memory (M15 to MO) has the capacity to store multiple screens, and the terminal for specifying the multiple screens is
This is a block input terminal to which block values (BLK 6 to BLKO) are added. This block value (BLK6~BL
KO) specifies the target block, that is, the page of the screen.

The upper bits of the Y coordinate (YK) of the basic image (YK7 to YK
4) and the upper 4 bits (XK7 to XK4) of the X coordinate XK are input terminal A of selector SLI and selector SL2, respectively.
, input terminal B of selector SLI, and input terminal A of selector SLl. Selector SLI, SL2
selects the data applied to input terminals A and B and outputs it to output terminal C.
This is a circuit that outputs data to the selection terminal S.
It is determined by the vertical/horizontal switching signal H/V applied to EL. When the vertical/horizontal switching signal H/V is at L level "O", selectors SL1 and SL2 select the data applied to input terminal A and output it to output terminal C, and vice versa when it is at H level @1". Select the data to be added to output terminal C
Output to. In the following, first, the case where the selection signal H/V is an L level signal will be explained. At this time, the aforementioned selector SLI selects the upper 4 bits of the Y coordinate of the basic image, YK.
7 to YK4 are selected, and the selector SL2 selects the top four pixels of the X coordinate of the basic image (XK7 to XK4) and outputs them to each output terminal C.

Output terminal C of selector SLI is exclusive OR group EORG
The upper 4 bits of the basic image YK selected through 2
~YK4) are output as signals YS3 to YSO to terminals to which address values Y7 to Y3 of frame memories M15 to MO are added. Since the vertical/horizontal switching signal H/V is applied to one input of exclusive OR group EORC;2, exclusive OR group EORG2 operates as a buffer and selector S
The output logic of L1 is not inverted and is applied to the terminals of the frame memories M15 to MO mentioned above. The output terminal of selector SL2 outputs the upper 4 bits of the selected basic image XK (XK7
~XK4) are output to terminals to which address values X3 to XO of frame memories M15 to MO are added. On the other hand, the lower 4 bits (YK3 to YKO) of the Y coordinate (YK) of the basic image are sent to A of the address decoder via the exclusive OR group EORGI.
It is applied to a terminal to which decoded input values YA3 to YAO of DRR are applied and to a terminal to which decoded input values YB3 to YBO of decoder DRH are inputted. The vertical/horizontal switching signal H/V is applied to one gate of the exclusive OR group EORGI, and the lower 4 bits (Y
K3~YKO) has been added. Therefore, when the vertical/horizontal switching signal H/V is at L level, exclusive OR group EORG
1 operates as a non-inverting circuit, that is, a simple buffer. In the address decoder ADRR, in addition to the output of the exclusive OR group EORCI mentioned above being added as address values YB3 to YBO, a vertical/horizontal switching signal H/V is also applied to the terminal S of the address decoder ADRR, and these signals cause the memories M15 to M15 to A specific decode value QF3~Q is applied to the lower 4 bits of the terminal to which the MO address values Y7~YO are added.
FO, . . . outputs QO3 to QOO.

FIG. 3 is an input/output data chart of address decoder ADRR. Figure 3(a) shows that the vertical/horizontal switching signal H/V is L.
Figure 3 (at the time of 7L/ (i.e. H/V-0) to L/
In b), the vertical/horizontal switching signal H/V is at H level (H/V-1
) is the input/output data chart for each time. As mentioned above, when the vertical/horizontal switching signal H/V is L, as shown in Fig. 3 (
The output data is determined as shown in a) and each frame memory M
The address values Y3-YO added to frame memories M15-MO, that is, the respective decoded outputs QF3-QFO, .

Each of the above-mentioned values (block values B6 to BO and address value Y7
~YO, X3-XO) are added to the frame memories M15-MO, each frame memory M15-MO outputs or inputs data DI5-Do corresponding to the value. In addition, a read/write signal R/W is added to each frame memory M15 to MO in addition to the above-mentioned one, and when this read/write signal R/W is at L level, a read operation is performed, and when it is at an H level, a write operation is performed, and each memory M15 ~MO becomes.

In other words, when it is at L level, it outputs the stored data,
When the level is H, data to be added is input. Address values Y7 to YO and X3 to XO are the same as accessing 16 bits in the horizontal direction in FIG. 1, and for example, when reading, 16 bits in the horizontal direction are read simultaneously.

As shown in FIG. 1, in the embodiment of the present invention, the 16 bits in the horizontal direction are always shifted by 1 bit in the vertical direction. Correcting this shift,
The bit shift circuit BSC sets the position corresponding to the X and Y coordinates of the basic image to be added. By this bit shift circuit BSC, data DB15 corresponding to the position is
~DBO can be obtained.

The output of the exclusive OR group EORGI of YK3 to YKO described above is added to the decoder DRR.

When the vertical/horizontal switching signal H/V is at the L level, this exclusive OR group EORGI is not inverted, that is, it operates as a buffer, so the decoder DRR receives the Y coordinate (Y
K)'s bottom four pits) (YK3 to YKO) will be added. Decoder DRR is the added value (address value) VB3~YBO
This is a circuit that decodes the . For example, when the 4-bit address value YB3 to YBO is "0000", the output SDO becomes "1", the others become "0", when it is "0001", the output SDI becomes "1", and the others become O". On the other hand, the bit shift circuit BSC has 16 bit shift circuits BSCQ.
~13SC15, and is configured to have a shift amount corresponding to the decoded value described above. In other words, bit shift circuit B5C0 shifts 0 (input/output (data) D
15~DO and input/output DB15~DBO have a one-to-one correspondence)
, bit shift circuit B'S C1 is input/output (data)
DO is input/output DB15, input/output (data) D15-D
1 corresponds to the input/output DB14 to DBO, and similarly, the bit shift circuits B5C2 to B5Cl3 sequentially shift and correspond.

This bit shift circuit BSC allocates positions corresponding to the dots in each of the frame memories M15 to MO shown in FIG. In addition, bit shift circuits B5C0-B5
Each of the Cl 5's is composed of 16 bidirectional buffers, and the above-mentioned shift amount is determined by the connections of the bidirectional buffers, and the direction thereof is controlled by the read/write signal R/W.

Due to the operation described above, the vertical/horizontal switching signal H/V becomes L.
When the level is "0", the dots are arranged as shown in FIG. 4, and the data in the memory arrangement shown in FIG. 1 can be accessed by external access. Note that output is performed in units of 16 bits, so the lower 4 bits of the X coordinate (XK) of the basic image,
3~XKO is not necessary.

Next, the case when the vertical/horizontal switching signal H/V is at H level will be explained. At this time, first selector SLI.

SL2 selects data input from input terminal B and outputs it to output terminal C. That is, the output terminal C of the selector SLI has the upper 4 bits XK7 to X of the X coordinate XK of the basic image.
K4 is output. This output is the exclusive OR group EORG
2, but in this case the exclusive disjunction group E O'RG 2
Since the H level of the vertical/horizontal switching signal H/V is added to one input of the
Bifts XK7-XK4 are reversed or inverted. Due to this inversion operation, the address values Y7 to Y4 of the frame memories M15 to MO become values obtained by inverting the upper four bits XK7 to XK4 of the X coordinate of the basic image. For example, when accessing from the upper left corner to the right, such as when accessing a basic image, F is sequentially accessed.

E,...0. The input changes as F, E, ...0...0. On the other hand, the bottom 4 of Y Kuri YK in the basic image
P1-YK3 to YKO are added to the exclusive OR group EORGI, and the vertical/horizontal switching signal H/V is also applied to one input of this exclusive OR group EORG1 as described above. Therefore, by this exclusive OR group EORG1, the lower 4 Biff1-YK3~ of the Y coordinate YK of the basic image
YKO is inverted and applied to address decoder ADRR and decoder DRR as address values YB3 to YBO. The address decoder ADRR switches the output data using the vertical/horizontal switching signal H/v, converts the address values YB3 to YBO as shown in FIG. 3 (bl), and stores the decoded values QF3 to QFO, .・・Q
Outputs O3 to QOO. For example, when the upper left end of the basic image is accessed, the lower four bits (YK3 to YKO) of the Y coordinate YK of the basic image are inverted (1111'') by the exclusive OR group EORGI and added to the address decoder.

“When 111 Hi is added, the address decoder ADRR
"oooo" for each frame memory M15 to MO
”, “1111”, “1110”, “0ill
l''.

“0110”, “0101”, “oioo”,
“ooit”.

0001''. Also, the selector SL2 selects the upper 4 bits YK7 to YK4 of the Y coordinate YK of the basic image and adds them as dot values X3 to XO of the frame memories M15 to MO, so when the above-mentioned upper left corner is accessed, Frame memories M15 to MO each have FOOH and FF.
0T (-FIOH (H represents hexadecimal. H is omitted in the figure) is added. Frame memory M15
By adding these address values Y7 to YO and X3 to XO to ~MO, 16 bits of data are stored in each frame memory M15 to M from the lower left end in FIG.
Output from O. This data is 16 bits of data from the lower left end of the basic image to the upper side, but the order is shifted. This is corrected and DI4-DO is performed as shown in FIG.

The bit shift circuit BSC operates at D15. As mentioned above, when the vertical/horizontal switching signal H/V is at a high level, the lower 4 bits of the Y coordinate YK of the basic image are inverted by the exclusive OR group EORG1 and sent to the decoder DR.
R (YB3 to YBO), the decode output 5D15 connected to the bit shift circuit B5Cl3 becomes H level, and the H level is applied to the enable terminal E of the bit shift circuit BSC to operate the bit shift circuit B5Cl3. The input/output (data) D15 of this bit shift circuit B5Cl3 corresponds to input/output DBO, and the input/output (data) DO-DI4 corresponds to input/output DBI to DB15, so this bit shift circuit B5Cl5 allows
Input/output DB15 to DI30 correspond to 16 bits sequentially cut out above the lower left end of the basic image. and,
Next, when the upper 4 bits of the X coordinate XK of the basic image change sequentially, the frame memories M15 to MO are sequentially read out in the vertical direction in the same manner as described above, and a specific bit is shifted by the bit shift circuit BSC.

In the embodiment of the invention shown in FIG. 2, the bit shift circuit BSC is a bidirectional buffer whose direction changes with the read/write signal R/W.

Therefore, the X coordinate of the basic image mentioned above and the Y coordinate of the basic image
When coordinates are added and the memory is accessed, when the read/write signal R/W is at L level, the frame memory M15
~ MO read and write when at H level. Also, since vertical access or horizontal access is performed depending on the vertical/horizontal switching signal H/V, when the vertical/horizontal switching signal H/V is at L level, reading and writing are performed at the normal position (not rotated). When the vertical/horizontal switching signal H/V is at H level, it is possible to obtain data in which the basic image is rotated concavely to the right during reading. Furthermore, during writing, data rotated 90° to the left with respect to the data written when the vertical/horizontal switching signal H/V is at L level is written in the frame memory.

Through the above-described operations, the image data when the vertical/horizontal switching signal H/V is rotated by an L level to the right can be read out, and the H level can be used to write image data when the image is rotated by an angle to the left. In addition, 16 bits can be obtained in both directions at the same time in one write or read operation, making memory access faster than in the past.

FIG. 5 is a circuit diagram of a second embodiment of the present invention. The image memory CHG has a circuit configuration similar to that shown in Fig. 2, and the block values BLK5 to BLKO1 vertical/horizontal switching signals H/V, address values Y7 to YO, X3 to XO, and read/write signals R/W. The input terminal and data DB15 to DBO are output when reading, and data D is output when writing.
It has terminals to which B15 to DBO are input.

In the circuit configuration shown in Figure 2, the image memory CHG reads out data rotated by 90 degrees to the right with respect to the basic image, and 90 degrees to the left.
Only rotated data could be written.

The circuit in Figure 5 is ``step'',
180”, 270° clockwise rotation (270°.

This circuit makes it possible to successively print and write basic images rotated by 180° or 90° to the left. If it is possible to obtain a rotated image of ±(capital)°, image memo IJ CH
By inverting the address value of G and swapping the data bits (exchanging all MSB and LSB bits) when necessary, it is possible to obtain any rotated image or reversed image.

The exclusive OR group EOR performs the inversion of this address value.
G3. EORG4 is a data swap circuit WSC that performs data bit swapping.

The inversion control signal YINV is applied to one input of the exclusive OR group EORG3, and the address values YA7 to YAO of the Y coordinate are applied to the other input. The inversion control signal YINV is “
1", that is, I (at level, address value YA7~Y
AO is inverted and added to the image memory CHG as address value YK. Also, when the inversion control signal YTNv is "0", that is, at L level, its output is not inverted (the logic is not inverted) and the address values YA7 to YAO are sent to the image memo +
Add as address value YK of JCHG.

The inversion control signal XINV is applied to one input of the exclusive OR group EORG4, and the other input receives the X-coordinate address values XA7 to XA4 (upper 4 bits only; lower 16 bits are not necessary as they are read in parallel). ) is added. When the inversion control signal XINV is “1”, the address values XA7 to XA
4 is inverted and the address value XK is added to the image memory CHG. Further, when the inversion control signal XINV is "0", its output is non-inverted, and the address values XA7 to XA4 are directly added as the address value XK of the image memory CHG. Address values YA7 to YAO are generated by the exclusive OR group EORG3°BORG4 described above.

Image memory C by inverting or non-inverting XA7 to XA4
Can be added to HG.

On the other hand, the data swap circuit WSC has two-phase bidirectional buffers WSC1 and WSC2 in units of 161B1, and the bidirectional buffer group WSCI has the input/output D of the image memory C1 (G).
B15 to DBO are connected corresponding to data DD15 to DDO. Further, the bidirectional buffer group WSC2 transfers data DBO to DB15 of the image memory CHG to data DD1.
5 - Connected in accordance with DDO. The data swap signal WS is applied to the input terminal E (terminal for controlling operation) of the bidirectional buffer group WSCI via the inverter INV, and the data swap signal WS is directly applied to the bidirectional buffer group WSC2. Each bidirectional buffer group W
S.C.I.

WSe2 operates when “1” (H level) is applied to the enable terminal E, so when the data swap signal is “11”, the input/output DB15 of the image memory CHG is activated.
-Make correspondence between DBO and data DD15 - data DDO,
In other words, swap the data bit by bit up and down,
10'', input/output is controlled in a one-to-one correspondence. Note that the read/write signal R/W is applied to the bidirectional buffer groups WSCI and WSC2, and the read (“O”)
When , data I) 815~DBO is changed to data DD15~
It is output in correspondence with DDO or data DDO-DD15, and when writing (“1”), data DD15-DDO is output as data DB15-DBO or data DBO-DB1.
5 and added to the image memory CHG.

Figure 6 shows the vertical/horizontal switching signal H/V and the inversion control signal YIN.
3 is a chart showing the positional relationship between an image obtained during reading and an image written during writing in V, XINV, and data swap signals WS.

In addition, the rotation operation at the time of reading uses the position state of the image read when the missionary basic image is written, and the written data at the time of writing, using the signals VINV, XINV, and WS.
, H/V are both in the "0" state.

First, the case where the vertical/horizontal switching signal H/V is "0" will be explained. When the inversion control signals YINV, XINV and the data swap signal WS are both ``O'', a normal basic image can be obtained and written during reading and writing. In other words, it is possible to read and write data without rotation.

On the other hand, when the inversion control signal YINV is "13", the address values YA7 to YAO are inverted by the exclusive OR group EORC3, so an upside-down back image is obtained both during reading and writing. When the basic image of the position is written, the image of the upside down back side can be read,
Conversely, when a basic image is being input, it is possible to write the reverse side of the basic image upside down.

When the inversion control signal YINV is “O”, the inversion control signal XINV
When the data swap signal WS is "1", writing and reading can be performed on the reverse side of the left and right sides. inverted control signal YINV,
When XINV and data swap signal WS are all "1", the X and Y coordinates are reversed horizontally and vertically, and the data is swapped by the data swap signal, so when reading and writing, the basic image rotated by 180 degrees is read. You can publish and write again.

On the other hand, when the vertical/horizontal switching signal H/V is "1", if the other signals YINV, XTNV, and WS are all "0", data rotated 90 degrees to the right can be read out, and data rotated 90 degrees to the left can be read.
Image data rotated by 0" can be written. The vertical/horizontal switching signal H/V controls outputting or importing data rotated 90" to the right in accordance with the address value added as described above. and this signal H/V is “1”.
When the above-mentioned inversion control signal YINV is “1” and the inversion control signal It is possible to write image data rotated 90 degrees to the left on the back side of the disc.At the same time, when the vertical/horizontal switching signal H/V is "1", the inversion control signal YINV is "O", the inversion control signal XINV, and the data swap signal "1". Sometimes, it is possible to read image data by rotating the back side 90" to the right when the left and right sides are reversed, and it is also possible to write image data that is rotated 90" to the left from the back side when the left and right sides are reversed.In addition, the vertical/horizontal switching signal H/V reversal control Signal YINV, XINV data swap signal WS
When both are "1", image data rotated by 270 degrees to the right can be read, and image data rotated by 270 degrees to the left can be written.

By adding the desired value to the various signals mentioned above,
0° and 90° on the front and back screens when reading and writing
, 180°, and 270" images can be obtained. In Figure 6, the "=" symbol indicates other data, and most of the data is interchanged in units of 16 bits in the vertical or horizontal direction. The image data is as follows.

The embodiment of the present invention described above is a circuit that writes and reads rotation data in each of four directions on the front and back screens.

When rotating actual image data, the back screen is rarely used, and most of the rotation processing is performed on the front screen. FIG. 7 is a rotation configuration diagram of the third embodiment of the present invention, and shows the rotation in four directions (0°, 90°, 180°,
270°) rotated images can be read and written.

In the circuit configuration diagram of the embodiment of the present invention shown in FIG.
is provided on its input side, and exclusive OR group EORG3
．． The configuration is such that it is inverted by EORG4, and then inverted again to return to the original logic. The rotation configuration of the third embodiment of the present invention shown in FIG. 7 is a combination of this logic and a configuration in which the back side is not output. Note that the first aspect of the present invention in FIGS. 2 and 5. Circuits that operate in the same manner as in the second embodiment are designated by the same reference numerals and explanations will be omitted.

The rotation control signals FDIRQ and FDIRI rotate the stored basic image by 90° and 180° when reading.

270° counterclockwise rotation for reading and 90° for writing.

This is a signal that controls the state of writing by rotating clockwise by 180 degrees and 270'.

The rotation control signal FDIRQ is applied to selection terminals SEL of selectors SL3 to SL4. Address values YA7 to YA4 . are input to input terminals A and B of selector SL3. XA7~X
A4, and input terminals A and B of selector SL3 have address values XA7 to XA4. Since YA7 to YA4 are added, when this rotation control signal FDIRQ is '0'', selector SL3 selects the address values YA7 to YA7 applied to input terminal A.
Selector SL4 selects address values YA7 to YA4 to be applied to input terminal A and applies them to one input of exclusive OR groups EORG5 and EORG6, respectively. Since the rotation control signal FDIRI is applied to the other input of the exclusive OR group EORG5, when the rotation control signal FDIRI is aO'', the output of the selector SL3 is non-inverted, and when it is @1'', the output of the selector SL3 is is inverted and stored in frame memory M1 as address values YA7 to YA4.
5-Add to MO. The aforementioned rotation control signals FDIRQ and FDIRI are added to the input of exclusive OR EOR.

The output of selector SL4 is output to one input of exclusive OR group EORG6. Since the output of the exclusive OR EOR is added to the other input of the exclusive OR group IEORG6, the rotation control signals FDTRO and FDIRI are 61″, ′
The selected signal is inverted when it is "0" or "0" or "1", and is not inverted when it is at the same level like "0", "O!" or "1" or "1" (same logic), frame memory. Output to M15-MO. Figure 8 shows the rotation control signal F.
DIRI, FDIRQ and address values Y7~Y4, X3~
It is a figure showing the relationship of XO.

Rotation control signal FDIR1, FDIRO/l<O″.

mO”, address values Y7 to Y4 added to frame memories M15 to MO are input address values YA7 to YA4,
Address values X3 to XO are input address values YA7 to YA4
becomes. Rotation control signals FDIRI and FDIRQ are “0”
, when '1', address values Y7 to Y4 are address value Y
A7-YA4. Address values Y7 to Y4 are address values YA
7 to YA4 inversion value (- in Figure 8 above the symbol)
The zero rotation control signals FDIRI and FD are
When IRQ is "l"IIQ", address value Y7~Y
4 is the inverted value of address values YA7 to YA4, address value X
3 to XO are inverted values of address values YA7 to YA4.

Rotation control signals FDIR1 and FDIRQ are “1°,” “1”
When , address values Y7 to Y4 are address values YA7 to Y
Inverted value of A4, address values X3 to XO are address values YA
7 to YA4.

On the other hand, the rotation control signal FD r Rl is the exclusive OR group E
It is connected to one input of ORG7. The other input of the exclusive OR group EORC7 has an address value YA.
Since 3 to YAO are added, the output is non-inverted when the rotation control signal FDIRI is "0", and is inverted when it is '1', and is output as each address value YB3 to YBO of address decoder ADRR and decoder DRR. join.

Address decoder ADRR and frame memory M15-M
O connection, decoder and bit shift circuit BSC
The connections between the frame memos IJM15-MO and the bit shift circuit BSC are the same as those shown in FIG. 2 described above. Note that a rotation control signal FDIRQ is applied to the terminal S of the address decoder, and this signal causes the
Similarly to the above, the decoded data shown in FIGS. 3(al) and (b) are selected.

The bit shift circuit BSC and the data swap circuit WSC are connected, and the output of the exclusive OR EOR causes 1
It is determined whether the bits are selected on a pair-to-one basis, or whether the LSB and MSB sides are sequentially swapped, that is, swapped and selected in units of bit positions. Further, the read/write signal R/W is applied to the direction control terminals of the data swap circuits WSCI and WSC2, the direction control terminals of the bit shift circuits B5C0 to B5Cl5, and the read/write terminals of the frame memories M15 to MO. When the read/write signal R/W is 1", the data is switched.

Step circuits WSCI, WSC2 and bit shift circuit B5C0
-BSC15 is connected to frame memories M15 to M from an external device.
The direction is determined to send data to the O side, and data from the frame memories M15 to MO are taken in. Conversely, when the read/write signal R/W is O'', the frame memory M1
5-MO output the stored data, and the data swap circuits WSCI, WSC2 and the bit shift circuit determine the direction of the data output from the frame memories M15-MO to be output to an external device.

When the rotation control signals FDIR1 and FDIRQ are both O'', the inverted control signal YINV is output in the circuit shown in FIG.
, XINV, data swap signal WSS! l Direct/horizontal switching signal! (The state is the same as when both /V are "0". In other words, the address value Y7 of frame memories M15 to MO
~YO becomes address values YA7 to YAO, and address values X3 to XO become address values XA7 to XA4. Also,
Frame memory M15-MO input/output data D15-D
O is a bit shift circuit BSC which shifts address values YA3 to YAO in units of words (16 bits) to correspond to input/output data DB15 to DBO of the external device. Also,
Exclusive OR EOR for data swap circuit ws-ci
The output (“O”) is inverted by the inverter INV and becomes “1”.
”, so the input/output (data) DBO
~DB15 and input/output DDO-DD15 have a one-to-one correspondence. Therefore, memory access is similar to the basic memory arrangement shown in FIG.

Rotation control signals FDIRI and FDIRQ are “0”.

1'', address value Y7 as shown in FIG.
~Y4 is address value XA7~XA4, address value X3~
XO becomes YA7 to YA4. Then, the address values YA3 to YAO that are not inverted (“0” is added to the exclusive OR group) are added to the address decoder via the exclusive OR group EOR1, and the address values YA3 to YAO are added as shown in Figure 3). The address is decoded and added to the frame memory. Therefore, the frame memory M1 for vertical columns is sequentially stored from the upper right corner of the basic image.
5-MO is accessed. In addition, in this case, since the output (“1”) of the exclusive OR EOR is added to the terminal E of the data swap circuit WSC2, the input/output data DD1
5~DDO is the input/output data D of the bit shift circuit BSC
Corresponds to BO to DB15. As mentioned above, 16 bits for each column in frame memories M15 to MO are read out, and the read bit positions are 1 in order from bottom to top.
Since it constitutes a word, this data swap circuit W
The vertical relationship is reversed by SC2. This operation causes the rotation control signals FDIRI and FDIRQ to become '0''.
, 11'', the memory is accessed by rotating it clockwise. Therefore, when reading, it is possible to read data that has been rotated to the left, and when writing, it is possible to write data that has been rotated to the right.

Rotation control signals FDIR1 and FDIRO are 'II'.

When "Oo," as shown in FIG. 8, address values Y7-Y4 added to frame memories M15-MO are inverted values of address values YA7-YA4, and addresses MtY3-YO are added inverted values of address values YA7-YA4. That is, the Y coordinate address values YA7 to YA4 and the X coordinate address values XA7 to XA4 are both inverted and added to the frame memory.

At this time, 0'' is added to the terminal S of the address decoder ADRR, and the address values YA3 to YAO are also exclusive OR group EO.
Since the data is inverted and added at RG7, memory access is performed horizontally from the lower right end as shown in FIG. Decoder DR
Since inverted data is added to R, it is similarly shifted from the lower right end by the shift read for the horizontal row. In other words, the basic images are read out in the reverse order. When reading in the reverse order from the lower right end, the 16 bits of one word are in the bit order in which the basic image was read, so at this time "1" is added to terminal E of the data swap circuit WSC2, and the MSB and LSB of the bits are It's the other way around. As a result, the data is read in 16-bit units horizontally from the lower right corner, and the bit positions are inverted between MSB and LSB.
Writing and reading are performed by rotating the basic image by 180 degrees (clockwise rotation and counterclockwise rotation are the same).

When the rotation control signals FDIRI and FDIRQ are both 11'', the frame memories M15 to M15 as shown in FIG.
Address values Y7 to Y4 added to MO are address value XA7
The inverted values of ~XA4, address values X3~XO, become address values YA7~YA4. Also, the exclusive disjunction group EOR
Since “1” is added to one input of G7, the address value Y
A3 to YAO are also inverted and the address decoder AD
It joins RR and decoder DRR. address decoder AD
Similarly, 11" is added to the terminal S of RR, so different address values are added to the lower addresses Y3 to YO for each frame memory M15 to MO, as shown in FIG. 3(b). The access results in an access to the memory corresponding to the vertical column from the lower left edge.At this time, this access is exactly the same as reading upward from the lower left edge of the basic image.Furthermore, the focus shift circuit BSC also uses the inverted address values YA3 to YAO. Therefore, the shift amount when sequentially reading is changing. At this time, 11" is added to the terminal E of the data swap circuit WSCI, so the bit shift circuit BSC
The input/output (data) DI315 to DBO correspond to the input/output DD15 to DDO of the external device. by this,
Reading and writing in the vertical direction is performed sequentially in 16-bit units starting from the lower left end. That is, in other words, reading by rotating 270 degrees to the left and writing by rotating 90 degrees to the right are performed.

FIG. 9 is a display example of a rotated image obtained by reading or writing to a memory according to an embodiment of the present invention. For example, the seventh
As shown in the figure, rotation control signals FDrR1, FDIRQ
(a) “O” respectively.

O", (b) O", 11'", (e) "1", '0",
(Write as d+"1", "1'", rotation control signal F
When both DIRI and FD r RO are read as 10'', the 0°+90 shown in FIG. 9 (al~(d+)
” It is possible to obtain image data rotated clockwise by +180°3270°.This rotation is performed not only during writing (the rotation control signal FDIRI is also applied during reading).

A similar rotated image can be obtained by varying FDIRQ. Note that when reading, the angles are 90" and 180° relative to the basic image, respectively, contrary to when writing.

Image data rotated 270 degrees to the left is obtained. Also, the rotation control signal FD I R1゜FDI when adding the basic image
When RQ is not set to O" or "0'", the value of the rotation control signal FD f R1° FDIRQ when the basic image is added becomes the basic image storage position.
The same applies to the embodiment of the present invention shown in the figure.

The memory arrangement of the present invention and the circuit for driving the memory have been described above using embodiments. However, the present invention is not limited to the memory arrangement shown in FIG. It is also possible to arrange by shifting in units of odd numbers, such as shifting in units of bits, or assigning in other random number arrangements.

For example, if the data is divided into 16 bits and 7 bits in the vertical and horizontal directions, then the divided 16 x 16 bit area is divided into random numbers so that there are no identical bits when read in units of 16 bits in the vertical and horizontal directions. Note that in this case, address decoder ADRR and decoder DRR should also be arranged in the same way to perform random number decoding.

In the embodiment of the present invention, the horizontal and vertical addresses are selected by the selector and added to the memory, but the invention is not limited to this.
For example, by adding horizontal and vertical addresses to the address decoder and selecting and adding address decoder values using the vertical/horizontal switching signal H/V, it is possible to access the memory in the horizontal and vertical directions in the same way. Become.

〔Effect of the invention〕

As described above, the present invention stores bits in units of addresses as addresses, and assigns bits to frame memory for multiple dots of n×n dot image data to correspond to horizontal rows or vertical columns. According to the present invention, a plurality of target dot data can be stored by shifting the data by one dot. An image memory can be obtained in which it is possible to similarly store and read out images.

[Brief explanation of drawings]

FIG. 1 is a memory layout diagram of the present invention, FIG. 2 is a circuit configuration diagram of the first embodiment of the present invention, and FIG.
a) and (b) are address decoder input/output data diagrams, Figure 4 is a memory layout diagram during access, Figure 5 is a circuit configuration diagram of the second embodiment of the present invention, and Figure 6 is a read/write diagram. FIG. 7 is a circuit diagram of the third embodiment of the present invention; FIG. 8 is a diagram showing the relationship between rotation control signals and address values; FIG. al is image data without rotation, Fig. 9(b)
is image data rotated clockwise by 90 degrees, and Fig. 9 (C) is image data rotated 180 degrees.
Image data rotated to the right; FIG. 9+d) is image data rotated clockwise by 270°; FIG. 10 is a diagram illustrating storage of data in a conventional memory. EORGl ~EORG7- ・-Exclusive OR group, S
LI~SL, 4...Selector, DRR...Decoder, BSC (BSCO-BSCI 5)...Bit shift circuit, ADRR...Address decoder, M15~MO...Frame memory, CHG... Image memory, INV...Inverter, WSC (WSCI, WSC2)...Data swap circuit. Patent Applicant Casio Computer Co., Ltd. Same as above Casio Electronics Co., Ltd. 4 images of X-print book slip (×K) Map of the back of Honfu Town Figure 1 12 squares of Kirin-cho 16 times of flea Illustration 8 of spears, illustration 5, relation 4 illustration
Chi Esu 1 Sij Hook Elephant, Take (a)
(b) Image rescuer of lδO0 stone rotation 2g. , turn right d town. Picture image... (c)
((j) Figure 9

Claims (1)

[Scope of Claims] 1) In a memory that stores a plurality of dots of n×n dots of image data in units of one address, the memory corresponds to at least one of a horizontal row or a vertical column of dots of the image data. An image memory characterized in that at least one of a horizontal row or a vertical column of the memory is sequentially shifted by one dot and stored. 2) The image memory according to claim 1, wherein the shift rotationally shifts the image data in units of a plurality of dots. 3) a memory that stores n×n dots of image data in units of one address; An image memory comprising: a shift circuit for shifting data in at least one of a horizontal row or a vertical column and adding the shifted data to the memory. 4) The shift circuit adds at least one of the horizontal row address or the vertical column address of the dots of the image data, and adjusts the image of the plurality of dots according to at least one of the vertical column address or the horizontal row address. 4. The image memory according to claim 3, wherein data is shifted.