JPS62249284A - memory drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory, and more particularly to an image memory for storing image data.

[Traditional technique]

The development of microprocessors has made it possible to perform complex processing of image data. For example, rotation in the displayed image of the obtained figure can be mentioned.

For example, in the image data of the above-mentioned figure, the white and black of each dot are set to 0.
This is 1-bit data represented by "" or "1", and is stored in memory in units of multiple dots (if the dot has color or gradation, multiple bits are assigned to one dot).
Figure 0 is a block diagram of a memory that stores image data (256 dots x 256 dots). One address is one word (
16 dots are stored in the horizontal direction (X-direction image) of the image, and 1 dot is stored in the vertical direction (Y-direction image) as one word, corresponding to the position of the image. The image is divided into 16 dots to the right of the upper left dot, and the data of the 16 dots (16 bits) is stored in the image address "0OOH', and the next 16 dots on the right side are stored in the image address XG "00111".

Since there are 256 dots in the horizontal direction, 16 addresses (the lowest 4 bits of the address) are the addresses for one row. Then, the Y-direction image address (YG) is stored in rows of one dot as "0OOH" to "0101", etc. (H in "" represents hexadecimal).

Conventionally, when reading data stored in the above-mentioned memory, addresses 000... Address 001...Address 0
By reading in the order of 10, address 021...
It is possible to obtain image data in the normal position, that is, unrotated image data (when not rotated).

On the other hand, for example, 90 degrees from the position when displayed on the display screen.
When obtaining right-rotated image data, the bit corresponding to one dot on the lower left side is read upward. That is,
If the MSB (B15) of the 16 bits is placed on the left side of the display screen, 16 words from address FFO to address FOO are sequentially read out, and each dot 15 of the 16 words is read out sequentially.
(B15) is configured as one word, and the obtained one word is one word (address 000) at the upper left on the screen.

Next, 16 words from address EFO to address EOO are read out, and each bit 15 (
B15) as one word and the next one word (address 00
1). After reading out one vertical column, 16 words at the same addresses FFO to FOO are read out, and bit 14 (B14) of the 16 words is set as one word. After further 16 columns have been read, one word is similarly read from bit 15 (B15) of 16 words of addresses EFO to EOO. By reading out 16 words and selecting 1 bit in this manner, image data rotated to the right by 90 degrees is obtained.

[Problems with conventional technology]

In the conventional 90° rotation described above, although data is read in units of one word, one bit of data within one read word becomes a valid bit. In other words, 15 bits out of the 16 bits read are invalid data. Further, when writing, the 16-bit data for writing is divided into 1-bit units, and 1 word at the target position is read out, 1-bit conversion is performed, and the data is written again. In other words, although it has 16-bit read and write functions, the processing within it is only 1
This is done using bits, which has the problem of slow processing. Particularly in writing, since the data is read once and then written, there is a problem in that it takes additional processing time.

Directly access the memory described above sequentially in the horizontal direction, and
In the case of outputting the video signal to a display device such as T, etc., memory access is performed using a circuit that operates as described above. However, the read speed in the horizontal direction and the read speed in the vertical direction are different, and the processing of the obtained word in units of dots is different (in the horizontal direction, a parallel in-serial out register is used each time one word is read out). (in the vertical direction, the target bit is selected and output every time one word is read out), which has the problem of complicating the circuit.

[Purpose of the invention]

In view of the above conventional drawbacks, the present invention provides an image memory that simultaneously outputs a plurality of targeted dot data both when accessing the memory from the horizontal direction and when accessing the memory from the vertical direction. The purpose was to.

[Key points of the invention]

In order to achieve the above object, the present invention has m memories each having an input/output terminal corresponding to one dot of nxn dot image data and storing at least (nxn)/m dots, and a row address. and at least a portion of the column address in the vertical direction and add the decoded data to the memory.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a memory layout diagram of the present invention. In the figure, the upper part of the box corresponding to each dot represents a memory address, and the lower part represents a focus position within that address. The Y coordinate (Y K) of the basic image is "OO" and the X coordinate (X K) of the basic image is "OO".
) is 00, it is assigned to bit 15 (Di5) of memory address ADD "0000". Then, the basic image is sequentially stepped in the X-coordinate (XK) direction by 16 addresses (FH: H is hexadecimal) in 16-bit units, and the dots in between are focused from 15 to 0 (D15 to DO).
is assigned to. Also, the Y coordinate (YK) of the basic image is “01”
”, the horizontal line of the basic image corresponding to the Y coordinate (YK) of the basic image is expressed in units of 1 word.
The dot correspondence when YK) is "00" is shifted by one bit. In other words, if the Y coordinate (YK) of the basic image is "01", the address ADD is "0100".
Bit O (MO) of , and bits 15 to the right of it
It is constructed by shifting bit 1 (D15 to DI) by one bit. Further, each time the Y coordinate (YK) address of the basic image increments, it is shifted by 1 bit in units of 16 bits.

In other words, the Y coordinate (YK) of the basic image is 100''
When , bits 15 to pin 0 (DI5 to DO) of address ADD "oooo", address ADD "0001"
bits 15 to 0 (DI5 to DO), address A
Bits 15 to 0 of DD “0002” (DI5 to D
O)..., and the Y coordinate (YK) of the basic image is 0.
When it is 1'', bit O(
DO) Then bit 15 to bit 1 (D15 to D1)
, bit 0 (Do) of address 0101, followed by bits 15 to 1 (015 to D1), bit O (DO) of address 0102, and so on. Furthermore, when the Y coordinate (YK) of the basic image is "02", address A
Bit 1.0 of DD'0200 (Di・
~Do) Continued with Bit 15~Pitsu) 2 (D15~D2
) Bit 1 of address ADD ``0201''''. O(Di
, Do), followed by bits 15 to 2 (DI5 to D
2) In order to sequentially increment the Y coordinate of the basic image as shown in FIG.

Due to the above-mentioned allocation, when a basic image is read in units of 16 bits in the horizontal and vertical directions, the bit values (D15 to DO) within the 16 bits are always different. This allows vertical and horizontal access in units of 16 bits. Note that in the horizontal direction, the same address is accessed, and in the vertical direction, different memories are accessed bit by bit.

FIG. 2 is a circuit diagram of the first embodiment of the present invention. Each frame memory (M15 to MO) has a 1-bit input/output terminal I10, and has 16-bit data (D15 to D10).
It constitutes a memory that inputs and outputs O). Note that the number of diagonal lines in the connecting portion in the figure represents the number of bits. Each frame memory M15~MO has an address value (Y7~YO, X3~XO
) is added to the address input terminal, and the block value (B L
K6 to BLKO) are added to the block input terminal.

The frame memory (M15 to MO) has the capacity to store multiple screens, and the terminal for specifying the multiple screens is
This is a block input terminal to which block values (BLK6 to BLKO) are added. This block value (BLK6~BLKO)
The target block, ie, the page of the screen, is specified by .

Upper via of Y coordinate (YK) of basic image) (YK7 to YK
4) and the upper 4 bits (XK7 to XK4) of the X coordinate XK are input terminal A of selector SLI and selector SL2, respectively.
, input terminal B of selector SLI, and input terminal A of selector SL1. Selector SLI, SL2
selects the data applied to input terminals A and B and outputs it to output terminal C.
This is a circuit that outputs data to the selection terminal S.
It is determined by the vertical/horizontal switching signal H/V applied to EL. When the vertical/horizontal switching signal H/V is at the L level "0", selectors SL1 and SL2 select the data applied to the input terminal A and output it to the output terminal C, and vice versa when the I■ level is "1". Data added to B is selected and output to output terminal C. In the following, first, the case where the selection signal H/V is an L level signal will be explained. At this time, the aforementioned selector SLI selects the top 4 focal points Y of the Y coordinate of the basic image.
Select K7 to YK4, selector SL2 is X of the basic image
The upper 4 bits of the coordinates XK7 to XK4 are selected and output to each output terminal C.

Output terminal C of selector SLI is exclusive OR group EORG
The upper 4 bits of the basic image YK selected through 2
~YK4) as signals YS3~ys.

As frame memory M15~MO address value Y7~
Output to the terminal to which Y3 is applied. Exclusive OR group EORG
Since the vertical/horizontal switching signal H/V is applied to one input of the selector SL1, the exclusive OR group EORG2 operates as a buffer, and the output logic of the selector SL1 is not inverted.
It is added to the terminals of the frame memories M15 to MO mentioned above.

The output terminal of selector SL2 transfers the upper 4 bits (XK7 to XK4) of the selected basic image XK to frame memory M1.
The address values X3 to XO of 5 to MO are output to the terminals to which they are applied. On the other hand, the lower 4 bits of the Y coordinate (YK) of the basic image (
YK3~YKO) are input to the decoded input value Y of ADRR of the address decoder via exclusive OR group EORG1.
It is applied to a terminal to which YAQ is applied and a terminal to which decoded input values YB3 to YBO of decoder DRR are input. One gate of the exclusive OR group EORG1 receives a vertical/horizontal switching signal H/
V is added, and the other is the basic image address YK.
The lower 4 bits (YK3 to YKO) are added. Therefore, when the vertical/horizontal switching signal II/V is at L level, the exclusive OR group EORGI operates as a non-inverting circuit, that is, a mere buffer.

The address decoder ADRR is the exclusive OR group E mentioned above.
In addition to the output of ORG1 being added as address values YB3 to YBO, the vertical/horizontal switching signal 1 (/V is added to the address decoder A
These signals are applied to the terminal S of the DRR, and these signals cause a specific decode value QF3 to QF to be applied to the lower 4 bits of the terminal to which the address values Y7 to YO of the memories M15 to MO are applied.
O, . . . outputs Q03 to QOO.

FIG. 3 is an input/output data chart of address decoder ADRR. FIG. 3(a) shows the vertical/horizontal switching signal when the vertical/horizontal switching signal H/V is at L level (that is, H/V=O), and FIG. 3(b) shows the vertical/horizontal switching signal! (This is a diagram of each input/output data when /V is at H level (H/V=1).As mentioned above, when the vertical/horizontal switching signal H/V is L, the output is as shown in Figure 3+8) The data is determined and each frame memory M15~
Address values Y3 to YO added to MO, that is, each decode output QF3 to QFO□...QO3 to QOO are the same as decode input values YB3 to YBO and are added to frame memories M15 to MO.

Each value mentioned above (block value 86 to BO and address value Y7
~YO, X3-XO) are added to the frame memories M15-MO, each frame memory M15-MO outputs or inputs data DI5-DO corresponding to the value. In addition, a read/write signal R/W is added to each frame memory M15 to MO in addition to the above-mentioned one, and when this read/write signal R/W is at L level, a read operation is performed, and when it is at an H level, a write operation is performed, and each memory M15 ~MO becomes.

In other words, when it is at L level, it outputs the stored data,
When the level is H, data to be added is input. Address values Y7 to YO and X3 to XO are the same as accessing 16 bits in the horizontal direction in FIG. F, and for example, when reading, 16 bits in the horizontal direction are read simultaneously.

As shown in FIG. 1, in the embodiment of the present invention, the 16 bits in the horizontal direction are always shifted by 1 bit in the vertical direction. Correcting this shift,
The bit shift circuit BSC sets the position corresponding to the X and Y coordinates of the basic image to be added. This bit shift circuit BSC transfers data DB15 corresponding to the position.
~DI30 can be obtained.

The output of the exclusive OR group EORG1 of YK3 to YKO described above is added to the decoder DRR.

When the vertical/horizontal switching signal H/V is at the L level, this exclusive OR group EORGI is not inverted, that is, it operates as a buffer, so the decoder DRR receives the Y coordinate (Y
K)'s bottom four pits) (YK3 to YKO) will be added. Decoder DRR is the added value (address value) YB3 to YBO
This is a circuit that decodes the . For example, when the 4-bit address value YB3 to YBO is "0000", the output SDO is I", the others are "0", and when it is "0001", the output SDI is 1", and the others are 0. Only the output corresponding to the value was set to 1''. On the other hand, the bit shift circuit BSC is a 16ftM bit shift circuit B5C0-B.
5Cl5, and is configured to have a shift amount corresponding to the decoded value described above. In other words, bit shift circuit B5C0 is O-shifted (input/output (data) D15
~Do corresponds to input/output DB15~DBO on a one-to-one basis), in the bit shift circuit B5Cl, input/output (data) DO corresponds to input/output DB15, input/output (data) D15~D1 corresponds to input/output DB14~DBO, Similarly, the bit-node shift circuits ESC2 to B5Cl3 respond by shifting sequentially.

This bit shift circuit BSC allocates positions corresponding to the dots in each of the frame memories M15 to MO shown in FIG. In addition, the bi-nod shift circuits B5C0 to B
Each of the 5Cls 5 is composed of 16 bidirectional buffers, and the shift hi described above is determined by the connections of the bidirectional buffers, and its direction is controlled by the read/write signal R/W.

Due to the operation described above, the vertical/horizontal switching signal H/V becomes L.
At the level ("O"), the dots are arranged as shown in FIG. 4, and the data in the memory arrangement shown in FIG. 1 can be accessed by accessing from the outside. Note that output is performed in units of 16 bits, so the lower 4 bits of the X coordinate (XK) of the basic image,
3~XKO is not necessary.

Next, the case when the vertical/horizontal switching signal H/V is at H level will be explained. At this time, first selectors S and LL.

SL2 selects data input from input terminal B and outputs it to output terminal C. That is, the output terminal C of the selector SL1 has the upper 4 bits XK7 to X of the X coordinate XK of the basic image.
K4 is output. This output is the exclusive OR group EORG
However, at this time, since the H level of the vertical/horizontal switching signal H/V is applied to one input of the exclusive OR group EORG2, it is selected by the selector SLI and the output terminal C
The upper 4 bits of the Xi mark XK of the basic image output from
K7-XK4 are reversed or inverted. Due to this reversal operation, the address values Y7 to Y4 of frame memories M15 to MO are changed to the upper four bins 1 to XK of the X coordinate of the basic image.
It becomes the inverted value of 7 to XK4. For example, when accessing from the upper left corner to the right, such as when accessing a basic image, F is sequentially accessed.

El...The input changes as O, E, F,...0...0. On the other hand, the lower 4 bits (YK3 to YKO) of YKURA YK in the basic image are included in the exclusive OR group EORGI, and one input of this exclusive OR group BORCI is also supplied with a vertical/horizontal switching signal as described above. H/V has been added. Therefore, by this exclusive OR group EORGI, the lower 4 pis of Y coordinate YK of the basic image 1-YK 3~YK
O is inverted and added to address decoder ADRR and decoder DRR as address values YB3 to YBO. The address decoder ADRR switches the output data using the vertical/horizontal switching signal H/V, converts the address values YB3 to YBO, and stores the decoded values QF3 to QFO in each frame memory M15 to MO as shown in FIG. 3(b). ...QO
3 to output QOO. For example, when the upper left end of the basic image is accessed, the lower 4 bits YK3 to YKO of the Y coordinate YK of the basic image are inverted ("1111") by the exclusive OR group EORC;1 and added to the address decoder.

When “1111” is added, the address decoder ADR
R is oooo'' for each frame memory M15 to MO.
, "1111", "1110", "0111"
.

"0110", "0101", "0100", "0"
011”.

Add “oooi”. In addition, the selector SL2 selects the top four points (YK7 to YK4) of the Y coordinate YK of the basic image and sets the dot values X3 to xO of the frame memories M15 to MO.
Therefore, when the upper left corner mentioned above is accessed, FOOH is added to frame memories M15 to MO respectively.
, FF0H-FIOH (H represents hexadecimal. H is omitted in the figure) are added. Frame memory M
This address value Y7~YO, X3~XO to 15~MO
By adding 16 bits of data upward from the lower left end in FIG.
~Output from MO. This data is 16 bits of data from the lower left end of the basic image to the upper side, but the order is shifted. The bit shift circuit BSC corrects this and operates during D14 to DO1D15 as shown in FIG. As mentioned above, when the vertical/horizontal switching signal H/V is at a high level, the lower 4 bits of the Y coordinate YK of the basic image are inverted by the exclusive OR group EORGI and added to the decoder DRR (YB3 to YBO), so that the bit The decode output 5D15 connected to the shift circuit B5Cl5 becomes H level and the bit shift circuit B
The H level is applied to the enable terminal E of SC to operate the bit shift circuit B5Cl3. This bit shift circuit B
5Cl 50 input/output (data) D15 corresponds to input/output DBO, input/output (data) DO-D14 corresponds to input/output DBI
Since the bit shift circuit B5Cl3 corresponds to DB15 to DB15, the input/output DB15 to DBO correspond to 16 bits sequentially cut out above the lower left end of the basic image. Then, the top 4 of the X coordinates XK of the basic image
When the bits change sequentially, the frame memories M15 to MO are sequentially read out toward the edge in the same manner as described above, and a specific bit is shifted by the bit shift circuit BSG.

In the embodiment of the invention shown in FIG. 2, the bit shift circuit BSC is a bidirectional buffer whose direction changes with the read/write signal R/W.

Therefore, the X coordinate of the basic image mentioned above and the Y coordinate of the basic image
When coordinates are added and the memory is accessed, when the read/write signal R/W is at L level, the frame memory M15
~ MO read and write when at H level. Also, since access is performed in the vertical direction or in the horizontal direction depending on the vertical/horizontal switching signal H/V, when the vertical/horizontal switching signal H/V is at L level, reading and writing are performed without rotating to the normal position. When the vertical/horizontal switching signal H/V is at H level, it is possible to obtain data in which the basic image is rotated to the right during reading. Furthermore, during writing, data rotated 90° to the left with respect to the data written when the vertical/horizontal switching signal H/V is at L level is written in the frame memory.

Through the above operations, image data rotated 90 degrees to the right can be read by the L level of the vertical/horizontal switching signal H/V, and image data rotated 90 degrees to the left can be written by the H level. Furthermore, 16 bits can be obtained simultaneously in both directions with one write or read operation, making memory access faster than in the past.

FIG. 5 is a circuit diagram of a second embodiment of the present invention. Image memory CHG has a circuit similar to the circuit configuration shown in Fig. 2, and block values BLK5 to BLKO1 vertical/horizontal switching signal H/V, address values Y7 to YO, X3 to XO, and read/write signal R/W. When reading, data DB15 to 'DBO are output, and when writing, data D is output.
It has terminals to which B15 to DBO are input.

In the circuit configuration shown in Fig. 2, the image memory CHG reads data rotated 90 degrees to the right with respect to the basic image, and
Only rotated data could be written.

The circuit in Fig. 5 is a step of +90'.
, 180", 270" clockwise rotation (270',
180'.

This circuit makes it possible to successively print and write basic images that have been rotated 90 degrees to the left.If an image that has been rotated by ±90 degrees can be obtained, the address value of the image memory CHG is inverted and the image can be written as needed. Swap bits of data (MSB
By exchanging all bits of the LSB and LSB), it is possible to obtain an arbitrary rotated image or reversed image.

The exclusive OR group EOR performs the inversion of this address value.
G3. EORG4 is a data swap circuit WSC that performs data bit swapping.

The inversion control signal YINV is applied to one input of the exclusive OR group EORG3, and the address values YA7 to YAO of the Y coordinate are applied to the other input. Inverted ff1grI signal YI
NV is “l”, that is! Address value Y at f level
A7 to YAO are inverted and added to the image memory CHG as an address value YK. Also, the inversion control signal YINV is “O”.
``In other words, when the output is at the L level, the output is not inverted (the logic is not inverted) and the address values YA7 to YAO are directly added as the address value YK of the image memory CIfG.

The inversion control signal XINV is applied to one input of the exclusive OR group EORG4, and the X coordinate address values XA7 to XA4 are applied to the other input (upper 4 bits only; lower 16 bits are not necessary as they are read in parallel. ) is added. When the inversion control signal XINV is “1”, the address values XA7 to X
A4 is inverted and the address value XK is added to the image memory CHG. Further, when the inversion control signal XINV is "O", its output is non-inverted, and the address values XA7 to XA4 are directly added as the address value XK of the image memory CHG. Y.A.O.

Image memory C by inverting or non-inverting XA7 to XA4
Can be added to HG.

On the other hand, the data swap circuit WSC has 2-phase bidirectional buffers WSCI and WSC2 in units of 16, and has 3 bidirectional buffers WSCI and WSC2.
The 771st group WSCI is the input/output DB1 of the Wi image memory CHG.
5 to DBO are connected corresponding to data DD15 to DDO. Further, the bidirectional buffer group WSC2 transfers the data DBO to DB15 of the Ii image memory CHG to the data DD15.
- Connected in accordance with DDO. Bidirectional buffer group W
A data swap signal WS is applied to an input terminal E (terminal for controlling operation) of the SCI via an inverter INV, and a data swap signal ws is directly applied to the first group of bidirectional pamphlets WSC2. Each bidirectional buffer group WS
C.I.

WSe2 operates when '1' (H level) is applied to the enable terminal E, so when the data swap signal is '1', the input/output DB15 to image memory CHG
DBQ and data DD15 to data DDO are made to correspond, that is, the data is swapped up and down in bit units, and “
When it is 0'', input/output is controlled in one-to-one correspondence.

Note that the bidirectional buffer groups WSCI and WSC2 have read and
A write signal R/W is added, and when reading (10'') data DB15~DBO is transferred to data DD15~DD.
0 or data DDO to DD15, and at the time of write (11''), data DD15 to DDO are added to the image memory CHG in correspondence to data DB15 to DBO or data DBO to DB15.

Figure 6 shows the vertical/horizontal switching signal H/V and the inversion control signal YIN.
77 is a chart showing the positional relationship between an image obtained during reading and an image written during writing in data bus signal ws.

In addition, the rotation operation at the time of reading uses the position state of the image read when the missionary basic image is written, and the written data at the time of writing, using the signals VINV, XINV, and WS.
, H/V are both in the "o" state. First, the vertical/horizontal switching signal H/V is “O”.
” 0 inversion control signals YINV, XINV
.

When both the data swap signals WS are 60'', a normal basic image can be obtained during reading and writing, and writing can be performed.In other words, it is possible to read and write data that does not rotate.On the other hand, inversion control Signal YrNV is “l”
At this time, the address values YA7 to YAO are inverted by the exclusive OR group EORG3, so that an upside-down back image is obtained both during reading and writing. In addition, when writing, when the basic image in the normal position is written, the image on the back side of the upper and lower roads can be read, and conversely, when the basic image is input, the upside down back side of the basic image can be written. Can be done.

When the inversion control signal YINV is “O”, the inversion control signal XINV
When the data swap signal WS is "1", writing and reading can be performed on the reverse side of the left and right sides. inverted control signal YINV,
When XINV and data swap signal WS are all "1", the X and Y coordinates are reversed horizontally and vertically, and the data is swapped by the data swap signal, so when reading and writing, the basic image rotated by 180 degrees is read. You can publish and write again.

On the other hand, when the vertical/horizontal switching signal H/V is "1" and the other signals YINV, XINV, and WS are all "0", data rotated 90" to the right can be read,
Image data rotated by 0° can be written. As mentioned above, the vertical/horizontal switching signal H/V controls outputting and importing data rotated 90 degrees to the right in response to the applied address value, and when this signal H/V is "1",
”, when the inversion control signal YINV is “1” and the inversion control signal It is possible to write image data rotated 90” to the left on the back side of the disc. At the same time, when the vertical/horizontal switching signal H/V is “1”, the inversion control signal YINV is “O”, the inversion control signal Get it out.
In addition, image data rotated 90 degrees to the left on the back side with the left and right sides reversed can be written. Furthermore, when both the vertical/horizontal switching signal H/V inversion control signal YINV and the XINV data swap signal WS are "1", image data rotated by 270 degrees to the right can be read, and image data rotated by 270 degrees to the left can be written. .

By adding the desired value to the various signals mentioned above,
0° and 90° on the front and back screens when reading and writing
, 180°, and 270° rotated images can be obtained. Note that "-" in the operation column in FIG. 6 indicates data other than this, and most of it is image data in which data is exchanged in units of 16 bits in the vertical or horizontal direction.

The embodiment of the present invention described above is a circuit that writes and reads rotation data in each of four directions on the front and back screens.

When rotating actual image data, the back screen is rarely used, and most of the rotation processing is performed on the front screen. FIG. 7 is a rotation configuration diagram of the third embodiment of the present invention, and shows the rotation in four directions (0", 90", 180") of the surface.
270”) can be read and written.

In the circuit configuration diagram of the embodiment of the present invention shown in FIG.
is provided on its input side, and exclusive OR group EORG3
．． The configuration is such that it is inverted by EORG4, and then inverted again to return to the original logic. The rotation configuration of the third embodiment of the present invention shown in FIG. 7 is a combination of this logic and a configuration in which the back side is not output. Note that the first aspect of the present invention in FIGS. 2 and 5. Circuits that operate in the same manner as in the second embodiment are designated by the same reference numerals and explanations will be omitted.

Rotation control signals FDIRQ and FDIRI rotate the stored basic image by 90° and 180° during rotation.

Rotate 270 degrees to the left for reading and 90 degrees for writing.

This is a signal for controlling the writing position by rotating clockwise by 180 degrees and 270 degrees.

The rotation control signal FDIRQ is applied to selection terminals SEL of selectors SL3 to SL4. Input terminals A and B of selector SL3 have address values YA7 to YA4. XA7～
Since the address values XA7 to XA4; YA7 to YA4 are applied to the input terminals A and B of the selector SL3, when the rotation control signal FDIRQ is "O", the selector SL3 selects the address value applied to the input terminal A. YA
7 to YA4, and selector SL4 selects address values YA7 to YA4 to be applied to input terminal A to form exclusive OR groups E and ORG5, respectively.

Add to one input of EORG6. exclusive disjunction group EO
Since the rotation control signal FDIRI is added to the other input of RG5, this rotation control signal FD I R1 is “O”.
”, the output of selector SL3 is not inverted, and when it is “1”, the output of selector SL3 is inverted, and the address value YA
7 to YA4 to the frame memories M15 to MO. The input of exclusive OR EOR is the rotation control signal F mentioned above.
DIRQ and FDIRI have been added.

The output of selector SL4 is output to one input of exclusive OR group EORG6. Since the output of the exclusive OR EOR is added to the other input of the exclusive OR group EORG6, the rotation control signals FDIRQ and FDIRI are "1" and "O".
When it is ``or 0'' or ``1'', the selected signal is inverted, and when it is at the same level as 0'' or ``1'' or 1'', it is not inverted (the same logic) and output to frame memories M15 to MO. Figure 8 shows the rotation control signal FD.
IR1, FDIRQ and address values Y7~Y4, X3~X
It is a figure showing the relationship of O.

Rotation control signals FDIR1 and FDIRQ are @θ″.

0'', the address values Y7 to Y4 added to the frame memories M15 to MO become the input address values YA7 to YA4, and the address values X3 to XO become the input address values YA7 to YA4.The rotation control signals FDIR1 and FDIRQ are "0",
“When 11, address values Y7 to Y4 are address values YA
7~YA4. Address values Y7 to Y4 are address value YA7
~YA4 is the inverted value (- is added above the symbol in FIG. 8). Rotation control signal FDIRI, FDI
When RQ is "1" or 10", address values Y7 to Y4 are inverted values of address values YA1. to YA4, and address value X3.
~XO is the inverted value of the address values YA7 to YA4. When the rotation control signals FDIR1 and FDIRQ are 1'' and '1'', the address values Y7 to Y4 are the address values YA7 to YA4.
The inverted value of address value X3~XO is the address value YA7~
It will be YA4.

On the other hand, the rotation control signal FD I R1 is the exclusive OR group E
It is added to one input of ORC7. The other input of the exclusive OR group EORG1 has an address value YA.
Since 3 to YAO are added, the output is non-inverted when the rotation control signal FDIRI is O'', and is inverted when it is 1'', and is added as each address value VB3 to YBO of address decoder ADRR and decoder DRR.

Address decoder ADRR and frame memory M15-M
O connection, decoder and bit shift circuit BSC
The connection between the frame memo IJM15~MO and the bit shift circuit BSC is made using the aforementioned second rI! J
The connection is similar to that of . A rotation control signal FDTPO is applied to the terminal S of the address decoder, and this signal selects the decoded data shown in FIGS. 3(a) and 3(b) in the same manner as described above.

The bit shift circuit BSC and the data swap circuit WSC are connected, and the output of the exclusive OR EOR causes 1
It is determined whether the bits are selected on a pair-to-one basis, or whether the LSB and MSB sides are sequentially swapped, that is, swapped and selected in units of bit positions. Further, the read/write signal R/W is applied to the direction control terminals of data swap circuits WSC1 and WSC2, the direction control terminals of bit shift circuits B5C0 to BSC15, and the read/write terminals of frame memories M15 to MO. Read/write signal R
When /W is “1”, data swap circuit WSC1,W
The direction of SC2 and bit shift circuits B5C0-B5Cl5 is determined so as to send data from the external device to the frame memories M15-MO side, and take in the frame memories M15-MO data. Conversely, the read/write signal R/
When W is "01", the frame memories M15 to MO output the stored data, and the data swap circuits WSC1 and WSC2 and the bit shift circuit output the data output from the frame memories M15 to MO to the external device. determine the direction.

When both rotation control signals FDIR1 and FDIRQ are "0", in the circuit shown in FIG.
The state is the same as when V, XINV, data swap signal WS, and vertical/horizontal switching signal H/V are all "0". That is, address values Y7 to frame memory M15 to MO
YO becomes the address value YA7 to YAO, and the address value X
3 to XO become address values XA7 to XA4. In addition, input/output data DI5 to DO of frame memories M15 to MO
are shifted by the address values YA3 to YAO in units of words (16 bits) by the bit shift circuit BSC to correspond to the input/output data DB15 to DBO of the external device. In addition, since the output ("0') of the exclusive OR EOR is inverted by the inverter INV and added to the data swap circuit WSCI as "1", the input/output (data) DBO-D
B15 and input/output DDO to DD15 have a one-to-one correspondence. Therefore, memory access is similar to the basic memory arrangement shown in FIG.

Rotation control signal FD1. R1 and FDIRQ are “0”.

1'', address value Y7 as shown in FIG.
~Y4 is address value XA7~XA4, address value X3~
XO becomes YA7 to YA4. Then, address values YA3 to YAO that are not inverted (“0” is added to the exclusive OR group) are added to the address decoder via the exclusive OR group EORI, and the result is shown in FIG. 3(b). The address representing is decoded and added to the frame memory. Therefore,
Sequential edges from the upper right of the basic image - frame memory M of the device
15 to MO are accessed. In addition, in this case, since the output (1'') of the exclusive OR EOR is added to the terminal E of the data swap circuit WSC2, the input/output data DD1
5~DDO is the input/output data D of the bit shift circuit BSC
Corresponds to BO to DB15. As mentioned above, 16 bits for vertical columns in frame memories M15 to MO are read out, and the read focus positions are 1 in order from bottom to top.
Since it constitutes a word, this data swap circuit W
The vertical relationship is reversed by SC2. As a result of this operation, the rotation control signals FDIR1 and FDIRQ become 0'',
When the value is 1'', the memory is accessed by rotating 90 degrees to the right, so that data rotated 15 degrees to the left can be read when reading, and data rotated 10 degrees to the right can be written when writing.

Rotation control signals FDIR1 and FDIRQ are 1'''.

When it is "O", the address values Y7 to Y4 added to the frame memories M15 to MO are the inverted values of the address values YA7 to YA4, and the address values Y3 to YO are the inverted values of the address values YA7 to YA4, as shown in FIG. join. That is,
Y coordinate address values YA7 to YA4. Address values XA4 to XA4 of the X coordinate are both inverted and added to the frame memory.

At this time, "0" is added to the terminal S of the address decoder ADRR, and the address values YA3 to YAO are also added to the exclusive OR group E.
Since the data is inverted and added at ORG7, memory access is performed horizontally from the lower right end as shown in FIG. Decoder D
Since inverted data is added to RR, it is similarly shifted from the lower right end by the shift read for the horizontal row.

In other words, the basic images are read out in the reverse order. When read in reverse order from the bottom right corner, 16 words are read.
Since the bits are in the bit order in which the basic image was read, at this time, 1'' is added to the terminal E of the data swap circuit WSC2 to reverse the MSB and LSB of the bits. Since it is read out in units of 16 bits and the bit position is reversed from MSB (!: LSB), writing and reading are performed with the basic image rotated by 180° (clockwise rotation and left rotation are the same).

When the rotation control signals FDIR1 and FDIRQ are both 11'', frame memories M15 to M15 as shown in FIG.
Address values Y7 to Y4 added to MO are address value XA7
The inverted values of ~XA4, address values X3~xO, become address values YA7~YA4. Also, the exclusive disjunction group EOR
Since "1" is added to one input of G7, the address value Y
A3 to YAO are also inverted and the address decoder AD
It joins RR and decoder DRR. address decoder AD
Since "1" is also added to the terminal S of RR, different address values are added to the lower addresses Y3 to YO for each frame memory M15 to MO, as shown in FIG. 3(b). This access results in access to the memory for one column from the lower left end. At this time, this access is exactly the same as reading upward from the lower left end of the basic image. Further, the bit shift circuit BSC also changes the shift amount when sequentially reading out the inverted address values YA3 to YAO. At this time, "1" is added to the terminal of the data swap circuit WSCI, so the bit shift circuit BSC
The input/output (data) DB15 to DBO correspond to the input/output DD15 to DDO of the external device. As a result, reading and writing in the vertical direction is performed sequentially in units of 16 bits from the lower left end. That is, in other words, reading by rotating 270 degrees to the left and writing by rotating 90 degrees to the right are performed.

FIG. 9 is a display example of a rotated image obtained by reading or writing to a memory according to an embodiment of the present invention. For example, the seventh
As shown in the figure, rotation control signals FDIR1, FDIRQ
(a) 6m, @g+'', (bl"θ', "1
″, (C) @1″, ″0″, (d) “1”.

Write as 1″, rotation control signal FDIRI, FDIR
When both Qs are read as “0′”, the results in Figure 9 (
O", 90°, 180" shown in a) to (d),
270' image data rotated to the right can be obtained. A similar rotated image can be obtained by changing the rotation side faI signals FDIRI and FDIRQ not only during writing but also during reading. Note that when reading, 90% of the basic image is used, contrary to when writing.
Image data rotated to the left by 180°, 180°, and 270° are obtained. Also, the rotation control signal FDIR when adding the basic image
1, FDIRQ to 0”.

10'', the values of the rotation control signals FDIRI and FDfRO when the basic image is held in the mouth become the basic image storage position.This is the same in the embodiments of the present invention shown in FIGS. 2 and 5 described above. .

The memory arrangement of the present invention and the circuit that drives the memory have been described above using embodiments. However, the present invention is not limited to the memory arrangement shown in FIG. It is also possible to shift and arrange by odd number units, such as by shifting by , or to assign by other random number arrangement.

For example, if the data is divided into 16 bits in the vertical and horizontal directions, and the divided 16 x 16 beats/bit area is read in units of 16 bits in the vertical and horizontal directions, random numbers are used to ensure that there are no identical bits. Just place it. In this case, address decoder ADRR and decoder DRR must also be arranged in the same way to perform random number decoding.

In the embodiment of the present invention, the horizontal and vertical addresses are selected by the selector and added to the memory, but the invention is not limited to this.
For example, by adding a horizontal or vertical address to the address decoder and selecting and adding the address decoder value using the vertical/horizontal switching signal I (/V, it is possible to access the memory in the horizontal or vertical direction in the same way. becomes.

〔Effect of the invention〕

As described above, the present invention stores addresses in units of nxn dots! According to the present invention, a plurality of dots of i-image data are stored in a basic image by shifting the bits assigned to the frame memory by one dot corresponding to horizontal rows or vertical columns. For example, it is possible to obtain an image memory capable of storing and reading out a plurality of target dot data in the same way whether the memory is accessed from the horizontal direction or the memory from the vertical direction.

[Brief explanation of drawings]

FIG. 1 is a memory layout diagram of the present invention, FIG. 2 is a circuit configuration diagram of the first embodiment of the present invention, and FIG.
a) and (b) are address decoder input/output data diagrams, Figure 4 is a memory layout diagram during access, Figure 5 is a circuit configuration diagram of the second embodiment of the present invention, and Figure 6 is a read/write diagram. FIG. 7 is a circuit configuration diagram of the third embodiment of the present invention; FIG. 8 is a diagram showing the relationship between rotation control signals and address values; FIG. 9 (a) ) is image data without rotation, Figure 9 (b) is image data rotated 90 degrees to the right, Figure 9 fQ) is image data rotated 180 degrees right, and Figure 9 (d) is image data rotated 270 degrees right. Data FIG. 10 is a diagram illustrating the storage of data in a conventional memory. EORGI-EORG7...Exclusive OR group, SLI
~SL4...Selector, DRR...Decoder, BSC (BSGO-BSCI 5)...Bit shift circuit, ADRR...Address decoder, M15~MO...Frame memory, CHG...Image memory, INV...Inverter, WSC (WSCI, WSC2)...Data swap circuit. Patent applicant: Casio Computer Co., Ltd. Above: Casio Electronics Co., Ltd. Basic Image X
廂” vote (to X) Akira Honshu’s menu! Figure 1 Main stirrup H month's sZ Daiki Oj's mouth route Sai 41'J\1 Figure 5
Figure 8 of 7th dress, 4th shift, no rotation / IJb4 & reservation 90-
Rotation image image data (a)
(b) 11th step to the iao'b umbrella 27θ
Image data for the first time (c)
(d) Figure 9

Claims (1)

[Scope of Claims] 1) m memories each having an input/output terminal corresponding to one dot of n×n dot image data and storing at least (n×n)/m dots, and a row address. A memory drive circuit comprising first decoding means for decoding at least a portion of the column address and at least a portion of the column address in the vertical direction and adding the decoded data to the memory. 2) m memories having input/output terminals corresponding to data of one dot of n×n dots of image data and storing at least (n×n)/m dots and horizontal rows of dots of image data; first and second selection means that select at least part of the address and at least part of the column address in the vertical direction and add one of them to the m memories in common; and at least one of the row address or the column address. at least a portion of the row address or the column address, and decoding means for decoding at least a portion of at least one of the row address or the column address and separately adding the decoding means to the m memories. 3) The memory drive circuit according to claim 2, wherein the second selection means selects an address that is not selected by the first selection means. 4) The first selection means has a first inversion logic means to which an inversion control signal is applied, and the logic of the address selected by the inversion control signal is inverted and outputted. Memory drive circuit described in Section 1. 5) The memory drive circuit according to claim 2, wherein said decoding means has second inversion logic means to which an inversion control signal is applied.