JP3427586B2 - Data processing device and storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for reproducing processed original data by reproducing processed original data such as decompressing compressed image data to reproduce original image data. , A storage device suitable for use in such a data processing device.

[0002]

2. Description of the Related Art Conventionally, as this type of data processing device,
The image data of the pixel to be reproduced by learning the relationship between the image data of the pixel to be reproduced, which includes the image data of the pixel reproduced immediately before, and the image data of the pixel to be reproduced that has a fixed positional relationship with the pixel to be reproduced. It has been proposed to obtain data for decompression processing for analogizing the image data and reproduce the image data of the pixel to be reproduced by using the data for decompression processing to increase the reproduction speed. , The main part of the example is shown.

In FIG. 12, reference numeral 1 denotes a decompression processing circuit for decompressing compressed image data (monochrome data) to reproduce the original image data. The reproduced image data is transmitted to, for example, a printer. .

Reference numeral 2 is a table memory for storing decompression processing data used for decompression processing in the decompression processing circuit 1, and 3 is a memory for storing image data output from the decompression processing circuit 1.

Reference numeral 4 designates an address A7 ... from the image data of the reproduced pixel having a fixed positional relationship with the pixel to be reproduced.
A0 is generated, the table memory 2 is accessed, the decompression processing data is read from the table memory 2, the decompression processing data is transferred to the decompression processing circuit 1, and the decompression processing data is updated in the decompression processing circuit 1. If it is, the table memory access circuit writes the updated decompression processing data to the table memory 2.

13 to 17 are diagrams for explaining the operation of the data processing apparatus. FIG. 13 shows an original document which is being reproduced. In the original document 6, pixels are reproduced in line order. , The pixels on the left side are sequentially performed.

FIG. 14 is an enlarged plan view showing a part of the manuscript 6 shown in FIG. 13, where X _{n, k} , X _{n, k + 1} and X are shown.
_{n and k + 2} are the kth from the left of the nth line _{and k +} , respectively.
1st, k + 2nd pixel, X _{n + 1, k} , X _{n + 1, k + 1} , X
_{n + 1, k + 2} are the kth pixel, the k + 1th pixel, the k + 2nd pixel from the left of the n + 1th line, and _{Xn + 2, k} , X, respectively.
_{n + 2, k + 1} and X _{n + 2, k + 2} are the kth, k + 1th, and k + 2nd pixels from the left of the n + 2th line, respectively.

Since the pixels are reproduced in line order and from the pixel on the left side in the decompression processing circuit 1, when the pixel X _{n + 2, k + 2} is to be reproduced, the pixel is reproduced. X _{n, k} , X _{n, k + 1} , X _{n, k + 2} , X _{n + 1, k} , X _{n + 1, k + 1} , X
_{n + 1, k + 2} , X _{n + 2, k} and X _{n + 2, k + 1} have already been reproduced, and white or black has already been determined.

Therefore, in this case, the table memory
In the access circuit 4, as shown in FIG. 15, pixel X _n, the value of the image data of _k = A7, pixel X _{n, k + 1} image data value = A6, the pixel X _{n, k + 2} images Data value = A5,
Pixel X _{n + 1,} the value of _k image data = A4, the pixel X _{n + 1, k + 1} image data value = A3, the pixel X _{n + 1, k + 2} of the image data value = A2, the pixel When the value of the image data of X _{n + 2, k} = A1 and the value of the image data of pixel X _{n + 2, k + 1} = A0, the address A
7 to A0 are generated.

In this case, the pixels X _{n, k} , X of the nth line
The image data of _{n, k + 1} , X _{n, k + 2 and} the image data of the pixels X _{n + 1, k} , X _{n + 1, k + 1} , X _{n + 1, k + 2} of the _{n + 1-th line} are It is supplied from the memory 3 to the table memory access circuit 4,
The image data of the pixels X _{n + 2, k} and X _{n + 2, k + 1 on} the _{n +} 2th line is supplied from the decompression processing circuit 1 to the table memory access circuit 4.

FIG. 16 is a diagram for specifically explaining the operation of this data processing apparatus. In FIG. 16, "0" and "1" in the document 6 are image data, and "0" is. Pixels are white, "1" indicates that the pixel is black, and "x" indicates that the image data is undecided.

Here, in the document 6, k + on the (n + 2) th line
When the image data of the second pixel is reproduced,
According to the rule shown in FIG. 5, in the table memory access circuit 4, [00111101] is generated as the addresses A7 to A0 from the value of the image data of the pixels surrounded by the double line 7, the table memory 2 is accessed, and the address The decompression processing data DA designated by A7 to A0 = [00111101] is read.

This decompression processing data DA is transferred to the decompression processing circuit 1 via the table memory access circuit 4, and in the decompression processing circuit 1, k + 2 of the (n + 2) th line.
The image data of the th pixel is reproduced. In this example, n
The image data of the k + 2nd pixel of the + 2nd line is “0”
It is said that.

The image data of the (k + 2) th pixel on the (n + 2) th line is transferred to the printer and also stored in the memory 3
And to the table memory access circuit 4, and in the table memory access circuit 4, the address A7 to reproduce the k + 3th pixel of the (n + 2) th line.
A0 is generated.

In this case, according to the rule shown in FIG. 15, in the table memory access circuit 4, [01111110] is generated as the addresses A7 to A0 from the value of the image data of the pixels surrounded by the double line 8, and the table memory is accessed. 2 is accessed and addresses A7 to A0 =
Decompression data DB specified by [01111110]
Is read.

The decompression processing data DB is transferred to the decompression processing circuit 1 via the table memory access circuit 4, and in the decompression processing circuit 1, k + 3 on the (n + 2) th line.
The image data of the th pixel is reproduced.

FIG. 17 is a time chart showing the operating states of the table memory access circuit 4 and the decompression processing circuit 1 as binary waveforms. When the binary waveform is "H", it indicates that the operation is in progress. Is "L", it means that the device is not in operation.

[0018]

As described above, in this data processing device, the table memory access circuit 4 and the decompression processing circuit 1 wait for the end of the operation of the other party to start the operation, and then the operation and the pause. Since the data processing is performed by repeating the above, there is a problem that the decompression processing cannot be performed at high speed.

In view of the above point, the present invention is a data process for reproducing processed data such as decompressing compressed image data to reproduce the original image data, and reproducing the original data. An object of the present invention is to provide a data processing device capable of speeding up reproduction processing, and a storage device suitable for use in such a data processing device.

[0020]

A data processing apparatus of the present invention uses reproduction processing data selected based on reproduced data associated with reproduction target data, including data reproduced immediately before, A reproduction processing circuit that performs reproduction processing of the processed data and reproduces the original data, a reproduction processing data storage circuit that stores reproduction processing data, and a reproduction processing data storage circuit by accessing the reproduction processing data storage circuit. In a data processing device having an access circuit for reading data, the access circuit reproduces the data to be reproduced next to the data being reproduced as reproduction target data during reproduction of the data in the reproduction processing circuit. Multiple replay processes that may be used to replay the replay target data based on replayed data that is related to the replay target data and does not include the data in it When the data is read from the reproduction processing data storage circuit and held, and the data being reproduced in the reproduction processing circuit is reproduced, from among the plurality of reproduction processing data held, based on the reproduced data. The reproduction processing data used for the reproduction processing of the reproduction target data is selected, and the selected reproduction processing data is supplied to the decompression processing circuit.

In the data processing device of the present invention, the access circuit is
A plurality of reproduction processing data that may be used for the reproduction processing of the next reproduction target data is read from the reproduction processing data storage circuit and held, and when the data being reproduced is reproduced by the reproduction processing circuit, it is held. The reproduction processing data to be used for the reproduction processing of the next reproduction target data is selected from the plurality of reproduction processing data, and the selected reproduction processing data is supplied to the decompression processing circuit. Therefore, the access circuit and the reproduction processing circuit operate continuously without waiting for the end of the operation, that is, without stopping, until the reproduction of a series of image data is completed.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIGS.
An example of an embodiment of the present invention will be described by exemplifying a case where the present invention is applied to a data processing device used in a facsimile device.

FIG. 1 is a circuit diagram showing an essential part of an example of an embodiment of the present invention. In FIG. 1, 11 is a decompression processing circuit for decompressing compressed image data to reproduce the original image data. The reproduced image data is transmitted to, for example, a printer.

Further, 12 is a table memory for storing decompression processing data designated by addresses A7 to A0, which is used for decompression processing in the decompression processing circuit 11, and 13 is image data output from the decompression processing circuit 11. It is a memory for storing.

Further, numeral 14 generates addresses A7 to A1 from image data of reproduced pixels having a fixed positional relationship with the pixel to be reproduced in the expansion processing circuit 11, accesses the table memory 12, and expands from the table memory 12. When the decompression processing circuit 11 updates the decompression processing data while reading the processing data,
This is a table memory access circuit for writing the updated decompression processing data to the table memory 12.

FIG. 2 shows a memory map of the table memory 12. The table memory 12 has addresses A7 to A1 = [XXXXXXX] (X is "0").
Or a storage area designated by a value of "1") is set, and when the lowest address A0 is set to "0", that is, addresses A7 to A0 = [XXXXXXX
X0] for decompression processing and the lowest address A0 is “1”, that is, addresses A7 to A0
= Decompression processing data designated by [XXXXXXX1].

As a result, the table memory access circuit 14 outputs the addresses A7 to A1 as [XXXXXXX].
Is supplied to the table memory access circuit 14, the decompression processing data designated by the address [XXXXXXX0] and the decompression processing data designated by the address [XXXXXXX1] are used as the decompression processing data. Will be output at the same time.

For example, in FIG. 2, the table memory access circuit 14 sets addresses A7 to A1 as [0
[011110] is supplied, the decompression processing data [2B] specified by the address [00111100] and the address [001111] are used as the decompression processing data.
01] and the decompression processing data [8F] specified by [01] are simultaneously output to the table memory access circuit 14.

Here, the table memory 12 is constructed, for example, as shown in FIG. 3, and 16 in FIG.
Is a storage block string for storing the decompression processing data designated by the address [XXXXXXX0] when the lowest address A0 is set to "0", and 17 is for the decompression processing designated by the address [00000000]. A storage block for storing data, 18 is an address [00000
010] is a storage block for storing the decompression processing data, and 19 is a storage block for storing the decompression processing data specified by the address [11111110].

Further, 20 is the lowest address A0 is "1".
In other words, that is, a storage block string that stores the decompression processing data specified by the address [XXXXXXX1], 21 is a storage block that stores the decompression processing data specified by the address [00000001], and 22
Is a storage block for storing decompression processing data specified by the address [00000011], and 23 is a storage block for storing decompression processing data specified by the address [11111111].

Further, 24 is a decoder which decodes the addresses A7 to A1 and outputs a selection signal for selecting a storage block designated by the addresses A7 to A1, and 25 is a storage block 17 to 19, 21 to 23. In the memory block, a read control signal input terminal to which a read control signal RD for performing read control is input, and a write control signal input terminal 26 to which a write control signal WR for write control is input.

Further, FIG. 4 and FIG.
FIG. 4 is a diagram for explaining an operation of an address generation unit included in the access circuit 14, and FIG. 4 is an enlarged plan view showing a part of a document which is being reproduced.

Note that X _{n, k} , X _{n, k + 1} , and X _{n, k + 2} are kth, k + 1th, and k + 2 from the left of the nth line, respectively.
The _n- th pixel, X _{n + 1, k} , X _{n + 1, k + 1} , and X _{n + 1, k + 2} are k-th, k + 1-th, and k-th from the left on the n + 1-th line, respectively.
The + 2nd pixel, X _{n + 2, k} , X _{n + 2, k + 1} , X _{n + 2, k + 2} ,
These are the kth pixel, the k + 1th pixel, and the k + 2nd pixel from the left of the n + 2th line, respectively, and in the document 27, the reproduction of the pixels is performed in the line order and from the left side pixel in order.

As described above, since the reproduction of the pixels is performed in the line order and in order from the pixel on the left side, the expansion processing circuit 1
1, when the image data of the pixel X _{n + 2, k + 1} is being reproduced, the pixels X _{n, k} , X _{n, k + 1} , X _{n, k + 2} , X _{n + 1, k} , X
_{n + 1, k + 1} , X _{n + 1, k + 2} , and X _{n + 2, k} have already been reproduced, and white or black has already been determined.

Therefore, the table memory access circuit 1
In the expansion processing circuit 11, the address generation unit 4 of FIG. 4 uses the pixel X _{n + 2, k + 2} as the next reproduction target pixel while reproducing the image data of the pixel X _{n + 2, k + 1} as shown in FIG. As shown, pixel X
Image data value of _{n, k} = A7, image data value of pixel _{Xn, k + 1} = A6, image data value of pixel _{Xn, k + 2} = A5, image of pixel _{Xn + 1, k} Data value = A4, image data value of pixel X _{n + 1, k + 1} = A3, image data value of pixel X _{n + 1, k + 2} = A2, image data of pixel X _{n + 2, k} Value of = A1,
It is configured to generate addresses A7-A1.

The image data of the pixel X _{n + 2, k + 1 being} reproduced in the decompression processing circuit 11 is transferred to the printer at the same time as the reproduction is completed, and the table memory access circuit 14 sets it as the address A0. The data is transferred to the expansion processing data transfer unit described later.

FIG. 6 is a circuit diagram showing a configuration example of the address generation unit of the table memory access circuit 14, and 29 to 37 in FIG. 6 are registers for storing image data, respectively. In the figure, registers 29 to 3
The position 7 corresponds to the positions of the pixels X _{n, k to} X _{n + 2, k + 2} shown in FIG.

38 is an address output port,
Reference numerals 39 to 45 are address output terminals to which the addresses A7 to A1 are output, respectively.

In this example, the image data of the nth line is supplied from the memory 13 to the register 31 for each pixel every time one pixel is processed, and the register 34 is supplied to the register 34.
Each time one pixel is processed, n + 1 from the memory 13
The image data of the line is supplied for each pixel, and the image data of the (n + 2) th line is supplied to the register 37 for each pixel from the decompression processing circuit 11 every time the processing of one pixel is performed. Has been done.

The image data of the n-th line supplied from the memory 13 is processed every time one pixel is processed.
Register 31 → register 30 → register 29 are transferred in this order, the contents of register 29 are output as address A7 to address output terminal 39, the contents of register 30 are output as address A6 to address output terminal 40, and register 3
The content of 1 is controlled to be output to the address output terminal 41 as A5.

The image data of the (n + 1) th line supplied from the memory 13 is transferred in the order of register 34 → register 33 → register 32 every time one pixel is processed, and the content of the register 32 becomes the address A4. The contents are controlled to be outputted to the address output terminal 42, the contents of the register 33 as the address A3 to the address output terminal 43, and the contents of the register 34 to the address output terminal 44 as A2.

Further, n supplied from the expansion processing circuit 11
The image data of the + 2nd line is transferred in the order of register 37 → register 36 → register 35 every time one pixel is processed, and the content of the register 35 is controlled to be output to the address output terminal 45 as the address A1. It

FIG. 7 is a circuit diagram showing a configuration example of the decompression processing data transfer unit of the table memory access generation circuit 14 together with the decompression processing circuit 11. In FIG. 7, 47 is a decompression processing data transfer unit. is there.

In the decompression processing data transfer section 47, the reference numeral 48 designates the lowest address A0 of the decompression processing data output from the table memory 12 as "0", that is,
This is a register that stores decompression processing data specified by the address [XXXXXXX0].

Reference numeral 49 is a register for storing the decompression processing data designated by the lowest address A0 of the decompression processing data output from the table memory 12 by "1", that is, the address [XXXXXXX1]. .

Reference numerals 50 and 51 denote selectors for selecting the outputs of the registers 48 and 49.
Image data of a pixel which is being reproduced in the expansion processing circuit 11 while the addresses A7 to A1 are being generated in the table memory access circuit 14 is supplied to 51 as an address A0.

These selectors 50 and 51 have the address A
When 0 = “0”, the output of the register 48 is selected, and when the address A0 = “1”, the output of the register 49 is selected, and the output of the register selected by the selector 50 is , To the expansion processing circuit 11.

Further, 52 is a register for storing the output of the selector 51, 53 is a register for storing the address A0,
An inversion circuit 54 inverts the address A0 output from the register 53.

Further, 55 and 56 are selectors used when the expansion processing data is updated in the expansion processing circuit 11, and the selector 55 has the address A0 = "0".
In this case, the updated decompression processing data output from the decompression processing circuit 11 is selected, and when the address A0 = "1", the output of the register 52 is selected.

Further, the selector 56 has the address A0 =
In the case of "0", the output of the register 52 is selected, and in the case of the address A0 = "1", the updated decompression processing data output from the decompression processing circuit 11 is selected.

Reference numeral 57 is a register for storing the output of the selector 55 and transferring it to the table memory 12, and 58 is a register for storing the output of the selector 56 and transferring it to the table memory 12.

That is, in this example, the expansion processing circuit 1
When the decompression processing data is updated in 1, the updated decompression processing data and the unused decompression processing data are rewritten to the read addresses of the table memory 12.

FIG. 8 is a diagram for specifically explaining the operation of the example of the embodiment of the present invention. In the original 27, “0” and “1” are image data and “0”. "," Indicates that the pixel is white, "1" indicates that the pixel is black, and "x" indicates that the image data is undecided.

Here, in the example of the embodiment of the present invention, the table memory access circuit 14 is operated while the decompression processing circuit 11 is reproducing the (k + 1) th pixel of the (n + 2) th line.
5, the k + 2th pixel on the n + 2th line is targeted for reproduction, and the decompression processing data that may be used for reproducing the k + 2nd pixel on the n + 2th line is read from the table memory 12 as shown in FIG. According to the rule shown, the address [0011110] is generated from the value of the image data of the pixel surrounded by the double line 60, and the table memory 12 is accessed.

As a result, in the table memory 12, from the storage area specified by the addresses A7 to A1 = [0011110], for example, [2B], as decompression processing data with the lowest address A0 set to "0", As the decompression processing data in which the lowest address A0 is "1",
For example, [8F] is output at the same time.

The decompression processing data [2B] is stored in the register 48 of the table memory access circuit 14, and the decompression processing data [8F] is stored in the table memory.
It is stored in the register 49 of the access circuit 14.

After that, when the reproduction of the image data of the (k + 1) th pixel on the (n + 2) th line is completed and, for example, the image data of this pixel is determined to be "1", this image data "1" is output to the printer. Address A as supplied
0 is supplied to the selector 50 of the table memory access circuit 14.

As a result, in the selector 50, the output of the register 49 is selected and the address [0011110] is selected.
The decompression processing data [8F] specified in 1] is supplied to the decompression processing circuit 11.

As a result, in the expansion processing circuit 11,
This decompression processing data [8F] is used to reproduce the k + 2 pixel on the n + 2 line, and during this reproduction, the table memory access circuit 14
To read the decompression processing data that may be used for the reproduction of the k + 3th pixel of the n + 3th line as the next reproduction target from the k + 3th pixel of the n + 2th line, FIG. Following the rules shown
[0111111] is generated as the addresses A7 to A1 from the value of the image data of the pixels surrounded by the double line 61, and the table memory 12 is accessed.

As a result, in the table memory 12, from the storage area specified by the addresses A7 to A1 = [0111111], for example, [3C] as decompression processing data for setting the lowest address A0 to "0", As the decompression processing data in which the lowest address A0 is "1",
For example, [6A] is output at the same time.

The decompression processing data [3C] is stored in the register 48 of the table memory access circuit 14, and the decompression processing data [6A] is stored in the table memory.
It is stored in the register 49 of the access circuit 14.

After that, when the reproduction of the image data of the (k + 1) th pixel on the (n + 2) th line is completed and, for example, the image data of this pixel is determined to be "0", this image data "0" is output to the printer. Address A as supplied
0 is supplied to the selector 50 of the table memory access circuit 14.

As a result, in the selector 50, the output of the register 48 is selected and the address [0111111] is selected.
The data [3C] for decompression processing specified by [0] is supplied to the decompression processing circuit 11.

Therefore, the decompression processing circuit 11 uses this decompression processing data [3C] to obtain n + 2.
While the image data of the k + 3th pixel on the line is reproduced, the table memory access circuit 14 selects the k + 4th pixel on the n + 2th line as the next reproduction target during the reproduction. K + 4
Addresses A7 to A1 for reading out the decompression processing data that may be used for reproducing the th pixel from the table memory 12 are generated, and the table memory 12 is accessed. Hereinafter, the same operation is repeated.

FIG. 9 shows the table memory access circuit 14
2 is a time chart showing the operation status of the decompression processing circuit 11 as a binary waveform. When the binary waveform is “H”, it is in operation, and when the binary waveform is “L”, it is in pause. .

As described above, in the example of the embodiment of the present invention, the decompression processing data is specified by the addresses A7 to A0, and is stored in the storage area specified by the addresses A7 to A1 of the table memory 12. Stores the decompression processing data having the lowest address A0 as "0" and the decompression processing data having the lowest address A0 as "1". When the addresses A7 to A1 are supplied, The decompression processing data having the lower address A0 of "0" and the decompression processing data having the lowest address A0 of "1" are simultaneously output.

Correspondingly, during the reproduction of the image data of a certain pixel in the expansion processing circuit 11, the table memory access circuit 14 sets the pixel to be reproduced next to the pixel being reproduced as the reproduction target pixel. , The addresses A7 to A1 are generated from the image data of the reproduced pixels which do not include the image data of the pixel being reproduced and have a fixed positional relationship with the pixel to be reproduced, and the table memory 12 is accessed to Two pieces of decompression processing data that may be used for reproducing the image data are read from the table memory 12 and held.

Then, when the image data of the pixel being reproduced is reproduced in the expansion processing circuit 11, the table memory access circuit 14 uses the image data as the address A0 and expands the two stored expansions. From the processing data, the expansion processing data to be used for reproducing the image data of the next reproduction target pixel is selected, and the selected expansion processing data is supplied to the expansion processing circuit 11.

Therefore, according to the example of the embodiment of the present invention, the table memory access circuit 14 and the decompression processing circuit 11 wait for the end of the operation to start the operation, and repeat the operation and the pause. , The data is not processed, but the operations are continuously performed without waiting for the end of the operations, that is, without stopping until the reproduction of the series of image data is completed.
The decompression process can be performed at twice the speed of the conventional data processing device shown in FIG.

The table memory 12 is, for example,
It can also be configured as shown in FIG. Here 6
3 is a storage block sequence 1 such as storage blocks 17 to 19
6, a write control signal input terminal to which a write control signal WR0 for performing write control of the storage block 6 is input, and 64 is write control for performing write control of the storage blocks of the storage block column 20 such as the storage blocks 21 to 23. Signal WR1
Is a write control signal input terminal to which is input.

That is, this table memory is composed of storage blocks 17 to 19, 21 to 23, etc.
The read control of the storage blocks 6 and 20 is performed by the read control signal RD, and the write control of the storage blocks of the storage block row 16 such as the storage blocks 17 to 19 is performed.
The storage block 21 is performed by the write control signal WR0.
The write control of the storage blocks of the storage block column 20, such as 23 to 23, is performed by the write control signal WR1.

In this case, when the updated decompression processing data is written, only the updated decompression processing data can be written, and the unused decompression processing data can be written as follows. Rewriting can be prevented, and as a result, the decompression processing data transfer unit of the table memory access circuit 14 is denoted by reference numeral 6 in FIG.
It can be simplified as shown at 6.

[0073]

As described above, according to the data processing apparatus of the present invention, the access circuit and the reproduction processing circuit do not wait for the end of their operations until the reproduction of a series of image data is completed, that is, Since the operation is continuously performed without pausing, the speed of the data reproducing process can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an example of an embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of a table memory included in an example of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a table memory included in an example of an embodiment of the present invention.

FIG. 4 is an enlarged plan view showing a part of a document which is being reproduced.

FIG. 5 is a diagram for explaining a relationship between an address generated in an address generation unit of a table memory access circuit and a reproduced pixel included in an example of an embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of an address generation unit of a table memory access circuit included in an example of an embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a decompression processing data transfer unit of a table memory access circuit included in an example of an embodiment of the present invention, together with a decompression processing circuit.

FIG. 8 is a diagram for specifically explaining the operation of the example of the embodiment of the present invention.

FIG. 9 is a time chart showing binary waveforms of operation states of the table memory access circuit and the expansion processing circuit included in the example of the embodiment of the present invention.

FIG. 10 is a circuit diagram showing another configuration example of the table memory included in the example of the embodiment of the present invention.

FIG. 11 is a circuit diagram showing another configuration example of the decompression processing data transfer unit of the table memory access circuit included in the example of the embodiment of the present invention.

FIG. 12 is a circuit diagram showing a main part of an example of a conventional data processing device.

FIG. 13 is a plan view showing a document which is being reproduced.

FIG. 14 is an enlarged plan view showing a part of the document shown in FIG.

15 is a diagram for explaining a relationship between an address generated in a table memory access circuit included in the conventional data processing device shown in FIG. 12 and a reproduced pixel.

16 is a diagram for specifically explaining the operation of the conventional data processing device shown in FIG.

FIG. 17 is a time chart showing binary waveforms of operating states of the table memory access circuit and the expansion processing circuit included in the conventional data processing apparatus shown in FIG.

[Explanation of symbols]

11 Decompression processing circuit 12 table memory 13 memory 14 Table memory access circuit A7-A0 Address that specifies decompression data

Claims (7)

(57) [Claims] 1. Reproduction processing of processed data is performed by using reproduction processing data selected based on reproduced data related to reproduction target data, including data reproduced immediately before, and reproducing original data. A reproduction processing circuit for reproducing data, a reproduction processing data storage circuit for storing the reproduction processing data, and an access circuit for accessing the reproduction processing data storage circuit and reading the reproduction processing data. In the data processing device, the access circuit, while reproducing the data in the reproduction processing circuit, sets the data to be reproduced next to the data being reproduced as the reproduction target data and does not include the data being reproduced. Based on the reproduced data related to the reproduction target data, the plurality of reproduction processing data that may be used for the reproduction processing of the reproduction target data are reproduced. When the data being reproduced is reproduced in the reproduction processing circuit by reading out and holding it from the logical data storage circuit, the reproduction target is selected from the plurality of reproduction processing data based on the reproduced data. A data processing device configured to select reproduction processing data to be used for data reproduction processing and to supply the selected reproduction processing data to the decompression processing circuit. 2. The image data of a pixel reproduced immediately before is included.
A decompression processing circuit for decompressing the compressed image data using the decompression processing data selected based on the image data of the replayed pixel related to the replay target pixel and replaying the original image data. A data processing device having a decompression processing data storage circuit for storing the decompression processing data and an access circuit for accessing the decompression processing data storage circuit and reading the decompression processing data. During reproduction of the image data in the decompression processing circuit, the circuit sets a pixel to be reproduced next to the pixel being reproduced as a reproduction target pixel, and does not include image data of the pixel being reproduced, Based on the image data of the related reproduced pixels, a plurality of decompression processing data that may be used for reproducing the image data of the reproduction target pixel are decompressed. When the image data of the pixel being reproduced is reproduced by the expansion processing circuit by reading and holding the read data from the data storage circuit, based on the reproduced image data, among the plurality of expansion processing data, A data processing device configured to select decompression processing data to be used for reproducing the image data of the reproduction target pixel and to supply the selected decompression processing data to the decompression processing circuit. 3. The data processing apparatus according to claim 2, wherein the decompression processing data storage circuit stores decompression processing data in an updatable manner. 4. The decompression processing data includes addresses A _m and A _m-1.
... A ₀ (where m is an integer of 2 or more), and the decompression processing data storage circuit has an address _Am ,
A _m-1 has a storage area specified by A ₁ , and in this storage area, decompression processing data whose lowest address A ₀ is “0” and lowest address A ₀ is “1”. Decompression processing data is stored, and the access circuit extracts addresses A _m , A _m-1 from the image data of the reproduced pixel associated with the pixel to be reproduced, which does not include the image data of the pixel being reproduced. The data processing apparatus according to claim 3, wherein A ₁ is generated and the decompression processing data storage circuit is accessed. 5. A storage area for storing decompression processing data in which the lowest address A ₀ is "0", and a storage area for storing decompression processing data in which the lowest address A ₀ is "1". 5. The data processing device according to claim 4, wherein the write control is performed by a separate write control signal. 6. Addresses A _m , A _m-1 ... A ₁ (where m
Has a storage area specified by an integer of 2 or more), this storage area, among the data designated by the address _{A m, A m-1 ···} A 1, A 0, the least significant address A A storage device which stores decompression processing data having ₀ as “0” and data having the lowest address A ₀ as “1”. 7. A write control is separately provided for a storage area for storing data having the lowest address A ₀ as “0” and a storage area for storing data having the lowest address A ₀ as “1”. 7. The storage device according to claim 6, wherein write control is performed by a signal.