JPS6037930B2 - information storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information storage device that stores a huge amount of information such as image information.

An image processing device using an electronic computer requires a large capacity image memory.

However, in recent years, with the development of IC memories, it has become possible to provide large-capacity, high-speed access memories that can store an entire image or several images. However, this type of memory is very expensive and requires efficient use. Therefore, in an image processing device, the image memory is arranged at the same level as the main memory, and the DMA (Direct
ctMemoryAccess) method, and by using one memory for multiple purposes, such as refreshing a display, input/output buffer, and working memory for calculations, it is possible to improve the usage efficiency.
If image memory is divided and used in this way, allowing one part to be used as a working area for calculations and another part as refresh memory, then several processes of image processing can be performed in an overlapping manner. , a reduction in processing time is expected. When dividing this memory, for example, in the case of image memory, a variety of data is handled, from multi-tone color images to monochrome single-value figures, and the number of pixels also varies, so it is not only necessary to divide it in the word direction. , space efficiency can be improved by making division easier in the beat direction. The present invention has been made in view of the above points, and an object of the present invention is to provide an information storage device with high usage efficiency.
- An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the overall schematic configuration of the present invention. 1st
In the figure, 1 is a memory bank, which is composed of a plurality of memory boards 1 to ln. Each of the above memory boards 1, ~
For example, ln is 256 pieces x 25 needles (pixels) x 1
It has a storage capacity of (bits), and is given a common X and Y address. By specifying this address, bit information at the same address can be read or written to each memory board. It is now possible to The above-mentioned memory bank is capable of inputting and writing single word and multi-word information, and the single word information read from memory bank 1 is held in a latch circuit, that is, a data register 2, and then transferred to a shift circuit 3 on one side, for example, in the lower order. It is shifted bitwise and sent via a single word channel 4 to an input/output device (not shown).
Also, single word information sent from the input/output device via the single word channel 4 is sent to the data register 5.
is set for one day, and after a predetermined bit shift in the upper bit direction by the shift circuit 6, it is written into the memory bank. In this case, in the shift circuits 3 and 6, the shift amount is designated by a signal from the bit position designation circuit 7, and the bit length of the output information is designated by a signal from the bit length designation circuit 8. Further, the outputs of the bit position designating circuit 7 and the bit length designating circuit 8 are sent to a board enable circuit 9, and the board enable circuit 9 selects the memory boards 1.about.ln. Information is written or output only to the memory board selected and designated by the board enable circuit 9. Information given to the bit position designation circuit 7 and bit length designation circuit 8 is performed by address designation of the computer in response to a request from an external device such as an input/output device.
For example, if the screen size of the image input/output device is 25 pixels vertically and 25 pixels horizontally, a total of 6553 pixels, and the gray level is 4 bits, the memory board 1, to l
Four boards to be connected (hereinafter, the first board is included) are selected based on an arbitrary board of n, and the discussion or writing is performed.

In this case, X, Y of the memory boards 11 to ln
All addresses shall be fixedly specified. In addition, if the size of one screen of the image input/output device is 512 pixels vertically and 512 pixels horizontally, for a total of 262,144 pixels, and the gray level is 4 bits, one screen is divided into four, and the divided screen is Four memory boards are assigned to each unit, and the divided memory boards are selected by the bit position designation circuit 7 and the bit length designation circuit 8, and as described above, the four boards are assigned. Alternatively, writing is performed.

Further, multi-word, for example, 16-word information read from the memory bank 1 is input to the read data register 2 via the bidirectional multi-word data bus 11.

The data temporarily stored in the data register 2 is shifted by a bidirectional shift circuit 13, for example, in the lower bit direction, and then transferred to a multi-word port 14.
From this multi-word boat 14, the data is further transferred to an input/output device via a multi-word channel 15. Further, multiword write data sequentially sent from the input/output device via the multiword channel 15 at each predetermined transfer position is first input to the multiword port 14, and from this multiword port 14, the above-mentioned bidirectional After being shifted to a predetermined bit position via the digital shift circuit 13, the data is sequentially sent to the first write data register 16.
The data temporarily stored in the first write data register 6 is then collectively stored in the second write data register 17.
The data is further sent to memory bank 1 via data line 11 and written to a predetermined memory board 1.about.ln. FIG. 2 shows an address designation circuit that designates the X and Y addresses of the memory boards 11 to ln, including an X address register 21, a Y address register 22, and a It is composed of an address register 23 which receives the outputs of both as input and specifies the addresses of the memory boards 1 to ln.

Note that the address information input to the x address register 21 and the Y address register 22 is provided from an input/output device, such as an image input/output device. Next, details of each of the above parts will be explained.

First, a case in which single word image information is written to memory bank 1 will be described. It is assumed that the memory bank 1 is made up of memory boards 11 to 1 and 6. FIG. 3 shows an address format for writing image information. This address format is given to each pixel of image information.
U information to specify bit length, Z information to specify bit position, X to specify memory address
, Y address information. The U information is multi-bit information for setting the number of memory boards 1, . It has bit information that can be specified at once, and in this embodiment, the maximum i
Five bits are required to specify a written statement. Further, the Z information is 4-bit information for specifying the first board of the memory boards, and is used to divide the memory bank 1 into blocks depending on the screen size and level. That is, if the number of pixels of the image information and the number of words of the memory board are different and cannot be matched, the image information is divided into blocks of a predetermined size and specified by the U information and the Z information.

Finally, the ×, Y address information is 8-bit information (256 x 25 pixels) that specifies the address on the memory board, and this ×, Y address information is led to the addressing circuit shown in Figure 2. I'm scared. Next, image information A, B
To describe the specific writing operation of the image processing storage device, let us first assume that the image information A has a screen size of 25 stitches vertically, 25 stitches horizontally, and a level of 4 bits. , further convert the image information into a(i,i)(i=0~
255 j = 0 to 255). In addition, image information B has a screen size of 512 pieces vertically and 5 pieces horizontally.
The pixel information is b(i,j) (i=0~511, i=0~5).
11). First, pixel information a (
Regarding the writing of i, i), it is assumed that 4-bit information {1110} is written at the address position of i=x, 1=y. This image information {1110} is input to the data register 5 from the image input/output device as shown in FIG. 4, and is transferred to the shift circuit 6 after being temporarily stored.

Here, board selection and address selection operations of the memory board are performed according to the address format shown in FIG. That is, the U information is 00100 and the Z information is 01.
00, these pieces of information are supplied to the bit length designation circuit 8 and bit position designation circuit 7 in FIG. 4, and address information x and y are supplied to the address register 23. As a result, the shift circuit 6 shifts the pixel information by 4 bits, that is, to the bit position specified by the Z information, and waits. Meanwhile, the board enable circuit 9 shifts the pixel information to the bit position specified by the Z information, that is, by 4 bits, and waits. By selecting memory board 15 using Z information and specifying the following four boards using U information,
16, 17, and 18, and writes the waiting pixel information to the x and y addresses specified in the address register 23. Next, pixel information b(x', y')
Regarding the writing of , it is assumed that 4-bit information {0001} is written at the address position of i=x, 1=y'.

First, the number of pixels of image information B is determined by the number of pixels of the image information B.・・・
- Since the numbers of words 1 and 6 are not the same, it is necessary to divide the memory board into blocks.

That is, image information A and B are each twice as large in length and width as the size of one screen, and therefore, in order to obtain image information B, a memory board that is four times as large is required. Therefore, 4 memory boards from the first memory board are 1/4 of one screen.
pixel information can only be stored. Next, image information {0001} is inputted from the image input/output device to the data register 5 and transferred to the shift circuit 6, as shown in FIG.

Hereinafter, if pixel information {0001} is information on an image belonging to the second block of a memory board divided into four, U information, Z information, and x', y' are given according to the address format shown in FIG. Thereafter, the pixel information a(i,j) is written by the same operation as that for writing.

Therefore, the memory boards 1, 12, . . . 1, 6
For the image information a(i,i), the image for 4 screens is also
One screen worth of images can be stored for each b(i,i).

In addition, please refer to Part 3 for details on the image information of the storage device.
By specifying the address as shown in the figure, image information is output to the data register 2 through the output circuit shown in Figure 1, and the basic structure is the same as the write operation described above, except for the direction of the information. I will omit the explanation of the problem of disclosing the image information.

Further, it is needless to say that the boards following the memory board do not need to be selected in a continuous manner, and may be arbitrarily designated as long as the total number of boards match. Next, the details of the multi-word data processing circuit system will be explained in Part 6.
This will be explained with reference to the figures.

A bus drive circuit 31 is provided between the multi-word data register 12 and the shift circuit 13 in FIG. This bus drive circuit 31 operates according to a signal from a gate signal generation circuit 32, and divides the multi-word data stored in the data register 12 into several transfers per predetermined transfer unit and sends them to the shift circuit 13 via a data bus 33. do. This shift circuit 13 also includes a multi-word board 1.
4 is inputted via the buzz drive circuit 34. The data other than the data output from the shift circuit 13 is input to the multi-word port 14 or the first write data register 6 via the data bus 35. In this case, data is input to the data register 6 in predetermined transfer units, and is sequentially latched. Then, by latching several times, all the data in the write unit of memory bank 1 is prepared, and then transferred to the second write data register 17. The data transferred to the data register 7 is written into the memory bank 1. FIG. 7 shows a part of the configuration of the shift circuit 13 mentioned above.

Input terminals 41, -414 are supplied with data from the data bus 33, and these input terminals 41, -414 are connected in parallel to the input terminals of each data selector 421-424.

Further, a bit position designation signal is inputted to the data selectors 42 to 424 from the bit position designation circuit 7 via input terminals 41a and 41b. Data selector 42・
.about.424 selects input data according to the command from the bit position specifying circuit 7, and outputs it to output terminals 43 and .about.434. That is, data selectors 42-424
operates to shift the input data to the least significant bit in response to a command from the bit position designation circuit 7 when inputting data, and to shift the specified bit in the direction of the upper bits when writing. . In the above configuration, for example, 16 words of multi-word data are output from the memory bank 1 to the data bus 11 in FIG. 1, and this multi-word data is set in the data register 12 at a time.

Note that address designation to the memory bank and the like are performed in the same manner as in the case of single word access, so a description thereof will be omitted. The multi-word data set in the data register 2 is divided into several times, for example, four times, by the bus drive circuit 31 and output to the data bus 33 in four-word increments. In this case, the bus drive circuit 31 operates according to the gate signal given from the gate signal generation circuit 32, and sequentially divides the data held in the data register 12 into predetermined transfer units and outputs the divided data. In this case, the bus drive circuit 34 on the data write side is disabled and its output terminal is in an open state, that is, a high impedance state, cutting off the relationship with the data bus 33. Then, the data outputted from the bus drive circuit 31 to the data bus 33 is shifted to the least significant bit position by the shift circuit 13 and sent to the multiword port 14, and is further transferred from the multiword port 14 to the multiword channel 15. is sent to the input/output device via the Also, data sent from the input/output device to the multiword port 14 via the multiword channel 15 is transferred to the memory bank 1.
When writing to the bus drive circuit 3 on the data output side.
1 is disabled and its output terminal is open,
In other words, it enters a high impedance state and disconnects from the data bus 33.

In this state, the data from the input/output device that is output via the multi-word port 14 is sent from the bus drive circuit 34 to the shift circuit 13 in predetermined transfer units, and is shifted to a predetermined bit position to become the first write data. register 1
6 in sequence. Then, by latching several times, all the data in units of writing to the memory bank are prepared in the data register 16. And this data register 1
When data is prepared in the write data register 6, the contents of the first write data register 16 are transferred to the second write data register 7 if the second write data register 7 is in a ready state. As a result, the first write data register 16 becomes ready, and the next write data can be transferred. Furthermore, the data transferred to the second write data register 17 is written to the memory bank 1. In this way, a proposal or write is made to the memory bank, but
It is also possible to read and write at the same time.

That is, at the time of issue, it takes time from the start of access until the issue data is prepared on the data register 12, which is the so-called access time. If write data is generated from the same input/output device or another input/output device from the start of this access until the delivery data can be transferred, the data transferred to the write data registers 16 and 17 is transferred to the read data register 12. This is done in parallel with the data submission. In this way, the first and second write data registers 16 and 17 are provided, and the memory bank 1
By effectively utilizing the access time, continuous discussion, continuous writing, discussion after writing, and writing after submission can be efficiently carried out in approximately the same cycle time.

Furthermore, since the data buses 11, 33, and 35 are shared for the transfer of read data and write data, the number of data lines required for the buses is halved. Furthermore, since the input data and write data are transferred in multiple batches, the capacity of the data bus can be reduced in accordance with the predetermined unit of data transfer, and the number of bits constituting the shift circuit 13 can be reduced. can. Furthermore, since this shift circuit 13 is shared for both the output data and the write data, it can achieve its purpose with half the circuit configuration compared to the case where it is provided for both the output data and the write data. can be achieved. In the present invention, since a memory bank of M bits per word is configured with M memory planes of 1 bit x N words, and a selection circuit is provided for selecting a specific memory plane when accessing the memory bank, (a) binary The memory bank can be divided and used not only in the word direction but also in the bit direction, depending on the size of the image, from graphics to multi-gradation images, or depending on the number of pixels, allowing for delicate area utilization. 'b - Each plane can be accessed individually or multiple planes can be accessed simultaneously, allowing bit-oriented access. effect can be obtained.

Furthermore, since a shift circuit is provided for sending data from a memory bank or writing data to a memory bank according to the area division in the bit direction, it is possible to appropriately handle data exchange with input/output devices, for example. can.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; Fig. 1 is a block diagram showing the overall circuit configuration, Fig. 2 is a block diagram showing the addressing circuit of the memory board, and Fig. 3 shows the address format. 4 is a block diagram showing the write operation, FIG. 5 is a diagram showing the address format, FIG. 6 is a block diagram showing details of the multi-word circuit system, and FIG. 7 is a block diagram showing details of the shift circuit. It is a block diagram. 1...Memory bank, 1,~1n..."Memory board,
2, 5...Data register, 3,6...Shift circuit, 4
・・・・・・Single word channel, 7・・・・・・
Bit position designation circuit, 8...Bit length designation circuit, 9
...Board enable circuit, 11, 33, 35...Data bus, 12...Read data register, T3...
...Shift circuit, 14...Multi-word boat, 15...Multi-word channel, 16, 17...1st
, second write data register, 21...X address register, 22...Y address register, 23...address register, 31, 34...bus drive circuit,
32...Gate signal generation circuit, 42, to 424
...Data selector. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 Figure 6 Figure 7

Claims (1)

[Claims] 1. A memory bank consisting of a plurality of memory boards and capable of read/write access in single word and multi-word, an address register for specifying the address of the memory bank, and a memory bank specified by the address register. bit position specifying means for specifying the data bit position of the specified address; bit length specifying means for specifying the bit length from the bit position specified by the bit position specifying means; A first register for latching, a second register for latching single data read from the memory bank, and at least one shift circuit for shifting the contents of the two registers based on a value given from the bit position specifying means. a first interface, a third register that latches write multi-data to the memory bank, and a fourth register that latches read multi-data from the memory bank.
a second interface comprising a register and at least one shift circuit for shifting the contents of the two registers based on a value provided by the bit position specifying means;
An information storage device comprising: 2 A P-bit internal bus that connects the memory bank and each of the registers of the second interface, and a P/bit bus that connects the second interface and the external output device.
The read multi-data output from the external bus of Q bits and the internal bus from the memory bank is latched in a register, divided into Q times, and output to the input/output device via the shift circuit and external bus. and means for transferring write multi-data input from the input/output device via the external bus and shift circuit to the write latch register Q times, converting it into P bits, and inputting it to the memory bank. An information storage device according to claim 1, characterized in that: 3. The information storage device according to claim 2, wherein the internal bus and the external bus are bidirectional buses, which are shared for read data and write data. 4 A multi-word port is provided between the second interface and the input/output device, and a plurality of input/output devices connected to the plurality of external buses and the second
3. The information storage device according to claim 2, wherein the information storage device performs interface data transfer.