JPS62179128A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62179128A JPS62179128A JP61020454A JP2045486A JPS62179128A JP S62179128 A JPS62179128 A JP S62179128A JP 61020454 A JP61020454 A JP 61020454A JP 2045486 A JP2045486 A JP 2045486A JP S62179128 A JPS62179128 A JP S62179128A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- semiconductor wafer
- surface side
- semiconductor
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005520 cutting process Methods 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 241000252203 Clupea harengus Species 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 235000019514 herring Nutrition 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Dicing (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to a method for manufacturing a semiconductor device.
特に、メサ形構造を有する半導体装置の製造方法の改良
に関する。In particular, the present invention relates to an improvement in a method for manufacturing a semiconductor device having a mesa structure.
〈発明の概要〉
本発明は半導体ウェハーから複数個の半導体素子を作成
する製造方法において、特にメサ形半導体装置の製造に
あたりガラスバシペーションヲ施したメサ溝部をダイシ
ングする工程において、特性に悪影響を及ぼさない様に
上記各半導体素子間を切断分割できる様に上記各半導体
素子間の表面側にはダブルメサ溝を、裏面側にはシング
ルメサ溝を形成するとともに、上記両メサ溝の内部にガ
ラスパシベーション膜を被着し、この半導体ウェ；ツ
バの表面側ダブルメサ溝の中心部に沿って、すなワチカ
ラスパシペーション膜のない箇所より機械的に切断分割
を行なうものでるる。<Summary of the Invention> The present invention relates to a manufacturing method for manufacturing a plurality of semiconductor devices from a semiconductor wafer, in particular, in the process of dicing a mesa groove portion subjected to glass basipation in the manufacturing of a mesa-shaped semiconductor device. A double mesa groove is formed on the front side between each of the semiconductor elements, and a single mesa groove is formed on the back side, so that each of the semiconductor elements can be cut and divided without any problem.A glass passivation film is also formed inside both of the mesa grooves. The semiconductor wafer is then mechanically cut and divided along the center of the double mesa groove on the surface side of the brim, that is, from a location where there is no cracked spasipation film.
〈従来の技術〉
一般に、中小電力用半導体装置のうち、比較的高耐圧が
要求されるメサ型半導体素子等においては、シリコンウ
ェノ・−に異なる導電型不純物を順次拡散した後゛メサ
溝を形成して切断分割しているが、こｎらメサ溝内部に
ガラスパ７ペーション！漢（ガラス保護膜）を被着して
、ＰＮ接合の表［ｆＩ］の安定化を行なっている。<Prior art> In general, in mesa-type semiconductor devices that require a relatively high breakdown voltage among small and medium-sized power semiconductor devices, impurities of different conductivity types are sequentially diffused into a silicon wafer, and then a mesa groove is formed. It is formed and cut and divided, but there are 7 glass perforations inside the mesa groove! A glass protective film is applied to stabilize the front [fI] of the PN junction.
このガラスパシベーション膜は、たとえば第２図に示す
ように、半導体ウエノ・−１状態で形成される。図にお
いて、ガラスパシベーション膜４は、エツチング液で形
成されたメサ溝３内に被着されている。その後、ダイシ
ングブレードＩＩＫより、該メサ溝３内に形成したガラ
スパシベーション膜４と共に半導体ウェハー１の切断分
割を行なっている。なお、５，６．７はメタル電極であ
る。This glass passivation film is formed in a semiconductor wafer-1 state, for example, as shown in FIG. In the figure, a glass passivation film 4 is deposited within a mesa groove 3 formed with an etching solution. Thereafter, the semiconductor wafer 1 is cut and divided together with the glass passivation film 4 formed in the mesa groove 3 using a dicing blade IIK. Note that 5, 6.7 are metal electrodes.
しかしながら、上記従来の方法により切断分割する際は
、しばしばガラスパシベーション膜３にカケ、クラック
等が生じてしまい、半導体素子の電気特性に悪影響をお
よぼすという問題点があった。そこで第３図（ａ） Ｖ
Ｃ示す様に半導体ウェハーｌの両面にダブルメサ溝２．
２′を形成し、切断する際にはダブルメサ溝２．２の中
心部すなわちガラスバンベー７ｇン膜４の無い箇所を機
械的に切断する方法が提案されている。However, when the glass passivation film 3 is cut and divided by the above-mentioned conventional method, chips, cracks, etc. often occur in the glass passivation film 3, which has a problem in that it adversely affects the electrical characteristics of the semiconductor element. Therefore, Fig. 3(a) V
As shown in C, double mesa grooves 2. are formed on both sides of the semiconductor wafer l.
When forming and cutting the double mesa groove 2.2, a method has been proposed in which the central part of the double mesa groove 2.2, that is, the area where the glass membrane 4 is not present, is mechanically cut.
〈発明が解決しようとする問題点〉
しかし、第２図の従来法の問題点を解決すべくなされた
、半導体ウェハーｌの両面にダブルメサ溝２．２ を
形成する方法にあっては、第３図（ｂ） Ｉｔで示す様
に後のダイボンド工程において金属ステム１０上の半田
９が半導体チップ８の周辺に回り込み、これにより半導
体素子の電気特性を劣化させるという問題点を有してい
た。<Problems to be Solved by the Invention> However, in the method of forming double mesa grooves 2.2 on both sides of a semiconductor wafer l, which was designed to solve the problems of the conventional method shown in FIG. As shown by It in Figure (b), there was a problem in that the solder 9 on the metal stem 10 wrapped around the semiconductor chip 8 in the subsequent die bonding process, thereby degrading the electrical characteristics of the semiconductor element.
この発明は上記従来の問題点に鑑みなされたもので、そ
の目的は半導体素子のもつ電気特性を損うこ（Ｊ（ガラ
スパシベーション膜に発生するカケ、クランクを防止で
き、製造歩留りを向上できる半導体装置の製造方法を提
供することにある。This invention was made in view of the above-mentioned conventional problems, and its purpose is to improve the manufacturing yield of a semiconductor device that can prevent cracks and cracks that occur in the glass passivation film and improve the manufacturing yield. The purpose of this invention is to provide a method for manufacturing the same.
く問題点を解決するための手段〉
この発明は、半導体ウェハーの両面のメサ溝部分で切断
分割を行なう半導体装置の製造方法において、表面側は
ダブルメサ構造、かつその裏面側はシングルメサ構造と
して、上記半導体ウニ・・−の両面にそれぞれメサ溝を
形成し、これら両メサ溝内部にガラスパシベーション膜
を被着し、切断分割の際には表面側のダブルメサ溝の中
心部すなわちガラスパシベーション膜のない箇所を切断
分割する方法である。Means for Solving Problems> The present invention provides a method for manufacturing a semiconductor device in which cutting and dividing are performed at mesa groove portions on both sides of a semiconductor wafer, in which the front side has a double mesa structure and the back side has a single mesa structure. Mesa grooves are formed on both sides of the semiconductor sea urchin, respectively, and a glass passivation film is coated inside both mesa grooves, and when cutting and dividing, the central part of the double mesa groove on the front side, where there is no glass passivation film, is formed. This is a method of cutting and dividing parts.
く作 用〉
本発明は上記の様に、半導体ウニ・・−の表面側に形成
したダブルメサ溝の中心部すなわちガラスパシベーショ
ン膜のない箇所を切断している為表［ｆＩｉ １１１１
のガラスパシベーション膜にカケ、クラック等が発生す
ることなく、又裏面側はシングルメサ構造としている為
切断後の工程でグイボンドする際にも半田がチップの周
辺に回り込むことなく、半導体素子の電気特性に悪影響
を及ばさず、製造歩留りを向上させることができる。Effect> As described above, the present invention cuts the central part of the double mesa groove formed on the surface side of the semiconductor sea urchin, that is, the part where there is no glass passivation film.
No chips or cracks will occur in the glass passivation film, and since the back side has a single mesa structure, the solder will not get around the chip when bonding in the post-cutting process, and the electrical characteristics of the semiconductor element will be maintained. It is possible to improve the manufacturing yield without adversely affecting.
なお、半導体ウェハー裏面側のガラスパシベーション膜
に、カケ、クラック等が発生することもあるが、ＭＩＩ
］側のガラスパシベーション膜のカケ。Note that chips, cracks, etc. may occur in the glass passivation film on the back side of the semiconductor wafer, but MII
] Chip in the glass passivation film on the side.
クラック等による半導体素子特性への影響はあまりなか
った。There was little effect on semiconductor device characteristics due to cracks and the like.
く実施例〉 以下、図面を参照してこの発明の一実施例を説明する。Example Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図（ａＪ（ｂ）（ｃ）はそれぞれ本発明ｔて係る半
導体装置の製造工程を示す図である。FIGS. 1A, 1B, and 1C are diagrams showing the manufacturing process of a semiconductor device according to the present invention, respectively.
まず、シリコンウェハーに例えばサイリスクを作成すべ
く適宜不純物拡散を行ない、第１図（ａ）に示すような
半導体ウェハー１を作製する。First, a semiconductor wafer 1 as shown in FIG. 1(a) is manufactured by appropriately diffusing impurities into a silicon wafer to form, for example, a silicon wafer.
次いで、第１図（ｂ）のように、シリコン半導体ウェハ
ー１の表面側にはダブルメサ溝２．２’、・・・を、裏
面、側にはシングルメサ溝３．・・・をそれぞれ形成し
、従来と同様の方法によってこれらの各メサ溝２、２’
、 ３．・・・内部にガラスパシベーション膜４゜・・
・を被着し、さらにメタル電極５．６．７を形成する。Next, as shown in FIG. 1(b), double mesa grooves 2.2', . . . are formed on the front side of the silicon semiconductor wafer 1, and single mesa grooves 3.2', . . . . and form each of these mesa grooves 2, 2' by the same method as in the conventional method.
, 3. ...Glass passivation film 4 degrees inside...
・Furthermore, metal electrodes 5.6.7 are formed.
次に、ダイシングブレード等により機械的に半導体ウェ
ハー１を切断分割するのであるが、この時、第１図（ｂ
Ｊ Ｋ点線で示した箇所、すなわち半導体ウェハーＩの
表面側はダブルメサ溝２．２′間の中心部（ガラスパシ
ベーション膜４のＺｌ／４Ｍ）、かつその裏面側はシン
グルメサ溝３の中心部に沿って切断分割を行な、ｔば、
第１図（ｄに示すようなサイリスクチップ８が得られる
。Next, the semiconductor wafer 1 is mechanically cut and divided using a dicing blade or the like.
The area indicated by the JK dotted line, that is, the front side of the semiconductor wafer I is located at the center between the double mesa grooves 2 and 2' (Zl/4M of the glass passivation film 4), and the back side thereof is located at the center of the single mesa groove 3. Cut and divide along the t,
A thyrisk chip 8 as shown in FIG. 1(d) is obtained.
第１図（ｃ）は上記の方法により作製されたサイリスタ
テップ８を半田９を用いて金属ステム１０にダイボンド
したものである。FIG. 1(c) shows a thyristor tip 8 produced by the above method die-bonded to a metal stem 10 using solder 9. As shown in FIG.
本発明は上記のように、半導体ウェハー１の表面側はそ
のダブルメサ溝２．２′間の中心部すなわちガラスパシ
ベーション膜４のない箇所を切断しているため、表面側
のガラスパシベーション膜４にカケ、クラック等が発生
することがなく、また裏面側はシングルメサ溝のほぼ中
心部で切断するため、切断後の工程でサイリスタチップ
８をダイボンドした際にも、半田９がチップ８０周辺に
回り込むことがない。As described above, in the present invention, since the front side of the semiconductor wafer 1 is cut at the center between the double mesa grooves 2 and 2', that is, the area where the glass passivation film 4 is not present, the glass passivation film 4 on the front side is cut. , cracks etc. do not occur, and since the back side is cut almost at the center of the single mesa groove, even when the thyristor chip 8 is die-bonded in the process after cutting, the solder 9 does not wrap around the chip 80. There is no.
なおこの実施例では、サイリスタを用いたが他の半導体
素子にも本発明を実施することカニできる。Although a thyristor is used in this embodiment, the present invention can also be applied to other semiconductor devices.
〈発明の効果〉
この発明の方法によれば、メサ型半導体素子等にお＾ラ
スパシベーション膜に生じるカケやクラック等金防ぐこ
とができる。そしてその結果、カケやクラック等が原因
であった半導体素子の電気特性への悪影響も防がれる。<Effects of the Invention> According to the method of the present invention, it is possible to prevent chips, cracks, and the like from occurring in the raspivation film of mesa-type semiconductor devices and the like. As a result, the adverse effects on the electrical characteristics of the semiconductor element caused by chips, cracks, etc. can also be prevented.
ざらに、ダイボンド工程においては半田が半導体素子の
周辺に回り込むことがなく、これによって半導体素子の
電気特性を劣化させることもなく、製造歩留りを向上で
きる。In general, in the die bonding process, solder does not wrap around the semiconductor element, thereby preventing deterioration of the electrical characteristics of the semiconductor element and improving manufacturing yield.
第１図（ａ）（ｂ）（ｃ）は、本発明に係る一実施例の
工程図で、同図（ａ）は不純物拡散の完了した半導体ウ
ェハーの断面図、同図（ｂ）はガラスパシベーション膜
の被着され之半導体つエノ・−の断面図、同図（ｃ）は
半導体素子を半田により金属ステムにダイボンドした際
の断面図、第２図は従来法による第１図に相当する断面
図、第３図（ａ）及び（ｂ）は他の従来法による第１図
（ｂ）及び（ｃ）ｔ／ｃそれぞれ相当する断面図である
。
ｌ・半導体ウェハー、２．２’： ダブルメサ溝、３ニ
シンゲルメサ溝、４ニガラスパシベーシヨン膜。
代理人 弁理士 杉 山 毅 至（他１名）−Ｃ）
−どゴ
（ａ）
（ｂ）
（Ｃ）
第１図
畜２図
第３図FIGS. 1(a), 1(b), and 1(c) are process diagrams of one embodiment of the present invention, in which FIG. 1(a) is a cross-sectional view of a semiconductor wafer after impurity diffusion has been completed, and FIG. A cross-sectional view of the semiconductor element on which the passivation film is deposited. Figure (c) is a cross-sectional view when the semiconductor element is die-bonded to the metal stem by solder. Figure 2 corresponds to Figure 1 using the conventional method. The sectional views in FIGS. 3(a) and 3(b) are sectional views corresponding to FIGS. 1(b) and 1(c) t/c, respectively, according to another conventional method. l. Semiconductor wafer, 2.2': double mesa groove, 3 herring mesa groove, 4 herring gel passivation film. Agent Patent attorney Takeshi Sugiyama (and 1 other person) -C) -Dogo (a) (b) (C) Figure 1 Figure 2 Figure 3
Claims (1)
記半導体ウェハーの両面のメサ溝部分で上記各半導体素
子間の切断分割を行なう半導体装置の製造方法において
、上記半導体ウェハーの表面側にはダブルメサ溝を、裏
面側にはシングルメサ溝を夫々形成し、これらのメサ溝
の内部にガラスパシベーション膜を被着し、上記半導体
ウェハーの表面側のダブルメサ溝間の中心部に沿って機
械的に切断分割を行なうことを特徴とする半導体装置の
製造方法。1. In a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor wafer, and the semiconductor elements are cut and divided using mesa grooves on both sides of the semiconductor wafer, a double mesa is formed on the front side of the semiconductor wafer. A groove and a single mesa groove are formed on the back side, a glass passivation film is deposited inside these mesa grooves, and the semiconductor wafer is mechanically cut along the center between the double mesa grooves on the front side. A method of manufacturing a semiconductor device characterized by performing division.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61020454A JPS62179128A (en) | 1986-01-31 | 1986-01-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61020454A JPS62179128A (en) | 1986-01-31 | 1986-01-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62179128A true JPS62179128A (en) | 1987-08-06 |
Family
ID=12027514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61020454A Pending JPS62179128A (en) | 1986-01-31 | 1986-01-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62179128A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1047025C (en) * | 1995-03-17 | 1999-12-01 | 山东师范大学 | Glassivation method for large mesa power semiconductor device |
| US6579782B2 (en) * | 1999-12-24 | 2003-06-17 | Stmicroelectronics S.A. | Vertical power component manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5310273A (en) * | 1976-07-15 | 1978-01-30 | Mitsubishi Electric Corp | Mesa type semiconductor device |
-
1986
- 1986-01-31 JP JP61020454A patent/JPS62179128A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5310273A (en) * | 1976-07-15 | 1978-01-30 | Mitsubishi Electric Corp | Mesa type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1047025C (en) * | 1995-03-17 | 1999-12-01 | 山东师范大学 | Glassivation method for large mesa power semiconductor device |
| US6579782B2 (en) * | 1999-12-24 | 2003-06-17 | Stmicroelectronics S.A. | Vertical power component manufacturing method |
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