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JPH05259274A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH05259274A
JPH05259274A JP4001192A JP4001192A JPH05259274A JP H05259274 A JPH05259274 A JP H05259274A JP 4001192 A JP4001192 A JP 4001192A JP 4001192 A JP4001192 A JP 4001192A JP H05259274 A JPH05259274 A JP H05259274A
Authority
JP
Japan
Prior art keywords
scribe street
pellet
groove
film
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4001192A
Other languages
Japanese (ja)
Inventor
Tokiyasu Aoyanagi
時康 青柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4001192A priority Critical patent/JPH05259274A/en
Publication of JPH05259274A publication Critical patent/JPH05259274A/en
Withdrawn legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE:To prevent short-circuiting of elements due to sagging of a connection wire or a different matter by including a scribe street provided on an upper face of a periphery of a semiconductor pellet and an insulation film provided on an upper part of a pellet side. CONSTITUTION:A silicon oxide film 2 is formed on a silicon substrate 1, and after a window is opened on the silicon oxide film 2, impurities are diffused to form a diffusion layer. Then a metal film is deposited on a surface including the window and etched to form an electrode 4, and a scribe street 5 is formed in the periphery of an element region. Then after a groove 6 is formed in the scribe street 5, an insulation film 7 such as a silicon oxide film or a silicon nitride film is formed selectively in the scribe street 5 including the groove 6. Thus short-circuiting of elements caused by contact with the electrode on the pellet surface due to sagging of a connection wire or a different matter can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体ペレットに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor pellet.

【0002】[0002]

【従来の技術】従来の半導体装置は、図3に示すよう
に、シリコン基板1の表面に設けた酸化シリコン膜3
と、酸化シリコン膜3に設けた窓よりシリコン基板1の
反対導電型の不純物を導入して形成した拡散層2と、拡
散層2に接続して設けた電極4によりプレーナ型の半導
体素子を形成し、ダイヤモンドダイシングソーを用いて
切断し、半導体ペレットを形成しており、スクライブス
トリート及び切断されたペレットの側面にシリコン基板
1が露出している。
2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor device has a silicon oxide film 3 formed on a surface of a silicon substrate 1.
And a diffusion layer 2 formed by introducing an impurity of the opposite conductivity type of the silicon substrate 1 through a window provided in the silicon oxide film 3 and an electrode 4 connected to the diffusion layer 2 to form a planar semiconductor element. Then, it is cut using a diamond dicing saw to form semiconductor pellets, and the silicon substrate 1 is exposed on the scribe streets and the side surfaces of the cut pellets.

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
では、スクライブストリート及び側面にシリコンの基板
の表面が露出しているため、金シリコンの共晶を用いて
パッケージ容器又はリードフレームにペレットをマウン
トする工程でペレットの側面及びスクライブストリート
に金シリコンの共晶膜が這上がるという問題点があっ
た。
In this conventional semiconductor device, since the surface of the silicon substrate is exposed on the scribe streets and the side surfaces, the pellets are mounted on the package container or the lead frame by using the eutectic of gold silicon. In the process, the gold-silicon eutectic film crawls on the side surface of the pellet and on the scribe street.

【0004】又、ダイオード,トランジスタの様な縦型
の素子では、スクライブストリート及びペレットの側面
は、ペレット裏面の電極と同電位になっているため、接
続ワイヤの垂下りや異物の介在によりペレット表面の電
極と接触すると、素子の短絡が発生するという問題点が
あった。
In a vertical device such as a diode or a transistor, the scribe street and the side surface of the pellet have the same potential as the electrode on the back surface of the pellet. There has been a problem that the element is short-circuited when it comes into contact with the electrode.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体ペレットの周縁部上面に設けたスクライブストリ
ート及びそれに続くペレットの側面の上部に設けた絶縁
膜を有する。
The semiconductor device of the present invention comprises:
It has a scribe street provided on the upper surface of the peripheral edge of the semiconductor pellet and an insulating film provided on the side surface of the pellet following the scribe street.

【0006】本発明の半導体装置の製造方法は、半導体
基板上に素子領域及び前記素子領域の周囲にスクライブ
ストリートを形成する工程と、前記スクライブストリー
トに溝を形成する工程と、前記スクライブストリート及
び溝の表面に絶縁膜を形成する工程と、前記溝の下部を
切断して個々の半導体ペレットに分割する工程とを含ん
で構成される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a scribe street on a semiconductor substrate around the element region, a step of forming a groove in the scribe street, the scribe street and the groove. A step of forming an insulating film on the surface of, and a step of cutting the lower part of the groove to divide it into individual semiconductor pellets.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0008】図1(a)〜(c)は本発明の第1の実施
例の製造方法を説明するための工程順に示した半導体ペ
レットの断面図である。なお、説明を単純化するためダ
イオードの場合について述べる。
1 (a) to 1 (c) are cross-sectional views of a semiconductor pellet showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention. The case of a diode will be described for simplification of description.

【0009】まず、図1(a)に示すように、シリコン
基板1の上に酸化シリコン膜2を形成し、フォトリソグ
ラフィ技術及びエッチング技術を用いて酸化シリコン膜
2に窓をあけた後酸化シリコン膜2をマススとしてシリ
コン基板1と反対導電型の不順物を拡散し拡散層2を形
成する。次に、窓を含む表面に蒸着技術を用い金属膜を
堆積してエッチングし、電極4を形成し、素子領域の周
囲にスクライブストリート5を形成する。
First, as shown in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1, a window is opened in the silicon oxide film 2 by using a photolithography technique and an etching technique, and then the silicon oxide film 2 is formed. The film 2 is used as a mass to diffuse the irregular substance of the opposite conductivity type to the silicon substrate 1 to form the diffusion layer 2. Next, a metal film is deposited on the surface including the window using a vapor deposition technique and etched to form an electrode 4, and a scribe street 5 is formed around the element region.

【0010】次に、図1(b)に示すように、スクライ
ブストリート5に、ダイサーを使用し、シリコン基板1
の厚さの1/3〜2/3程度の深さの溝6を形成した
後、CVD法等により溝6を含むスクライブストリート
に選択的に酸化シリコン膜又は窒化シリコン膜等の絶縁
膜7を形成する。
Next, as shown in FIG. 1 (b), a dicer is used on the scribe street 5, and the silicon substrate 1
After forming the groove 6 having a depth of about 1/3 to 2/3 of the thickness of the silicon oxide film, an insulating film 7 such as a silicon oxide film or a silicon nitride film is selectively formed on the scribe street including the groove 6 by a CVD method or the like. Form.

【0011】次に、図1(c)に示すように、シリコン
基板1を個々のペレットに分割する。
Next, as shown in FIG. 1C, the silicon substrate 1 is divided into individual pellets.

【0012】図2は本発明の第2の実施例を説明するた
めの半導体ペレットの断面図である。
FIG. 2 is a sectional view of a semiconductor pellet for explaining the second embodiment of the present invention.

【0013】図2に示すように、スクライブストリート
5にエッチング法を用いて溝8を形成した以外は第1の
実施例と同様の構成を有しており、溝8が傾斜を有して
いるため、第1の実施例に比較し溝8の側面に絶縁膜7
が被着し易いという利点がある。
As shown in FIG. 2, the structure is the same as that of the first embodiment except that the groove 8 is formed in the scribe street 5 by using the etching method, and the groove 8 is inclined. Therefore, the insulating film 7 is formed on the side surface of the groove 8 as compared with the first embodiment.
Has the advantage that it is easy to apply.

【0014】[0014]

【発明の効果】以上説明したように本発明は半導体、ペ
レットのスクライブストリートと、それに続く側面の一
部に絶縁膜を形成することにより、金シリコンの共晶を
用いてペレットをマウントする際の金シリコン共晶膜の
這上がりを抑え、万一、接続ワイヤの垂下りや異物によ
りペレットの表面電極とスクライブストリート及びペレ
ットの側面の上部が接触しても素子の短絡を防止できる
という効果を有する。
As described above, according to the present invention, when a scribe street of a semiconductor and a pellet and an insulating film is formed on a part of the side surface subsequent to the scribe street, the pellet is mounted by using a gold-silicon eutectic crystal. The gold-silicon eutectic film is prevented from climbing up, and even if the surface electrode of the pellet comes into contact with the scribe street or the upper portion of the side surface of the pellet due to a drop of the connecting wire or a foreign matter, it is possible to prevent a short circuit of the element.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の製造方法を説明するた
めの工程順に示した半導体ペレットの断面図。
1A to 1C are cross-sectional views of a semiconductor pellet showing steps in a manufacturing process for explaining a manufacturing method according to a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための半導体
ペレットの断面図。
FIG. 2 is a sectional view of a semiconductor pellet for explaining a second embodiment of the present invention.

【図3】従来の半導体装置の一例を示す半導体ペレット
の断面図。
FIG. 3 is a sectional view of a semiconductor pellet showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 拡散層 3 酸化シリコン膜 4 電極 5 スクライブストリート 6,8 溝 7 絶縁膜 1 Silicon substrate 2 Diffusion layer 3 Silicon oxide film 4 Electrode 5 Scribe street 6, 8 Groove 7 Insulating film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ペレットの周縁部上面に設けたス
クライブストリート及びそれに続くペレットの側面の上
部に設けた絶縁膜を有することを特徴とする半導体装
置。
1. A semiconductor device comprising a scribe street provided on an upper surface of a peripheral portion of a semiconductor pellet and an insulating film provided on an upper portion of a side surface of the pellet following the scribe street.
【請求項2】 半導体基板上に素子領域及び前記素子領
域の周囲にスクライブストリートを形成する工程と、前
記スクライブストリートに溝を形成する工程と、前記ス
クライブストリート及び溝の表面に絶縁膜を形成する工
程と、前記溝の下部を切断して個々の半導体ペレットに
分割する工程とを含むことを特徴とする半導体装置の製
造方法。
2. A device region and a scribe street formed around the device region on a semiconductor substrate, a groove formed in the scribe street, and an insulating film formed on the surface of the scribe street and the groove. A method of manufacturing a semiconductor device, comprising: a step of cutting the lower portion of the groove to divide into individual semiconductor pellets.
JP4001192A 1992-02-27 1992-02-27 Semiconductor device and its manufacture Withdrawn JPH05259274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4001192A JPH05259274A (en) 1992-02-27 1992-02-27 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4001192A JPH05259274A (en) 1992-02-27 1992-02-27 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH05259274A true JPH05259274A (en) 1993-10-08

Family

ID=12568970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4001192A Withdrawn JPH05259274A (en) 1992-02-27 1992-02-27 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH05259274A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825076A (en) * 1996-07-25 1998-10-20 Northrop Grumman Corporation Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique
WO2000059050A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
JP2001044141A (en) * 1999-07-30 2001-02-16 Nippon Sheet Glass Co Ltd Method for cutting semiconductor substrate
US6870248B1 (en) * 1999-06-07 2005-03-22 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
JP2006019427A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor chip, manufacturing method thereof, and semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825076A (en) * 1996-07-25 1998-10-20 Northrop Grumman Corporation Integrated circuit non-etch technique for forming vias in a semiconductor wafer and a semiconductor wafer having vias formed therein using non-etch technique
WO2000059050A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
US6573157B1 (en) 1999-03-31 2003-06-03 Seiko Epson Corporation Method of manufacturing semiconductor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
KR100416174B1 (en) * 1999-03-31 2004-01-24 세이코 엡슨 가부시키가이샤 Method of manufacturing semiconductor device
US6794746B2 (en) 1999-03-31 2004-09-21 Seiko Epson Corporation Method of manufacturing semiconductor device, semiconductor device, narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
US6870248B1 (en) * 1999-06-07 2005-03-22 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US7138298B2 (en) 1999-06-07 2006-11-21 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US7262490B2 (en) 1999-06-07 2007-08-28 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US7339264B2 (en) 1999-06-07 2008-03-04 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
JP2001044141A (en) * 1999-07-30 2001-02-16 Nippon Sheet Glass Co Ltd Method for cutting semiconductor substrate
JP2006019427A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor chip, manufacturing method thereof, and semiconductor device

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518