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JPS567471A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS567471A
JPS567471A JP8370479A JP8370479A JPS567471A JP S567471 A JPS567471 A JP S567471A JP 8370479 A JP8370479 A JP 8370479A JP 8370479 A JP8370479 A JP 8370479A JP S567471 A JPS567471 A JP S567471A
Authority
JP
Japan
Prior art keywords
wafer
groove
cut
layer
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8370479A
Other languages
Japanese (ja)
Inventor
Takeshi Yamamoto
Kiyoshi Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8370479A priority Critical patent/JPS567471A/en
Publication of JPS567471A publication Critical patent/JPS567471A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

Landscapes

  • Bipolar Transistors (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To increase the chip cut-out efficiency by cutting out so that the outer configuration of each of chips obtained when a plurality of active regions each including a P-N junction within a semiconductor wafer are formed circularly and cut them individually, becomes a regular hexagon. CONSTITUTION:Each of active regions which produce PE layer 11, PB layer 12, and NE layer 13 by diffusion is formed circularly in an N-type Si wafer 10, and is subjected to selective etching. A circular groove 14 which encircles the active region at both front and back surfaces of the wafer 10 is bored, and P-N junctions 15 and 16 are exposed in the above groove. Next, a glass insulating film 17 is buried in the groove 14 to protect the junctions 15 and 16, and the anode, cathode and gate electrodes 18-20 are metalized on the front and back sides of the wafer 10. Thereafter, the wafer 10 is cut into a regular hexagon from the outer side of the groove 14 to form respective thyristor chips. By this procedure, it can be pelletized by a scriber and a saw dicer which can perform straight line cutting only. Accordingly, the chip cut-out efficiency becomes high while the characteristic of the circular chip is left as it is.
JP8370479A 1979-06-29 1979-06-29 Semiconductor device Pending JPS567471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8370479A JPS567471A (en) 1979-06-29 1979-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8370479A JPS567471A (en) 1979-06-29 1979-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS567471A true JPS567471A (en) 1981-01-26

Family

ID=13809874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8370479A Pending JPS567471A (en) 1979-06-29 1979-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS567471A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
US5665655A (en) * 1992-12-29 1997-09-09 International Business Machines Corporation Process for producing crackstops on semiconductor devices and devices containing the crackstops
CN112271215A (en) * 2020-11-17 2021-01-26 国家电网有限公司 A fully controlled thyristor chip and design method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829820U (en) * 1971-08-07 1973-04-12
JPS5345987A (en) * 1976-10-06 1978-04-25 Mitsubishi Electric Corp Semiconductor integrated circuit element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4829820U (en) * 1971-08-07 1973-04-12
JPS5345987A (en) * 1976-10-06 1978-04-25 Mitsubishi Electric Corp Semiconductor integrated circuit element

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US5341024A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5665655A (en) * 1992-12-29 1997-09-09 International Business Machines Corporation Process for producing crackstops on semiconductor devices and devices containing the crackstops
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
CN112271215A (en) * 2020-11-17 2021-01-26 国家电网有限公司 A fully controlled thyristor chip and design method thereof

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