JPS6189653A - How to attach the lead pin - Google Patents
How to attach the lead pinInfo
- Publication number
- JPS6189653A JPS6189653A JP21171784A JP21171784A JPS6189653A JP S6189653 A JPS6189653 A JP S6189653A JP 21171784 A JP21171784 A JP 21171784A JP 21171784 A JP21171784 A JP 21171784A JP S6189653 A JPS6189653 A JP S6189653A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- pin
- circuit board
- lead pin
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 description 11
- 238000010304 firing Methods 0.000 description 5
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 238000007639 printing Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910002710 Au-Pd Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BBKFSSMUWOMYPI-UHFFFAOYSA-N gold palladium Chemical compound [Pd].[Au] BBKFSSMUWOMYPI-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は効率よくリードピンをセラミック回路基板に装
着する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for efficiently attaching lead pins to a ceramic circuit board.
電算機の処理能力を向上するためにＩＣやＬＳＩなどの
半導体装置は小形化と大容量化とが進められているが同
時に実装方法も改良されつ−ある。In order to improve the processing power of computers, semiconductor devices such as ICs and LSIs are becoming smaller and larger in capacity, and at the same time, their mounting methods are also being improved.
すなわち従来の半導体装置はチップ毎に多層配線が施さ
れたセラミック基板εこ装着してハーメチックシールす
るパッケージ構造がとられており、か＼る半導体装置を
プリント配線基板上にパターン形成しであるランド或い
はスルーホールに装着する実装方法がとられていた。In other words, conventional semiconductor devices have a package structure in which each chip is mounted on a ceramic substrate with multilayer wiring and hermetically sealed. Alternatively, a mounting method has been used in which it is mounted in a through hole.
然し今後の形態として複数個のＬＳＩ素子をセラミック
多層配線基板に搭載してＬＳＩモジールを作り、これを
プリント配線基板に装着する構成がとられつ＼ある。However, as a future form, a configuration is being adopted in which a plurality of LSI elements are mounted on a ceramic multilayer wiring board to create an LSI module, and this is mounted on a printed wiring board.
第２図はか＼る実装形態を示すもので複数個のＬＳＩ
１がセラミックパッケージ２を用いてセラミック回路
基板３に搭載されており、一方セラミック回路基板（、
以下略して基板）３はビヤホールに装着しであるリード
ピン４を用いてプリント配線基板５のスルーホール６に
挿入し、半田付けすることにより回路接続が行われてい
る。Figure 2 shows the implementation form, which includes multiple LSIs.
1 is mounted on a ceramic circuit board 3 using a ceramic package 2, while a ceramic circuit board (,
A circuit board (hereinafter abbreviated as a board) 3 is inserted into a through hole 6 of a printed wiring board 5 using a lead pin 4 which is attached to a via hole, and is connected to a circuit by soldering.
ここでｔ、ｓｒ ｉは膨大な素子が集積されて形成され
ているために端子数が多いが、ＬＳＩモジュールは複数
個のＬＳＩが搭載されているためにリードピン４の装着
数は莫大であり、例えば１０ｃｍ角の基板３に２０００
〜３０００本のり−ドピン４の装着が必要となる。Here, t, sr i has a large number of terminals because it is formed by integrating a huge number of elements, but since an LSI module is equipped with multiple LSIs, the number of attached lead pins 4 is enormous. For example, 2000 for a 10cm square board 3.
It is necessary to install ~3000 glue-doped pins 4.
この場合、リー１′ビン４の直径は約０．１ｉｍと小さ
く、これが密集して設けられることから多数のピンの基
板３への位置合わせと装着は極めて工数を要し繊細な作
業となる。In this case, the diameter of the Lie 1' pins 4 is as small as about 0.1 mm, and since they are arranged closely together, positioning and attaching a large number of pins to the substrate 3 requires an extremely large number of man-hours and is a delicate task.
本発明は多数のリートピンを効率よ（基板に接合する方
法に関するものである。The present invention relates to a method for efficiently bonding a large number of lead pins to a substrate.
基板上にスクリーン印刷或いは写真食刻技術（ホトリソ
グラフィ）を用いて形成した多数のバッドにリードピン
を正確に位置合わせし、溶着するには何らかの接合冶具
を用いる必要がある。It is necessary to use some type of bonding jig to accurately align and weld the lead pins to a large number of pads formed on the substrate using screen printing or photolithography.
この方法として基板焼成を行う前の段階で位置合わせ用
の穴を設けることが試みられた。As a method for this purpose, an attempt has been made to provide holes for positioning at a stage before firing the substrate.
すなわらグリーンノートの段階で基板の四隅に位置決め
用の穴を設けて焼成を行い、一方四隅にガ・イドピンが
あり、上にマトリックス状に配列した多数のリードピン
挿入口を備えたピン接合冶具を？＄備しておき、焼成の
終わった基板はバット部の印刷焼成とこの部分への半田
ペーストの印刷が終わった後、ビン接合冶具のガイドピ
ンを位置決め用の穴に挿入し、リードピンを位置決めす
ることが試みられた。In other words, at the Green Note stage, positioning holes are made in the four corners of the board and firing is performed, while there are guide pins in the four corners, and a pin bonding jig with a large number of lead pin insertion holes arranged in a matrix on the top. of? Prepare $, and after printing the butt part of the printed board and printing the solder paste on this part, insert the guide pin of the bottle joining jig into the positioning hole and position the lead pin. This was attempted.
然しなから、グリンノートは焼成に際してかなりの収縮
を生じ、また収縮の程度が場所により異なるためにビン
接合冶具のガイドビンを精度良く挿入することは困難で
あり、一方位置決め用の穴を大きくしてガイドビンの挿
入を容易にするとリードピンの位置ずれのためにバッド
との接合が悪くなると云う問題があった。However, Greennote shrinks considerably during firing, and the degree of shrinkage varies depending on the location, making it difficult to accurately insert the guide bin of the bin joining jig. However, if the guide pin is made easier to insert, there is a problem in that the lead pin is misaligned, resulting in poor bonding with the pad.
以上記したように基板に設けられているビヤホール位置
にリードピンを正確に装着するには基板面積が小さく、
一方リードビンの数が多いために位置合わせが難しいこ
とが問題である。As mentioned above, the board area is small in order to accurately attach the lead pins to the via holes provided on the board.
On the other hand, there is a problem in that alignment is difficult due to the large number of lead bins.
上記の問題は半導体素子を搭載したセラミ、・り回路基
板をプリント配ｖＡ基板へ回路接続するのに使用するリ
ードピンの該セラミック回路基板へのピン装着が、該回
路基板の四隅に位置決め用の穴を設け、該穴にリードビ
ン挿入口を備えたピン接合治具のガイドビンを挿入し、
位置合わせして接合することを特徴とするリードピンの
装着方法により解決することができる。The problem mentioned above is that the lead pins used to connect the ceramic circuit board with semiconductor elements to the printed circuit board must be attached to the ceramic circuit board using the positioning holes in the four corners of the circuit board. A guide bin of a pin joining jig equipped with a lead bin insertion port is inserted into the hole,
This problem can be solved by a lead pin mounting method characterized by positioning and joining.
本発明は基板に対する穴開けなどの切削作業がＮＣ（数
値制御）技術の進歩により極めそ精度よく且つ容易にで
きることから、焼成の終わった法仮に穴開すして位置決
め用の穴を設けることより高精度の位置合わせを行うも
のである。In the present invention, cutting work such as drilling holes in the substrate can be performed with extremely high accuracy and ease due to advancements in NC (numerical control) technology, so the cutting work such as drilling holes in the substrate can be performed with high precision and easily. This is to perform accurate positioning.
第１図（Ａ）〜（Ｆ）は本発明を実施したり−ドピンの
装着工程を示すものである。FIGS. 1(A) to 1(F) illustrate the mounting process of a dowel according to the present invention.
ここで実施例として用いた基板３はガラスセラミックス
よりなる多層配線裁板でリードビン装着位置にはビヤホ
ールを通じて回路接続が行われている。The substrate 3 used in this embodiment is a multilayer wiring board made of glass ceramics, and a circuit connection is made through a via hole at a position where a lead bin is attached.
第１図（Ａ）はこのリードピン装着位置にスクリーン印
刷法により金・パラジウム（Ａｕ−Ｐｄ）ペーストを印
刷してバッド６を形成する状態を示しており、９５０℃
で１０分間に互って大気中で焼成することによりバッド
１２が形成される。Figure 1 (A) shows a state in which a pad 6 is formed by printing gold-palladium (Au-Pd) paste at the lead pin attachment position by screen printing, and the temperature is 950°C.
The pads 12 are formed by firing in the atmosphere for 10 minutes.
ここで本実施例の場合、バッド１２の寸法は０．３１角
で、バッド１２の相互間のピッチは１．２７ｍｍである
。In the case of this embodiment, the dimensions of the pads 12 are 0.31 square, and the pitch between the pads 12 is 1.27 mm.
次に基十反３の四隅にダイヤモンドドリルを用いて直径
３ ｍｍの位置決め用の穴７を開ける（同図Ｂ）。Next, use a diamond drill to drill holes 7 for positioning with a diameter of 3 mm in the four corners of the base 3 (Figure B).
次にバッド１２の上に金・錫（八ｕ−３ｎ）ペースト８
をスクリーン印刷して溶着の前処理を行う （同図Ｃ）
。Next, gold/tin (8u-3n) paste 8 on top of the bad 12
Perform pre-treatment for welding by screen printing (C in the same figure)
.
次にこの位置決め用の穴７に予め別にＹ＄備したピン接
合治具９のガイドビン１０を挿入する（同図Ｄ）。Next, the guide pin 10 of the pin joining jig 9, which is separately prepared in advance by Y$, is inserted into this positioning hole 7 (D in the same figure).
ここでビン接合冶具９の金属面にはリードピン挿入口１
１が正確に穴開けされている。Here, the metal surface of the bottle joining jig 9 has a lead pin insertion opening 1.
1 is accurately drilled.
次にこのリードピン挿入口１１にリードピン４を順々に
挿入してゆく。Next, the lead pins 4 are sequentially inserted into the lead pin insertion opening 11.
ここで本実施例の場合、リードピン４の寸法は直径Ｑ、
ｌａｗ、 長さ５１１で燐青銅製であり、これにＰｄ−
Ａｕメッキが施されている。In the case of this embodiment, the dimensions of the lead pin 4 are diameter Q,
It is made of phosphor bronze and has a length of 511 mm, and is coated with Pd-
Au plating is applied.
このようにリートピン４を挿入し、位置合わせが終わっ
た基板３は温度約３５０°Ｃに保持した炉の中を通すこ
とによりバッド１２との溶着が行われる（同図Ｅ）。After the leet pins 4 have been inserted and the substrate 3 has been aligned in this manner, the substrate 3 is passed through a furnace maintained at a temperature of about 350° C. to be welded to the pad 12 (see E in the same figure).
その後ピン接合治具９を取り除くことによってリードピ
ン４の装着作業が完了する（同図Ｆ）。Thereafter, by removing the pin joining jig 9, the work of attaching the lead pin 4 is completed (FIG. F).
このように焼成の終わった基板を切削して位置決め用の
穴を設けることにより位置精度の良いリートピンの装着
を行うことができる。By cutting the substrate after firing in this way and providing holes for positioning, it is possible to attach the leet pin with high positional accuracy.
以上記したように本発明の実施により位置合わせ精度が
悪かった従来の欠点が無くなり、リードピン装着作業を
容易に行うことができる。As described above, by carrying out the present invention, the conventional drawback of poor positioning accuracy is eliminated, and the work of attaching lead pins can be easily performed.
第１図（Ａ）〜（Ｆ）は本発明に係るリードピン装着工
程を説明する断面図、
第２図はプリント配線基板への実装状態を示す断面図、
である。
図において、
１はＬＳＩ、 ３はセラミック回路基板、
４はリードピン、 ５はプリント配線基板、６は
スルーホール、 ７は位置決め用の穴、９はピン接続
冶具、 ｌＯはガイドピン、１１はリードピン挿入口
、１２はパッド、である。FIGS. 1A to 1F are cross-sectional views illustrating a lead pin mounting process according to the present invention, and FIG. 2 is a cross-sectional view showing a mounting state on a printed wiring board. In the figure, 1 is an LSI, 3 is a ceramic circuit board,
4 is a lead pin, 5 is a printed wiring board, 6 is a through hole, 7 is a positioning hole, 9 is a pin connection jig, IO is a guide pin, 11 is a lead pin insertion opening, and 12 is a pad.
Claims (1)
配線基板へ回路接続するのに使用するリードピンの該セ
ラミック回路基板へのピン装着が、該回路基板の四隅に
位置決め用の穴を設け、該穴にリードピン挿入口を備え
たピン接合治具のガイドピンを挿入し、位置合わせして
接合することを特徴とするリードピンの装着方法。Lead pins used to connect a ceramic circuit board on which a semiconductor element is mounted to a printed wiring board are attached to the ceramic circuit board by providing positioning holes at the four corners of the circuit board and inserting the lead pins into the holes. A lead pin mounting method characterized by inserting a guide pin of a pin joining jig with a mouth, aligning and joining.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21171784A JPS6189653A (en) | 1984-10-09 | 1984-10-09 | How to attach the lead pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21171784A JPS6189653A (en) | 1984-10-09 | 1984-10-09 | How to attach the lead pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6189653A true JPS6189653A (en) | 1986-05-07 |
Family
ID=16610430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21171784A Pending JPS6189653A (en) | 1984-10-09 | 1984-10-09 | How to attach the lead pin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6189653A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2629271A1 (en) * | 1988-03-25 | 1989-09-29 | Thomson Hybrides Microondes | DEVICE FOR INTERCONNECTING AND PROTECTING A BULK MICROFREQUENCY COMPONENT BLEACH |
| JPH02106062A (en) * | 1988-10-14 | 1990-04-18 | Mitsubishi Electric Corp | Semiconductor device |
| US7597232B2 (en) * | 2005-09-14 | 2009-10-06 | Samsung Electro-Mechanics Co., Ltd. | Apparatus for applying conductive paste onto electronic component |
-
1984
- 1984-10-09 JP JP21171784A patent/JPS6189653A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2629271A1 (en) * | 1988-03-25 | 1989-09-29 | Thomson Hybrides Microondes | DEVICE FOR INTERCONNECTING AND PROTECTING A BULK MICROFREQUENCY COMPONENT BLEACH |
| US4996588A (en) * | 1988-03-25 | 1991-02-26 | Thomson Hybrides Et Microondes | Device for interconnection and protection of a bare microwave component chip |
| JPH02106062A (en) * | 1988-10-14 | 1990-04-18 | Mitsubishi Electric Corp | Semiconductor device |
| US7597232B2 (en) * | 2005-09-14 | 2009-10-06 | Samsung Electro-Mechanics Co., Ltd. | Apparatus for applying conductive paste onto electronic component |
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